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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.speed.log] - Blame information for rev 62

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1 62 olivier.gi 
#####################################################################################
2 
#                            START SYNTHESIS (SPEED optimized)
3 
#====================================================================================
4 
# spartan3 (xc3s400pq208), speedgrade: -4
5 
#====================================================================================
6 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
7 
#     12          10          0         0            0          0            0
8 
#====================================================================================
9 
Clock to Setup on destination clock dco_clk
10 
---------------+---------+---------+---------+---------+
11 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
12 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
13 
---------------+---------+---------+---------+---------+
14 
dco_clk        |   33.265|         |         |    1.564|
15 
---------------+---------+---------+---------+---------+
16 
 
17 
====================================================================================
18 
Device utilization summary:
19 
---------------------------
20 
 
21 
Selected Device : 3s400pq208-4
22 
 
23 
 Number of Slices:                      923  out of   3584    25%
24 
 Number of Slice Flip Flops:            477  out of   7168     6%
25 
 Number of 4 input LUTs:               1761  out of   7168    24%
26 
 Number of IOs:                          80
27 
 Number of bonded IOBs:                  79  out of    141    56%
28 
 Number of BRAMs:                         6  out of     16    37%
29 
 Number of GCLKs:                         1  out of      8    12%
30 
 
31 
---------------------------
32 
 
33 
====================================================================================
34 
#                            SYNTHESIS DONE
35 
#####################################################################################
36 
 
37 
#####################################################################################
38 
#                            START SYNTHESIS (SPEED optimized)
39 
#====================================================================================
40 
# spartan3 (xc3s400pq208), speedgrade: -5
41 
#====================================================================================
42 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
43 
#     12          10          0         0            0          0            0
44 
#====================================================================================
45 
Clock to Setup on destination clock dco_clk
46 
---------------+---------+---------+---------+---------+
47 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
48 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
49 
---------------+---------+---------+---------+---------+
50 
dco_clk        |   30.586|         |         |    1.361|
51 
---------------+---------+---------+---------+---------+
52 
 
53 
====================================================================================
54 
Device utilization summary:
55 
---------------------------
56 
 
57 
Selected Device : 3s400pq208-5
58 
 
59 
 Number of Slices:                      920  out of   3584    25%
60 
 Number of Slice Flip Flops:            477  out of   7168     6%
61 
 Number of 4 input LUTs:               1755  out of   7168    24%
62 
 Number of IOs:                          80
63 
 Number of bonded IOBs:                  79  out of    141    56%
64 
 Number of BRAMs:                         6  out of     16    37%
65 
 Number of GCLKs:                         1  out of      8    12%
66 
 
67 
---------------------------
68 
 
69 
====================================================================================
70 
#                            SYNTHESIS DONE
71 
#####################################################################################
72 
 
73 
#####################################################################################
74 
#                            START SYNTHESIS (SPEED optimized)
75 
#====================================================================================
76 
# spartan3e (xc3s500epq208), speedgrade: -4
77 
#====================================================================================
78 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
79 
#     12          10          0         0            0          0            0
80 
#====================================================================================
81 
Clock to Setup on destination clock dco_clk
82 
---------------+---------+---------+---------+---------+
83 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
84 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
85 
---------------+---------+---------+---------+---------+
86 
dco_clk        |   31.219|         |         |    1.815|
87 
---------------+---------+---------+---------+---------+
88 
 
89 
====================================================================================
90 
Device utilization summary:
91 
---------------------------
92 
 
93 
Selected Device : 3s500epq208-4
94 
 
95 
 Number of Slices:                      946  out of   4656    20%
96 
 Number of Slice Flip Flops:            477  out of   9312     5%
97 
 Number of 4 input LUTs:               1799  out of   9312    19%
98 
 Number of IOs:                          80
99 
 Number of bonded IOBs:                  79  out of    158    50%
100 
 Number of BRAMs:                         6  out of     20    30%
101 
 Number of GCLKs:                         1  out of     24     4%
102 
 
103 
---------------------------
104 
 
105 
====================================================================================
106 
#                            SYNTHESIS DONE
107 
#####################################################################################
108 
 
109 
#####################################################################################
110 
#                            START SYNTHESIS (SPEED optimized)
111 
#====================================================================================
112 
# spartan3e (xc3s500epq208), speedgrade: -5
113 
#====================================================================================
114 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
115 
#     12          10          0         0            0          0            0
116 
#====================================================================================
117 
Clock to Setup on destination clock dco_clk
118 
---------------+---------+---------+---------+---------+
119 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
120 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
121 
---------------+---------+---------+---------+---------+
122 
dco_clk        |   26.827|         |         |    1.276|
123 
---------------+---------+---------+---------+---------+
124 
 
125 
====================================================================================
126 
Device utilization summary:
127 
---------------------------
128 
 
129 
Selected Device : 3s500epq208-5
130 
 
131 
 Number of Slices:                      946  out of   4656    20%
132 
 Number of Slice Flip Flops:            477  out of   9312     5%
133 
 Number of 4 input LUTs:               1800  out of   9312    19%
134 
 Number of IOs:                          80
135 
 Number of bonded IOBs:                  79  out of    158    50%
136 
 Number of BRAMs:                         6  out of     20    30%
137 
 Number of GCLKs:                         1  out of     24     4%
138 
 
139 
---------------------------
140 
 
141 
====================================================================================
142 
#                            SYNTHESIS DONE
143 
#####################################################################################
144 
 
145 
#####################################################################################
146 
#                            START SYNTHESIS (SPEED optimized)
147 
#====================================================================================
148 
# spartan3a (xc3s700aft256), speedgrade: -4
149 
#====================================================================================
150 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
151 
#     12          10          0         0            0          0            0
152 
#====================================================================================
153 
Clock to Setup on destination clock dco_clk
154 
---------------+---------+---------+---------+---------+
155 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
156 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
157 
---------------+---------+---------+---------+---------+
158 
dco_clk        |   32.020|         |         |    1.260|
159 
---------------+---------+---------+---------+---------+
160 
 
161 
====================================================================================
162 
Device utilization summary:
163 
---------------------------
164 
 
165 
Selected Device : 3s700aft256-4
166 
 
167 
 Number of Slices:                      930  out of   5888    15%
168 
 Number of Slice Flip Flops:            480  out of  11776     4%
169 
 Number of 4 input LUTs:               1769  out of  11776    15%
170 
 Number of IOs:                          80
171 
 Number of bonded IOBs:                  79  out of    161    49%
172 
 Number of BRAMs:                         5  out of     20    25%
173 
 Number of GCLKs:                         1  out of     24     4%
174 
 
175 
---------------------------
176 
 
177 
====================================================================================
178 
#                            SYNTHESIS DONE
179 
#####################################################################################
180 
 
181 
#####################################################################################
182 
#                            START SYNTHESIS (SPEED optimized)
183 
#====================================================================================
184 
# spartan3a (xc3s700aft256), speedgrade: -5
185 
#====================================================================================
186 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
187 
#     12          10          0         0            0          0            0
188 
#====================================================================================
189 
Clock to Setup on destination clock dco_clk
190 
---------------+---------+---------+---------+---------+
191 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
192 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
193 
---------------+---------+---------+---------+---------+
194 
dco_clk        |   27.706|         |         |    1.235|
195 
---------------+---------+---------+---------+---------+
196 
 
197 
====================================================================================
198 
Device utilization summary:
199 
---------------------------
200 
 
201 
Selected Device : 3s700aft256-5
202 
 
203 
 Number of Slices:                      924  out of   5888    15%
204 
 Number of Slice Flip Flops:            474  out of  11776     4%
205 
 Number of 4 input LUTs:               1759  out of  11776    14%
206 
 Number of IOs:                          80
207 
 Number of bonded IOBs:                  79  out of    161    49%
208 
 Number of BRAMs:                         5  out of     20    25%
209 
 Number of GCLKs:                         1  out of     24     4%
210 
 
211 
---------------------------
212 
 
213 
====================================================================================
214 
#                            SYNTHESIS DONE
215 
#####################################################################################
216 
 
217 
#####################################################################################
218 
#                            START SYNTHESIS (SPEED optimized)
219 
#====================================================================================
220 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
221 
#====================================================================================
222 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
223 
#     12          10          0         0            0          0            0
224 
#====================================================================================
225 
Clock to Setup on destination clock dco_clk
226 
---------------+---------+---------+---------+---------+
227 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
228 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
229 
---------------+---------+---------+---------+---------+
230 
dco_clk        |   32.066|         |         |    1.723|
231 
---------------+---------+---------+---------+---------+
232 
 
233 
====================================================================================
234 
Device utilization summary:
235 
---------------------------
236 
 
237 
Selected Device : 3sd1800acs484-4
238 
 
239 
 Number of Slices:                      942  out of  16640     5%
240 
 Number of Slice Flip Flops:            479  out of  33280     1%
241 
 Number of 4 input LUTs:               1782  out of  33280     5%
242 
 Number of IOs:                          80
243 
 Number of bonded IOBs:                  79  out of    309    25%
244 
 Number of BRAMs:                         5  out of     84     5%
245 
 Number of GCLKs:                         1  out of     24     4%
246 
 
247 
---------------------------
248 
 
249 
====================================================================================
250 
#                            SYNTHESIS DONE
251 
#####################################################################################
252 
 
253 
#####################################################################################
254 
#                            START SYNTHESIS (SPEED optimized)
255 
#====================================================================================
256 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
257 
#====================================================================================
258 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
259 
#     12          10          0         0            0          0            0
260 
#====================================================================================
261 
Clock to Setup on destination clock dco_clk
262 
---------------+---------+---------+---------+---------+
263 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
264 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
265 
---------------+---------+---------+---------+---------+
266 
dco_clk        |   25.434|         |         |    1.235|
267 
---------------+---------+---------+---------+---------+
268 
 
269 
====================================================================================
270 
Device utilization summary:
271 
---------------------------
272 
 
273 
Selected Device : 3sd1800acs484-5
274 
 
275 
 Number of Slices:                      927  out of  16640     5%
276 
 Number of Slice Flip Flops:            479  out of  33280     1%
277 
 Number of 4 input LUTs:               1760  out of  33280     5%
278 
 Number of IOs:                          80
279 
 Number of bonded IOBs:                  79  out of    309    25%
280 
 Number of BRAMs:                         5  out of     84     5%
281 
 Number of GCLKs:                         1  out of     24     4%
282 
 
283 
---------------------------
284 
 
285 
====================================================================================
286 
#                            SYNTHESIS DONE
287 
#####################################################################################
288 
 
289 
#####################################################################################
290 
#                            START SYNTHESIS (SPEED optimized)
291 
#====================================================================================
292 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
293 
#====================================================================================
294 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
295 
#     12          10          0         0            0          0            0
296 
#====================================================================================
297 
Clock to Setup on destination clock dco_clk
298 
---------------+---------+---------+---------+---------+
299 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
300 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
301 
---------------+---------+---------+---------+---------+
302 
dco_clk        |   24.353|    6.455|    2.777|    1.423|
303 
---------------+---------+---------+---------+---------+
304 
 
305 
====================================================================================
306 
Device utilization summary:
307 
---------------------------
308 
 
309 
Selected Device : 6slx45tfgg484-2
310 
 
311 
 
312 
Slice Logic Utilization:
313 
 Number of Slice Registers:             468  out of  54576     0%
314 
 Number of Slice LUTs:                 1564  out of  27288     5%
315 
    Number used as Logic:              1564  out of  27288     5%
316 
 
317 
Slice Logic Distribution:
318 
 Number of LUT Flip Flop pairs used:   1655
319 
   Number with an unused Flip Flop:    1187  out of   1655    71%
320 
   Number with an unused LUT:            91  out of   1655     5%
321 
   Number of fully used LUT-FF pairs:   377  out of   1655    22%
322 
   Number of unique control sets:        43
323 
 
324 
IO Utilization:
325 
 Number of IOs:                          80
326 
 Number of bonded IOBs:                  79  out of    296    26%
327 
 
328 
Specific Feature Utilization:
329 
 Number of Block RAM/FIFO:                5  out of    348     1%
330 
    Number using Block RAM only:          5
331 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
332 
 
333 
---------------------------
334 
 
335 
====================================================================================
336 
#                            SYNTHESIS DONE
337 
#####################################################################################
338 
 
339 
#####################################################################################
340 
#                            START SYNTHESIS (SPEED optimized)
341 
#====================================================================================
342 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
343 
#====================================================================================
344 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
345 
#     12          10          0         0            0          0            0
346 
#====================================================================================
347 
Clock to Setup on destination clock dco_clk
348 
---------------+---------+---------+---------+---------+
349 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
350 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
351 
---------------+---------+---------+---------+---------+
352 
dco_clk        |   17.186|    5.614|    2.121|    2.181|
353 
---------------+---------+---------+---------+---------+
354 
 
355 
====================================================================================
356 
Device utilization summary:
357 
---------------------------
358 
 
359 
Selected Device : 6slx45tfgg484-3
360 
 
361 
 
362 
Slice Logic Utilization:
363 
 Number of Slice Registers:             465  out of  54576     0%
364 
 Number of Slice LUTs:                 1605  out of  27288     5%
365 
    Number used as Logic:              1605  out of  27288     5%
366 
 
367 
Slice Logic Distribution:
368 
 Number of LUT Flip Flop pairs used:   1682
369 
   Number with an unused Flip Flop:    1217  out of   1682    72%
370 
   Number with an unused LUT:            77  out of   1682     4%
371 
   Number of fully used LUT-FF pairs:   388  out of   1682    23%
372 
   Number of unique control sets:        42
373 
 
374 
IO Utilization:
375 
 Number of IOs:                          80
376 
 Number of bonded IOBs:                  79  out of    296    26%
377 
 
378 
Specific Feature Utilization:
379 
 Number of Block RAM/FIFO:                5  out of    348     1%
380 
    Number using Block RAM only:          5
381 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
382 
 
383 
---------------------------
384 
 
385 
====================================================================================
386 
#                            SYNTHESIS DONE
387 
#####################################################################################
388 
 
389 
#####################################################################################
390 
#                            START SYNTHESIS (SPEED optimized)
391 
#====================================================================================
392 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
393 
#====================================================================================
394 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
395 
#     12          10          0         0            0          0            0
396 
#====================================================================================
397 
Clock to Setup on destination clock dco_clk
398 
---------------+---------+---------+---------+---------+
399 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
400 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
401 
---------------+---------+---------+---------+---------+
402 
dco_clk        |   15.161|    5.201|    1.755|    1.839|
403 
---------------+---------+---------+---------+---------+
404 
 
405 
====================================================================================
406 
Device utilization summary:
407 
---------------------------
408 
 
409 
Selected Device : 6slx45tfgg484-4
410 
 
411 
 
412 
Slice Logic Utilization:
413 
 Number of Slice Registers:             465  out of  54576     0%
414 
 Number of Slice LUTs:                 1582  out of  27288     5%
415 
    Number used as Logic:              1582  out of  27288     5%
416 
 
417 
Slice Logic Distribution:
418 
 Number of LUT Flip Flop pairs used:   1663
419 
   Number with an unused Flip Flop:    1198  out of   1663    72%
420 
   Number with an unused LUT:            81  out of   1663     4%
421 
   Number of fully used LUT-FF pairs:   384  out of   1663    23%
422 
   Number of unique control sets:        41
423 
 
424 
IO Utilization:
425 
 Number of IOs:                          80
426 
 Number of bonded IOBs:                  79  out of    296    26%
427 
 
428 
Specific Feature Utilization:
429 
 Number of Block RAM/FIFO:                5  out of    348     1%
430 
    Number using Block RAM only:          5
431 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
432 
 
433 
---------------------------
434 
 
435 
====================================================================================
436 
#                            SYNTHESIS DONE
437 
#####################################################################################
438 
 
439 
#####################################################################################
440 
#                            START SYNTHESIS (SPEED optimized)
441 
#====================================================================================
442 
# virtex4 (xc4vlx25sf363), speedgrade: -10
443 
#====================================================================================
444 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
445 
#     12          10          0         0            0          0            0
446 
#====================================================================================
447 
Clock to Setup on destination clock dco_clk
448 
---------------+---------+---------+---------+---------+
449 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
450 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
451 
---------------+---------+---------+---------+---------+
452 
dco_clk        |   19.953|         |         |    0.932|
453 
---------------+---------+---------+---------+---------+
454 
 
455 
====================================================================================
456 
Device utilization summary:
457 
---------------------------
458 
 
459 
Selected Device : 4vlx25sf363-10
460 
 
461 
 Number of Slices:                      934  out of  10752     8%
462 
 Number of Slice Flip Flops:            474  out of  21504     2%
463 
 Number of 4 input LUTs:               1773  out of  21504     8%
464 
 Number of IOs:                          80
465 
 Number of bonded IOBs:                  79  out of    240    32%
466 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
467 
    Number used as RAMB16s:               5
468 
 Number of GCLKs:                         1  out of     32     3%
469 
 
470 
---------------------------
471 
 
472 
====================================================================================
473 
#                            SYNTHESIS DONE
474 
#####################################################################################
475 
 
476 
#####################################################################################
477 
#                            START SYNTHESIS (SPEED optimized)
478 
#====================================================================================
479 
# virtex4 (xc4vlx25sf363), speedgrade: -11
480 
#====================================================================================
481 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
482 
#     12          10          0         0            0          0            0
483 
#====================================================================================
484 
Clock to Setup on destination clock dco_clk
485 
---------------+---------+---------+---------+---------+
486 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
487 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
488 
---------------+---------+---------+---------+---------+
489 
dco_clk        |   17.461|         |         |    0.807|
490 
---------------+---------+---------+---------+---------+
491 
 
492 
====================================================================================
493 
Device utilization summary:
494 
---------------------------
495 
 
496 
Selected Device : 4vlx25sf363-11
497 
 
498 
 Number of Slices:                      939  out of  10752     8%
499 
 Number of Slice Flip Flops:            477  out of  21504     2%
500 
 Number of 4 input LUTs:               1782  out of  21504     8%
501 
 Number of IOs:                          80
502 
 Number of bonded IOBs:                  79  out of    240    32%
503 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
504 
    Number used as RAMB16s:               5
505 
 Number of GCLKs:                         1  out of     32     3%
506 
 
507 
---------------------------
508 
 
509 
====================================================================================
510 
#                            SYNTHESIS DONE
511 
#####################################################################################
512 
 
513 
#####################################################################################
514 
#                            START SYNTHESIS (SPEED optimized)
515 
#====================================================================================
516 
# virtex4 (xc4vlx25sf363), speedgrade: -12
517 
#====================================================================================
518 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
519 
#     12          10          0         0            0          0            0
520 
#====================================================================================
521 
Clock to Setup on destination clock dco_clk
522 
---------------+---------+---------+---------+---------+
523 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
524 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
525 
---------------+---------+---------+---------+---------+
526 
dco_clk        |   15.024|         |         |    0.717|
527 
---------------+---------+---------+---------+---------+
528 
 
529 
====================================================================================
530 
Device utilization summary:
531 
---------------------------
532 
 
533 
Selected Device : 4vlx25sf363-12
534 
 
535 
 Number of Slices:                      938  out of  10752     8%
536 
 Number of Slice Flip Flops:            477  out of  21504     2%
537 
 Number of 4 input LUTs:               1779  out of  21504     8%
538 
 Number of IOs:                          80
539 
 Number of bonded IOBs:                  79  out of    240    32%
540 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
541 
    Number used as RAMB16s:               5
542 
 Number of GCLKs:                         1  out of     32     3%
543 
 
544 
---------------------------
545 
 
546 
====================================================================================
547 
#                            SYNTHESIS DONE
548 
#####################################################################################
549 
 
550 
#####################################################################################
551 
#                            START SYNTHESIS (SPEED optimized)
552 
#====================================================================================
553 
# virtex5 (xc5vlx30ff324), speedgrade: -1
554 
#====================================================================================
555 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
556 
#     12          10          0         0            0          0            0
557 
#====================================================================================
558 
Clock to Setup on destination clock dco_clk
559 
---------------+---------+---------+---------+---------+
560 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
561 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
562 
---------------+---------+---------+---------+---------+
563 
dco_clk        |   13.442|         |         |    0.781|
564 
---------------+---------+---------+---------+---------+
565 
 
566 
====================================================================================
567 
Device utilization summary:
568 
---------------------------
569 
 
570 
Selected Device : 5vlx30ff324-1
571 
 
572 
 
573 
Slice Logic Utilization:
574 
 Number of Slice Registers:             469  out of  19200     2%
575 
 Number of Slice LUTs:                 1488  out of  19200     7%
576 
    Number used as Logic:              1488  out of  19200     7%
577 
 
578 
Slice Logic Distribution:
579 
 Number of LUT Flip Flop pairs used:   1597
580 
   Number with an unused Flip Flop:    1128  out of   1597    70%
581 
   Number with an unused LUT:           109  out of   1597     6%
582 
   Number of fully used LUT-FF pairs:   360  out of   1597    22%
583 
   Number of unique control sets:        41
584 
 
585 
IO Utilization:
586 
 Number of IOs:                          80
587 
 Number of bonded IOBs:                  79  out of    220    35%
588 
 
589 
Specific Feature Utilization:
590 
 Number of Block RAM/FIFO:                3  out of     32     9%
591 
    Number using Block RAM only:          3
592 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
593 
 
594 
---------------------------
595 
 
596 
====================================================================================
597 
#                            SYNTHESIS DONE
598 
#####################################################################################
599 
 
600 
#####################################################################################
601 
#                            START SYNTHESIS (SPEED optimized)
602 
#====================================================================================
603 
# virtex5 (xc5vlx30ff324), speedgrade: -2
604 
#====================================================================================
605 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
606 
#     12          10          0         0            0          0            0
607 
#====================================================================================
608 
Clock to Setup on destination clock dco_clk
609 
---------------+---------+---------+---------+---------+
610 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
611 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
612 
---------------+---------+---------+---------+---------+
613 
dco_clk        |   12.171|         |         |    0.677|
614 
---------------+---------+---------+---------+---------+
615 
 
616 
====================================================================================
617 
Device utilization summary:
618 
---------------------------
619 
 
620 
Selected Device : 5vlx30ff324-2
621 
 
622 
 
623 
Slice Logic Utilization:
624 
 Number of Slice Registers:             466  out of  19200     2%
625 
 Number of Slice LUTs:                 1445  out of  19200     7%
626 
    Number used as Logic:              1445  out of  19200     7%
627 
 
628 
Slice Logic Distribution:
629 
 Number of LUT Flip Flop pairs used:   1534
630 
   Number with an unused Flip Flop:    1068  out of   1534    69%
631 
   Number with an unused LUT:            89  out of   1534     5%
632 
   Number of fully used LUT-FF pairs:   377  out of   1534    24%
633 
   Number of unique control sets:        41
634 
 
635 
IO Utilization:
636 
 Number of IOs:                          80
637 
 Number of bonded IOBs:                  79  out of    220    35%
638 
 
639 
Specific Feature Utilization:
640 
 Number of Block RAM/FIFO:                3  out of     32     9%
641 
    Number using Block RAM only:          3
642 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
643 
 
644 
---------------------------
645 
 
646 
====================================================================================
647 
#                            SYNTHESIS DONE
648 
#####################################################################################
649 
 
650 
#####################################################################################
651 
#                            START SYNTHESIS (SPEED optimized)
652 
#====================================================================================
653 
# virtex5 (xc5vlx30ff324), speedgrade: -3
654 
#====================================================================================
655 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
656 
#     12          10          0         0            0          0            0
657 
#====================================================================================
658 
Clock to Setup on destination clock dco_clk
659 
---------------+---------+---------+---------+---------+
660 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
661 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
662 
---------------+---------+---------+---------+---------+
663 
dco_clk        |   10.220|         |         |    0.643|
664 
---------------+---------+---------+---------+---------+
665 
 
666 
====================================================================================
667 
Device utilization summary:
668 
---------------------------
669 
 
670 
Selected Device : 5vlx30ff324-3
671 
 
672 
 
673 
Slice Logic Utilization:
674 
 Number of Slice Registers:             464  out of  19200     2%
675 
 Number of Slice LUTs:                 1447  out of  19200     7%
676 
    Number used as Logic:              1447  out of  19200     7%
677 
 
678 
Slice Logic Distribution:
679 
 Number of LUT Flip Flop pairs used:   1546
680 
   Number with an unused Flip Flop:    1082  out of   1546    69%
681 
   Number with an unused LUT:            99  out of   1546     6%
682 
   Number of fully used LUT-FF pairs:   365  out of   1546    23%
683 
   Number of unique control sets:        41
684 
 
685 
IO Utilization:
686 
 Number of IOs:                          80
687 
 Number of bonded IOBs:                  79  out of    220    35%
688 
 
689 
Specific Feature Utilization:
690 
 Number of Block RAM/FIFO:                3  out of     32     9%
691 
    Number using Block RAM only:          3
692 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
693 
 
694 
---------------------------
695 
 
696 
====================================================================================
697 
#                            SYNTHESIS DONE
698 
#####################################################################################
699 
 
700 
#####################################################################################
701 
#                            START SYNTHESIS (SPEED optimized)
702 
#====================================================================================
703 
# virtex6 (xc6vlx75tff484), speedgrade: -1
704 
#====================================================================================
705 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
706 
#     12          10          0         0            0          0            0
707 
#====================================================================================
708 
Clock to Setup on destination clock dco_clk
709 
---------------+---------+---------+---------+---------+
710 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
711 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
712 
---------------+---------+---------+---------+---------+
713 
dco_clk        |   11.195|    3.874|    1.642|    0.693|
714 
---------------+---------+---------+---------+---------+
715 
 
716 
====================================================================================
717 
Device utilization summary:
718 
---------------------------
719 
 
720 
Selected Device : 6vlx75tff484-1
721 
 
722 
 
723 
Slice Logic Utilization:
724 
 Number of Slice Registers:             470  out of  93120     0%
725 
 Number of Slice LUTs:                 1549  out of  46560     3%
726 
    Number used as Logic:              1549  out of  46560     3%
727 
 
728 
Slice Logic Distribution:
729 
 Number of LUT Flip Flop pairs used:   1599
730 
   Number with an unused Flip Flop:    1129  out of   1599    70%
731 
   Number with an unused LUT:            50  out of   1599     3%
732 
   Number of fully used LUT-FF pairs:   420  out of   1599    26%
733 
   Number of unique control sets:        41
734 
 
735 
IO Utilization:
736 
 Number of IOs:                          80
737 
 Number of bonded IOBs:                  79  out of    240    32%
738 
 
739 
Specific Feature Utilization:
740 
 Number of Block RAM/FIFO:                3  out of    156     1%
741 
    Number using Block RAM only:          3
742 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
743 
 
744 
---------------------------
745 
 
746 
====================================================================================
747 
#                            SYNTHESIS DONE
748 
#####################################################################################
749 
 
750 
#####################################################################################
751 
#                            START SYNTHESIS (SPEED optimized)
752 
#====================================================================================
753 
# virtex6 (xc6vlx75tff484), speedgrade: -2
754 
#====================================================================================
755 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
756 
#     12          10          0         0            0          0            0
757 
#====================================================================================
758 
Clock to Setup on destination clock dco_clk
759 
---------------+---------+---------+---------+---------+
760 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
761 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
762 
---------------+---------+---------+---------+---------+
763 
dco_clk        |    9.765|    3.012|    1.436|    0.615|
764 
---------------+---------+---------+---------+---------+
765 
 
766 
====================================================================================
767 
Device utilization summary:
768 
---------------------------
769 
 
770 
Selected Device : 6vlx75tff484-2
771 
 
772 
 
773 
Slice Logic Utilization:
774 
 Number of Slice Registers:             466  out of  93120     0%
775 
 Number of Slice LUTs:                 1474  out of  46560     3%
776 
    Number used as Logic:              1474  out of  46560     3%
777 
 
778 
Slice Logic Distribution:
779 
 Number of LUT Flip Flop pairs used:   1517
780 
   Number with an unused Flip Flop:    1051  out of   1517    69%
781 
   Number with an unused LUT:            43  out of   1517     2%
782 
   Number of fully used LUT-FF pairs:   423  out of   1517    27%
783 
   Number of unique control sets:        42
784 
 
785 
IO Utilization:
786 
 Number of IOs:                          80
787 
 Number of bonded IOBs:                  79  out of    240    32%
788 
 
789 
Specific Feature Utilization:
790 
 Number of Block RAM/FIFO:                3  out of    156     1%
791 
    Number using Block RAM only:          3
792 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
793 
 
794 
---------------------------
795 
 
796 
====================================================================================
797 
#                            SYNTHESIS DONE
798 
#####################################################################################
799 
 
800 
#####################################################################################
801 
#                            START SYNTHESIS (SPEED optimized)
802 
#====================================================================================
803 
# virtex6 (xc6vlx75tff484), speedgrade: -3
804 
#====================================================================================
805 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
806 
#     12          10          0         0            0          0            0
807 
#====================================================================================
808 
Clock to Setup on destination clock dco_clk
809 
---------------+---------+---------+---------+---------+
810 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
811 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
812 
---------------+---------+---------+---------+---------+
813 
dco_clk        |    8.949|    3.066|    1.224|    0.446|
814 
---------------+---------+---------+---------+---------+
815 
 
816 
====================================================================================
817 
Device utilization summary:
818 
---------------------------
819 
 
820 
Selected Device : 6vlx75tff484-3
821 
 
822 
 
823 
Slice Logic Utilization:
824 
 Number of Slice Registers:             464  out of  93120     0%
825 
 Number of Slice LUTs:                 1451  out of  46560     3%
826 
    Number used as Logic:              1451  out of  46560     3%
827 
 
828 
Slice Logic Distribution:
829 
 Number of LUT Flip Flop pairs used:   1487
830 
   Number with an unused Flip Flop:    1023  out of   1487    68%
831 
   Number with an unused LUT:            36  out of   1487     2%
832 
   Number of fully used LUT-FF pairs:   428  out of   1487    28%
833 
   Number of unique control sets:        42
834 
 
835 
IO Utilization:
836 
 Number of IOs:                          80
837 
 Number of bonded IOBs:                  79  out of    240    32%
838 
 
839 
Specific Feature Utilization:
840 
 Number of Block RAM/FIFO:                3  out of    156     1%
841 
    Number using Block RAM only:          3
842 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
843 
 
844 
---------------------------
845 
 
846 
====================================================================================
847 
#                            SYNTHESIS DONE
848 
#####################################################################################
849 
 
850 
#####################################################################################
851 
#                            START SYNTHESIS (SPEED optimized)
852 
#====================================================================================
853 
# spartan3 (xc3s400pq208), speedgrade: -4
854 
#====================================================================================
855 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
856 
#     12          10          1         0            0          0            0
857 
#====================================================================================
858 
Clock to Setup on destination clock dco_clk
859 
---------------+---------+---------+---------+---------+
860 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
861 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
862 
---------------+---------+---------+---------+---------+
863 
dco_clk        |   35.345|   18.429|         |    2.800|
864 
---------------+---------+---------+---------+---------+
865 
 
866 
====================================================================================
867 
Device utilization summary:
868 
---------------------------
869 
 
870 
Selected Device : 3s400pq208-4
871 
 
872 
 Number of Slices:                     1250  out of   3584    34%
873 
 Number of Slice Flip Flops:            616  out of   7168     8%
874 
 Number of 4 input LUTs:               2365  out of   7168    32%
875 
 Number of IOs:                          80
876 
 Number of bonded IOBs:                  80  out of    141    56%
877 
 Number of BRAMs:                         6  out of     16    37%
878 
 Number of GCLKs:                         1  out of      8    12%
879 
 
880 
---------------------------
881 
 
882 
====================================================================================
883 
#                            SYNTHESIS DONE
884 
#####################################################################################
885 
 
886 
#####################################################################################
887 
#                            START SYNTHESIS (SPEED optimized)
888 
#====================================================================================
889 
# spartan3 (xc3s400pq208), speedgrade: -5
890 
#====================================================================================
891 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
892 
#     12          10          1         0            0          0            0
893 
#====================================================================================
894 
Clock to Setup on destination clock dco_clk
895 
---------------+---------+---------+---------+---------+
896 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
897 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
898 
---------------+---------+---------+---------+---------+
899 
dco_clk        |   30.645|   15.379|         |    1.809|
900 
---------------+---------+---------+---------+---------+
901 
 
902 
====================================================================================
903 
Device utilization summary:
904 
---------------------------
905 
 
906 
Selected Device : 3s400pq208-5
907 
 
908 
 Number of Slices:                     1252  out of   3584    34%
909 
 Number of Slice Flip Flops:            617  out of   7168     8%
910 
 Number of 4 input LUTs:               2367  out of   7168    33%
911 
 Number of IOs:                          80
912 
 Number of bonded IOBs:                  80  out of    141    56%
913 
 Number of BRAMs:                         6  out of     16    37%
914 
 Number of GCLKs:                         1  out of      8    12%
915 
 
916 
---------------------------
917 
 
918 
====================================================================================
919 
#                            SYNTHESIS DONE
920 
#####################################################################################
921 
 
922 
#####################################################################################
923 
#                            START SYNTHESIS (SPEED optimized)
924 
#====================================================================================
925 
# spartan3e (xc3s500epq208), speedgrade: -4
926 
#====================================================================================
927 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
928 
#     12          10          1         0            0          0            0
929 
#====================================================================================
930 
Clock to Setup on destination clock dco_clk
931 
---------------+---------+---------+---------+---------+
932 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
933 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
934 
---------------+---------+---------+---------+---------+
935 
dco_clk        |   35.715|   18.857|         |    1.522|
936 
---------------+---------+---------+---------+---------+
937 
 
938 
====================================================================================
939 
Device utilization summary:
940 
---------------------------
941 
 
942 
Selected Device : 3s500epq208-4
943 
 
944 
 Number of Slices:                     1214  out of   4656    26%
945 
 Number of Slice Flip Flops:            603  out of   9312     6%
946 
 Number of 4 input LUTs:               2293  out of   9312    24%
947 
 Number of IOs:                          80
948 
 Number of bonded IOBs:                  80  out of    158    50%
949 
 Number of BRAMs:                         6  out of     20    30%
950 
 Number of GCLKs:                         1  out of     24     4%
951 
 
952 
---------------------------
953 
 
954 
====================================================================================
955 
#                            SYNTHESIS DONE
956 
#####################################################################################
957 
 
958 
#####################################################################################
959 
#                            START SYNTHESIS (SPEED optimized)
960 
#====================================================================================
961 
# spartan3e (xc3s500epq208), speedgrade: -5
962 
#====================================================================================
963 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
964 
#     12          10          1         0            0          0            0
965 
#====================================================================================
966 
Clock to Setup on destination clock dco_clk
967 
---------------+---------+---------+---------+---------+
968 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
969 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
970 
---------------+---------+---------+---------+---------+
971 
dco_clk        |   30.761|   15.416|         |    1.727|
972 
---------------+---------+---------+---------+---------+
973 
 
974 
====================================================================================
975 
Device utilization summary:
976 
---------------------------
977 
 
978 
Selected Device : 3s500epq208-5
979 
 
980 
 Number of Slices:                     1214  out of   4656    26%
981 
 Number of Slice Flip Flops:            603  out of   9312     6%
982 
 Number of 4 input LUTs:               2293  out of   9312    24%
983 
 Number of IOs:                          80
984 
 Number of bonded IOBs:                  80  out of    158    50%
985 
 Number of BRAMs:                         6  out of     20    30%
986 
 Number of GCLKs:                         1  out of     24     4%
987 
 
988 
---------------------------
989 
 
990 
====================================================================================
991 
#                            SYNTHESIS DONE
992 
#####################################################################################
993 
 
994 
#####################################################################################
995 
#                            START SYNTHESIS (SPEED optimized)
996 
#====================================================================================
997 
# spartan3a (xc3s700aft256), speedgrade: -4
998 
#====================================================================================
999 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1000 
#     12          10          1         0            0          0            0
1001 
#====================================================================================
1002 
Clock to Setup on destination clock dco_clk
1003 
---------------+---------+---------+---------+---------+
1004 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1005 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1006 
---------------+---------+---------+---------+---------+
1007 
dco_clk        |   34.381|   18.535|         |    2.134|
1008 
---------------+---------+---------+---------+---------+
1009 
 
1010 
====================================================================================
1011 
Device utilization summary:
1012 
---------------------------
1013 
 
1014 
Selected Device : 3s700aft256-4
1015 
 
1016 
 Number of Slices:                     1189  out of   5888    20%
1017 
 Number of Slice Flip Flops:            605  out of  11776     5%
1018 
 Number of 4 input LUTs:               2235  out of  11776    18%
1019 
 Number of IOs:                          80
1020 
 Number of bonded IOBs:                  80  out of    161    49%
1021 
 Number of BRAMs:                         5  out of     20    25%
1022 
 Number of GCLKs:                         1  out of     24     4%
1023 
 
1024 
---------------------------
1025 
 
1026 
====================================================================================
1027 
#                            SYNTHESIS DONE
1028 
#####################################################################################
1029 
 
1030 
#####################################################################################
1031 
#                            START SYNTHESIS (SPEED optimized)
1032 
#====================================================================================
1033 
# spartan3a (xc3s700aft256), speedgrade: -5
1034 
#====================================================================================
1035 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1036 
#     12          10          1         0            0          0            0
1037 
#====================================================================================
1038 
Clock to Setup on destination clock dco_clk
1039 
---------------+---------+---------+---------+---------+
1040 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1041 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1042 
---------------+---------+---------+---------+---------+
1043 
dco_clk        |   29.848|   15.469|         |    1.719|
1044 
---------------+---------+---------+---------+---------+
1045 
 
1046 
====================================================================================
1047 
Device utilization summary:
1048 
---------------------------
1049 
 
1050 
Selected Device : 3s700aft256-5
1051 
 
1052 
 Number of Slices:                     1232  out of   5888    20%
1053 
 Number of Slice Flip Flops:            606  out of  11776     5%
1054 
 Number of 4 input LUTs:               2322  out of  11776    19%
1055 
 Number of IOs:                          80
1056 
 Number of bonded IOBs:                  80  out of    161    49%
1057 
 Number of BRAMs:                         5  out of     20    25%
1058 
 Number of GCLKs:                         1  out of     24     4%
1059 
 
1060 
---------------------------
1061 
 
1062 
====================================================================================
1063 
#                            SYNTHESIS DONE
1064 
#####################################################################################
1065 
 
1066 
#####################################################################################
1067 
#                            START SYNTHESIS (SPEED optimized)
1068 
#====================================================================================
1069 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
1070 
#====================================================================================
1071 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1072 
#     12          10          1         0            0          0            0
1073 
#====================================================================================
1074 
Clock to Setup on destination clock dco_clk
1075 
---------------+---------+---------+---------+---------+
1076 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1077 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1078 
---------------+---------+---------+---------+---------+
1079 
dco_clk        |   33.891|   17.483|         |    3.086|
1080 
---------------+---------+---------+---------+---------+
1081 
 
1082 
====================================================================================
1083 
Device utilization summary:
1084 
---------------------------
1085 
 
1086 
Selected Device : 3sd1800acs484-4
1087 
 
1088 
 Number of Slices:                     1194  out of  16640     7%
1089 
 Number of Slice Flip Flops:            605  out of  33280     1%
1090 
 Number of 4 input LUTs:               2241  out of  33280     6%
1091 
 Number of IOs:                          80
1092 
 Number of bonded IOBs:                  80  out of    309    25%
1093 
 Number of BRAMs:                         5  out of     84     5%
1094 
 Number of GCLKs:                         1  out of     24     4%
1095 
 
1096 
---------------------------
1097 
 
1098 
====================================================================================
1099 
#                            SYNTHESIS DONE
1100 
#####################################################################################
1101 
 
1102 
#####################################################################################
1103 
#                            START SYNTHESIS (SPEED optimized)
1104 
#====================================================================================
1105 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
1106 
#====================================================================================
1107 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1108 
#     12          10          1         0            0          0            0
1109 
#====================================================================================
1110 
Clock to Setup on destination clock dco_clk
1111 
---------------+---------+---------+---------+---------+
1112 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1113 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1114 
---------------+---------+---------+---------+---------+
1115 
dco_clk        |   29.772|   15.569|         |    1.972|
1116 
---------------+---------+---------+---------+---------+
1117 
 
1118 
====================================================================================
1119 
Device utilization summary:
1120 
---------------------------
1121 
 
1122 
Selected Device : 3sd1800acs484-5
1123 
 
1124 
 Number of Slices:                     1245  out of  16640     7%
1125 
 Number of Slice Flip Flops:            605  out of  33280     1%
1126 
 Number of 4 input LUTs:               2341  out of  33280     7%
1127 
 Number of IOs:                          80
1128 
 Number of bonded IOBs:                  80  out of    309    25%
1129 
 Number of BRAMs:                         5  out of     84     5%
1130 
 Number of GCLKs:                         1  out of     24     4%
1131 
 
1132 
---------------------------
1133 
 
1134 
====================================================================================
1135 
#                            SYNTHESIS DONE
1136 
#####################################################################################
1137 
 
1138 
#####################################################################################
1139 
#                            START SYNTHESIS (SPEED optimized)
1140 
#====================================================================================
1141 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
1142 
#====================================================================================
1143 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1144 
#     12          10          1         0            0          0            0
1145 
#====================================================================================
1146 
Clock to Setup on destination clock dco_clk
1147 
---------------+---------+---------+---------+---------+
1148 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1149 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1150 
---------------+---------+---------+---------+---------+
1151 
dco_clk        |   25.580|   12.604|    7.022|    2.840|
1152 
---------------+---------+---------+---------+---------+
1153 
 
1154 
====================================================================================
1155 
Device utilization summary:
1156 
---------------------------
1157 
 
1158 
Selected Device : 6slx45tfgg484-2
1159 
 
1160 
 
1161 
Slice Logic Utilization:
1162 
 Number of Slice Registers:             605  out of  54576     1%
1163 
 Number of Slice LUTs:                 1837  out of  27288     6%
1164 
    Number used as Logic:              1837  out of  27288     6%
1165 
 
1166 
Slice Logic Distribution:
1167 
 Number of LUT Flip Flop pairs used:   2004
1168 
   Number with an unused Flip Flop:    1399  out of   2004    69%
1169 
   Number with an unused LUT:           167  out of   2004     8%
1170 
   Number of fully used LUT-FF pairs:   438  out of   2004    21%
1171 
   Number of unique control sets:        54
1172 
 
1173 
IO Utilization:
1174 
 Number of IOs:                          80
1175 
 Number of bonded IOBs:                  80  out of    296    27%
1176 
 
1177 
Specific Feature Utilization:
1178 
 Number of Block RAM/FIFO:                5  out of    348     1%
1179 
    Number using Block RAM only:          5
1180 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
1181 
 
1182 
---------------------------
1183 
 
1184 
====================================================================================
1185 
#                            SYNTHESIS DONE
1186 
#####################################################################################
1187 
 
1188 
#####################################################################################
1189 
#                            START SYNTHESIS (SPEED optimized)
1190 
#====================================================================================
1191 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
1192 
#====================================================================================
1193 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1194 
#     12          10          1         0            0          0            0
1195 
#====================================================================================
1196 
Clock to Setup on destination clock dco_clk
1197 
---------------+---------+---------+---------+---------+
1198 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1199 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1200 
---------------+---------+---------+---------+---------+
1201 
dco_clk        |   19.998|    9.231|    4.222|    1.939|
1202 
---------------+---------+---------+---------+---------+
1203 
 
1204 
====================================================================================
1205 
Device utilization summary:
1206 
---------------------------
1207 
 
1208 
Selected Device : 6slx45tfgg484-3
1209 
 
1210 
 
1211 
Slice Logic Utilization:
1212 
 Number of Slice Registers:             605  out of  54576     1%
1213 
 Number of Slice LUTs:                 1785  out of  27288     6%
1214 
    Number used as Logic:              1785  out of  27288     6%
1215 
 
1216 
Slice Logic Distribution:
1217 
 Number of LUT Flip Flop pairs used:   1906
1218 
   Number with an unused Flip Flop:    1301  out of   1906    68%
1219 
   Number with an unused LUT:           121  out of   1906     6%
1220 
   Number of fully used LUT-FF pairs:   484  out of   1906    25%
1221 
   Number of unique control sets:        55
1222 
 
1223 
IO Utilization:
1224 
 Number of IOs:                          80
1225 
 Number of bonded IOBs:                  80  out of    296    27%
1226 
 
1227 
Specific Feature Utilization:
1228 
 Number of Block RAM/FIFO:                5  out of    348     1%
1229 
    Number using Block RAM only:          5
1230 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
1231 
 
1232 
---------------------------
1233 
 
1234 
====================================================================================
1235 
#                            SYNTHESIS DONE
1236 
#####################################################################################
1237 
 
1238 
#####################################################################################
1239 
#                            START SYNTHESIS (SPEED optimized)
1240 
#====================================================================================
1241 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
1242 
#====================================================================================
1243 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1244 
#     12          10          1         0            0          0            0
1245 
#====================================================================================
1246 
Clock to Setup on destination clock dco_clk
1247 
---------------+---------+---------+---------+---------+
1248 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1249 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1250 
---------------+---------+---------+---------+---------+
1251 
dco_clk        |   17.427|    8.304|    4.483|    1.813|
1252 
---------------+---------+---------+---------+---------+
1253 
 
1254 
====================================================================================
1255 
Device utilization summary:
1256 
---------------------------
1257 
 
1258 
Selected Device : 6slx45tfgg484-4
1259 
 
1260 
 
1261 
Slice Logic Utilization:
1262 
 Number of Slice Registers:             604  out of  54576     1%
1263 
 Number of Slice LUTs:                 1795  out of  27288     6%
1264 
    Number used as Logic:              1795  out of  27288     6%
1265 
 
1266 
Slice Logic Distribution:
1267 
 Number of LUT Flip Flop pairs used:   1925
1268 
   Number with an unused Flip Flop:    1321  out of   1925    68%
1269 
   Number with an unused LUT:           130  out of   1925     6%
1270 
   Number of fully used LUT-FF pairs:   474  out of   1925    24%
1271 
   Number of unique control sets:        55
1272 
 
1273 
IO Utilization:
1274 
 Number of IOs:                          80
1275 
 Number of bonded IOBs:                  80  out of    296    27%
1276 
 
1277 
Specific Feature Utilization:
1278 
 Number of Block RAM/FIFO:                5  out of    348     1%
1279 
    Number using Block RAM only:          5
1280 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
1281 
 
1282 
---------------------------
1283 
 
1284 
====================================================================================
1285 
#                            SYNTHESIS DONE
1286 
#####################################################################################
1287 
 
1288 
#####################################################################################
1289 
#                            START SYNTHESIS (SPEED optimized)
1290 
#====================================================================================
1291 
# virtex4 (xc4vlx25sf363), speedgrade: -10
1292 
#====================================================================================
1293 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1294 
#     12          10          1         0            0          0            0
1295 
#====================================================================================
1296 
Clock to Setup on destination clock dco_clk
1297 
---------------+---------+---------+---------+---------+
1298 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1299 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1300 
---------------+---------+---------+---------+---------+
1301 
dco_clk        |   21.922|   11.627|         |    1.861|
1302 
---------------+---------+---------+---------+---------+
1303 
 
1304 
====================================================================================
1305 
Device utilization summary:
1306 
---------------------------
1307 
 
1308 
Selected Device : 4vlx25sf363-10
1309 
 
1310 
 Number of Slices:                     1236  out of  10752    11%
1311 
 Number of Slice Flip Flops:            614  out of  21504     2%
1312 
 Number of 4 input LUTs:               2334  out of  21504    10%
1313 
 Number of IOs:                          80
1314 
 Number of bonded IOBs:                  80  out of    240    33%
1315 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
1316 
    Number used as RAMB16s:               5
1317 
 Number of GCLKs:                         1  out of     32     3%
1318 
 
1319 
---------------------------
1320 
 
1321 
====================================================================================
1322 
#                            SYNTHESIS DONE
1323 
#####################################################################################
1324 
 
1325 
#####################################################################################
1326 
#                            START SYNTHESIS (SPEED optimized)
1327 
#====================================================================================
1328 
# virtex4 (xc4vlx25sf363), speedgrade: -11
1329 
#====================================================================================
1330 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1331 
#     12          10          1         0            0          0            0
1332 
#====================================================================================
1333 
Clock to Setup on destination clock dco_clk
1334 
---------------+---------+---------+---------+---------+
1335 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1336 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1337 
---------------+---------+---------+---------+---------+
1338 
dco_clk        |   18.589|    9.795|         |    1.905|
1339 
---------------+---------+---------+---------+---------+
1340 
 
1341 
====================================================================================
1342 
Device utilization summary:
1343 
---------------------------
1344 
 
1345 
Selected Device : 4vlx25sf363-11
1346 
 
1347 
 Number of Slices:                     1235  out of  10752    11%
1348 
 Number of Slice Flip Flops:            614  out of  21504     2%
1349 
 Number of 4 input LUTs:               2332  out of  21504    10%
1350 
 Number of IOs:                          80
1351 
 Number of bonded IOBs:                  80  out of    240    33%
1352 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
1353 
    Number used as RAMB16s:               5
1354 
 Number of GCLKs:                         1  out of     32     3%
1355 
 
1356 
---------------------------
1357 
 
1358 
====================================================================================
1359 
#                            SYNTHESIS DONE
1360 
#####################################################################################
1361 
 
1362 
#####################################################################################
1363 
#                            START SYNTHESIS (SPEED optimized)
1364 
#====================================================================================
1365 
# virtex4 (xc4vlx25sf363), speedgrade: -12
1366 
#====================================================================================
1367 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1368 
#     12          10          1         0            0          0            0
1369 
#====================================================================================
1370 
Clock to Setup on destination clock dco_clk
1371 
---------------+---------+---------+---------+---------+
1372 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1373 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1374 
---------------+---------+---------+---------+---------+
1375 
dco_clk        |   17.402|    9.311|         |    0.928|
1376 
---------------+---------+---------+---------+---------+
1377 
 
1378 
====================================================================================
1379 
Device utilization summary:
1380 
---------------------------
1381 
 
1382 
Selected Device : 4vlx25sf363-12
1383 
 
1384 
 Number of Slices:                     1236  out of  10752    11%
1385 
 Number of Slice Flip Flops:            614  out of  21504     2%
1386 
 Number of 4 input LUTs:               2333  out of  21504    10%
1387 
 Number of IOs:                          80
1388 
 Number of bonded IOBs:                  80  out of    240    33%
1389 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
1390 
    Number used as RAMB16s:               5
1391 
 Number of GCLKs:                         1  out of     32     3%
1392 
 
1393 
---------------------------
1394 
 
1395 
====================================================================================
1396 
#                            SYNTHESIS DONE
1397 
#####################################################################################
1398 
 
1399 
#####################################################################################
1400 
#                            START SYNTHESIS (SPEED optimized)
1401 
#====================================================================================
1402 
# virtex5 (xc5vlx30ff324), speedgrade: -1
1403 
#====================================================================================
1404 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1405 
#     12          10          1         0            0          0            0
1406 
#====================================================================================
1407 
Clock to Setup on destination clock dco_clk
1408 
---------------+---------+---------+---------+---------+
1409 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1410 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1411 
---------------+---------+---------+---------+---------+
1412 
dco_clk        |   14.234|    7.556|         |    0.974|
1413 
---------------+---------+---------+---------+---------+
1414 
 
1415 
====================================================================================
1416 
Device utilization summary:
1417 
---------------------------
1418 
 
1419 
Selected Device : 5vlx30ff324-1
1420 
 
1421 
 
1422 
Slice Logic Utilization:
1423 
 Number of Slice Registers:             605  out of  19200     3%
1424 
 Number of Slice LUTs:                 1776  out of  19200     9%
1425 
    Number used as Logic:              1776  out of  19200     9%
1426 
 
1427 
Slice Logic Distribution:
1428 
 Number of LUT Flip Flop pairs used:   1935
1429 
   Number with an unused Flip Flop:    1330  out of   1935    68%
1430 
   Number with an unused LUT:           159  out of   1935     8%
1431 
   Number of fully used LUT-FF pairs:   446  out of   1935    23%
1432 
   Number of unique control sets:        54
1433 
 
1434 
IO Utilization:
1435 
 Number of IOs:                          80
1436 
 Number of bonded IOBs:                  80  out of    220    36%
1437 
 
1438 
Specific Feature Utilization:
1439 
 Number of Block RAM/FIFO:                3  out of     32     9%
1440 
    Number using Block RAM only:          3
1441 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1442 
 
1443 
---------------------------
1444 
 
1445 
====================================================================================
1446 
#                            SYNTHESIS DONE
1447 
#####################################################################################
1448 
 
1449 
#####################################################################################
1450 
#                            START SYNTHESIS (SPEED optimized)
1451 
#====================================================================================
1452 
# virtex5 (xc5vlx30ff324), speedgrade: -2
1453 
#====================================================================================
1454 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1455 
#     12          10          1         0            0          0            0
1456 
#====================================================================================
1457 
Clock to Setup on destination clock dco_clk
1458 
---------------+---------+---------+---------+---------+
1459 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1460 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1461 
---------------+---------+---------+---------+---------+
1462 
dco_clk        |   12.917|    6.918|         |    0.709|
1463 
---------------+---------+---------+---------+---------+
1464 
 
1465 
====================================================================================
1466 
Device utilization summary:
1467 
---------------------------
1468 
 
1469 
Selected Device : 5vlx30ff324-2
1470 
 
1471 
 
1472 
Slice Logic Utilization:
1473 
 Number of Slice Registers:             607  out of  19200     3%
1474 
 Number of Slice LUTs:                 1767  out of  19200     9%
1475 
    Number used as Logic:              1767  out of  19200     9%
1476 
 
1477 
Slice Logic Distribution:
1478 
 Number of LUT Flip Flop pairs used:   1900
1479 
   Number with an unused Flip Flop:    1293  out of   1900    68%
1480 
   Number with an unused LUT:           133  out of   1900     7%
1481 
   Number of fully used LUT-FF pairs:   474  out of   1900    24%
1482 
   Number of unique control sets:        54
1483 
 
1484 
IO Utilization:
1485 
 Number of IOs:                          80
1486 
 Number of bonded IOBs:                  80  out of    220    36%
1487 
 
1488 
Specific Feature Utilization:
1489 
 Number of Block RAM/FIFO:                3  out of     32     9%
1490 
    Number using Block RAM only:          3
1491 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1492 
 
1493 
---------------------------
1494 
 
1495 
====================================================================================
1496 
#                            SYNTHESIS DONE
1497 
#####################################################################################
1498 
 
1499 
#####################################################################################
1500 
#                            START SYNTHESIS (SPEED optimized)
1501 
#====================================================================================
1502 
# virtex5 (xc5vlx30ff324), speedgrade: -3
1503 
#====================================================================================
1504 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1505 
#     12          10          1         0            0          0            0
1506 
#====================================================================================
1507 
Clock to Setup on destination clock dco_clk
1508 
---------------+---------+---------+---------+---------+
1509 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1510 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1511 
---------------+---------+---------+---------+---------+
1512 
dco_clk        |   11.672|    5.947|         |    1.227|
1513 
---------------+---------+---------+---------+---------+
1514 
 
1515 
====================================================================================
1516 
Device utilization summary:
1517 
---------------------------
1518 
 
1519 
Selected Device : 5vlx30ff324-3
1520 
 
1521 
 
1522 
Slice Logic Utilization:
1523 
 Number of Slice Registers:             604  out of  19200     3%
1524 
 Number of Slice LUTs:                 1825  out of  19200     9%
1525 
    Number used as Logic:              1825  out of  19200     9%
1526 
 
1527 
Slice Logic Distribution:
1528 
 Number of LUT Flip Flop pairs used:   1941
1529 
   Number with an unused Flip Flop:    1337  out of   1941    68%
1530 
   Number with an unused LUT:           116  out of   1941     5%
1531 
   Number of fully used LUT-FF pairs:   488  out of   1941    25%
1532 
   Number of unique control sets:        54
1533 
 
1534 
IO Utilization:
1535 
 Number of IOs:                          80
1536 
 Number of bonded IOBs:                  80  out of    220    36%
1537 
 
1538 
Specific Feature Utilization:
1539 
 Number of Block RAM/FIFO:                3  out of     32     9%
1540 
    Number using Block RAM only:          3
1541 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1542 
 
1543 
---------------------------
1544 
 
1545 
====================================================================================
1546 
#                            SYNTHESIS DONE
1547 
#####################################################################################
1548 
 
1549 
#####################################################################################
1550 
#                            START SYNTHESIS (SPEED optimized)
1551 
#====================================================================================
1552 
# virtex6 (xc6vlx75tff484), speedgrade: -1
1553 
#====================================================================================
1554 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1555 
#     12          10          1         0            0          0            0
1556 
#====================================================================================
1557 
Clock to Setup on destination clock dco_clk
1558 
---------------+---------+---------+---------+---------+
1559 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1560 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1561 
---------------+---------+---------+---------+---------+
1562 
dco_clk        |   11.410|    5.680|    3.939|    0.973|
1563 
---------------+---------+---------+---------+---------+
1564 
 
1565 
====================================================================================
1566 
Device utilization summary:
1567 
---------------------------
1568 
 
1569 
Selected Device : 6vlx75tff484-1
1570 
 
1571 
 
1572 
Slice Logic Utilization:
1573 
 Number of Slice Registers:             605  out of  93120     0%
1574 
 Number of Slice LUTs:                 1744  out of  46560     3%
1575 
    Number used as Logic:              1744  out of  46560     3%
1576 
 
1577 
Slice Logic Distribution:
1578 
 Number of LUT Flip Flop pairs used:   1812
1579 
   Number with an unused Flip Flop:    1207  out of   1812    66%
1580 
   Number with an unused LUT:            68  out of   1812     3%
1581 
   Number of fully used LUT-FF pairs:   537  out of   1812    29%
1582 
   Number of unique control sets:        54
1583 
 
1584 
IO Utilization:
1585 
 Number of IOs:                          80
1586 
 Number of bonded IOBs:                  80  out of    240    33%
1587 
 
1588 
Specific Feature Utilization:
1589 
 Number of Block RAM/FIFO:                3  out of    156     1%
1590 
    Number using Block RAM only:          3
1591 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1592 
 
1593 
---------------------------
1594 
 
1595 
====================================================================================
1596 
#                            SYNTHESIS DONE
1597 
#####################################################################################
1598 
 
1599 
#####################################################################################
1600 
#                            START SYNTHESIS (SPEED optimized)
1601 
#====================================================================================
1602 
# virtex6 (xc6vlx75tff484), speedgrade: -2
1603 
#====================================================================================
1604 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1605 
#     12          10          1         0            0          0            0
1606 
#====================================================================================
1607 
Clock to Setup on destination clock dco_clk
1608 
---------------+---------+---------+---------+---------+
1609 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1610 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1611 
---------------+---------+---------+---------+---------+
1612 
dco_clk        |   10.199|    5.125|    2.930|    1.191|
1613 
---------------+---------+---------+---------+---------+
1614 
 
1615 
====================================================================================
1616 
Device utilization summary:
1617 
---------------------------
1618 
 
1619 
Selected Device : 6vlx75tff484-2
1620 
 
1621 
 
1622 
Slice Logic Utilization:
1623 
 Number of Slice Registers:             606  out of  93120     0%
1624 
 Number of Slice LUTs:                 1743  out of  46560     3%
1625 
    Number used as Logic:              1743  out of  46560     3%
1626 
 
1627 
Slice Logic Distribution:
1628 
 Number of LUT Flip Flop pairs used:   1802
1629 
   Number with an unused Flip Flop:    1196  out of   1802    66%
1630 
   Number with an unused LUT:            59  out of   1802     3%
1631 
   Number of fully used LUT-FF pairs:   547  out of   1802    30%
1632 
   Number of unique control sets:        54
1633 
 
1634 
IO Utilization:
1635 
 Number of IOs:                          80
1636 
 Number of bonded IOBs:                  80  out of    240    33%
1637 
 
1638 
Specific Feature Utilization:
1639 
 Number of Block RAM/FIFO:                3  out of    156     1%
1640 
    Number using Block RAM only:          3
1641 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1642 
 
1643 
---------------------------
1644 
 
1645 
====================================================================================
1646 
#                            SYNTHESIS DONE
1647 
#####################################################################################
1648 
 
1649 
#####################################################################################
1650 
#                            START SYNTHESIS (SPEED optimized)
1651 
#====================================================================================
1652 
# virtex6 (xc6vlx75tff484), speedgrade: -3
1653 
#====================================================================================
1654 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1655 
#     12          10          1         0            0          0            0
1656 
#====================================================================================
1657 
Clock to Setup on destination clock dco_clk
1658 
---------------+---------+---------+---------+---------+
1659 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1660 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1661 
---------------+---------+---------+---------+---------+
1662 
dco_clk        |    9.800|    4.522|    2.898|    0.918|
1663 
---------------+---------+---------+---------+---------+
1664 
 
1665 
====================================================================================
1666 
Device utilization summary:
1667 
---------------------------
1668 
 
1669 
Selected Device : 6vlx75tff484-3
1670 
 
1671 
 
1672 
Slice Logic Utilization:
1673 
 Number of Slice Registers:             604  out of  93120     0%
1674 
 Number of Slice LUTs:                 1731  out of  46560     3%
1675 
    Number used as Logic:              1731  out of  46560     3%
1676 
 
1677 
Slice Logic Distribution:
1678 
 Number of LUT Flip Flop pairs used:   1775
1679 
   Number with an unused Flip Flop:    1171  out of   1775    65%
1680 
   Number with an unused LUT:            44  out of   1775     2%
1681 
   Number of fully used LUT-FF pairs:   560  out of   1775    31%
1682 
   Number of unique control sets:        54
1683 
 
1684 
IO Utilization:
1685 
 Number of IOs:                          80
1686 
 Number of bonded IOBs:                  80  out of    240    33%
1687 
 
1688 
Specific Feature Utilization:
1689 
 Number of Block RAM/FIFO:                3  out of    156     1%
1690 
    Number using Block RAM only:          3
1691 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1692 
 
1693 
---------------------------
1694 
 
1695 
====================================================================================
1696 
#                            SYNTHESIS DONE
1697 
#####################################################################################
1698 
 
1699 
#####################################################################################
1700 
#                            START SYNTHESIS (SPEED optimized)
1701 
#====================================================================================
1702 
# spartan3 (xc3s400pq208), speedgrade: -4
1703 
#====================================================================================
1704 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1705 
#     12          10          1         1            0          0            0
1706 
#====================================================================================
1707 
Clock to Setup on destination clock dco_clk
1708 
---------------+---------+---------+---------+---------+
1709 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1710 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1711 
---------------+---------+---------+---------+---------+
1712 
dco_clk        |   44.914|   19.434|         |    3.952|
1713 
---------------+---------+---------+---------+---------+
1714 
 
1715 
====================================================================================
1716 
Device utilization summary:
1717 
---------------------------
1718 
 
1719 
Selected Device : 3s400pq208-4
1720 
 
1721 
 Number of Slices:                     1289  out of   3584    35%
1722 
 Number of Slice Flip Flops:            664  out of   7168     9%
1723 
 Number of 4 input LUTs:               2450  out of   7168    34%
1724 
 Number of IOs:                          80
1725 
 Number of bonded IOBs:                  80  out of    141    56%
1726 
 Number of BRAMs:                         6  out of     16    37%
1727 
 Number of GCLKs:                         1  out of      8    12%
1728 
 
1729 
---------------------------
1730 
 
1731 
====================================================================================
1732 
#                            SYNTHESIS DONE
1733 
#####################################################################################
1734 
 
1735 
#####################################################################################
1736 
#                            START SYNTHESIS (SPEED optimized)
1737 
#====================================================================================
1738 
# spartan3 (xc3s400pq208), speedgrade: -5
1739 
#====================================================================================
1740 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1741 
#     12          10          1         1            0          0            0
1742 
#====================================================================================
1743 
Clock to Setup on destination clock dco_clk
1744 
---------------+---------+---------+---------+---------+
1745 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1746 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1747 
---------------+---------+---------+---------+---------+
1748 
dco_clk        |   36.911|   16.671|         |    2.347|
1749 
---------------+---------+---------+---------+---------+
1750 
 
1751 
====================================================================================
1752 
Device utilization summary:
1753 
---------------------------
1754 
 
1755 
Selected Device : 3s400pq208-5
1756 
 
1757 
 Number of Slices:                     1287  out of   3584    35%
1758 
 Number of Slice Flip Flops:            664  out of   7168     9%
1759 
 Number of 4 input LUTs:               2446  out of   7168    34%
1760 
 Number of IOs:                          80
1761 
 Number of bonded IOBs:                  80  out of    141    56%
1762 
 Number of BRAMs:                         6  out of     16    37%
1763 
 Number of GCLKs:                         1  out of      8    12%
1764 
 
1765 
---------------------------
1766 
 
1767 
====================================================================================
1768 
#                            SYNTHESIS DONE
1769 
#####################################################################################
1770 
 
1771 
#####################################################################################
1772 
#                            START SYNTHESIS (SPEED optimized)
1773 
#====================================================================================
1774 
# spartan3e (xc3s500epq208), speedgrade: -4
1775 
#====================================================================================
1776 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1777 
#     12          10          1         1            0          0            0
1778 
#====================================================================================
1779 
Clock to Setup on destination clock dco_clk
1780 
---------------+---------+---------+---------+---------+
1781 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1782 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1783 
---------------+---------+---------+---------+---------+
1784 
dco_clk        |   36.683|   17.437|         |    1.757|
1785 
---------------+---------+---------+---------+---------+
1786 
 
1787 
====================================================================================
1788 
Device utilization summary:
1789 
---------------------------
1790 
 
1791 
Selected Device : 3s500epq208-4
1792 
 
1793 
 Number of Slices:                     1340  out of   4656    28%
1794 
 Number of Slice Flip Flops:            659  out of   9312     7%
1795 
 Number of 4 input LUTs:               2542  out of   9312    27%
1796 
 Number of IOs:                          80
1797 
 Number of bonded IOBs:                  80  out of    158    50%
1798 
 Number of BRAMs:                         6  out of     20    30%
1799 
 Number of GCLKs:                         1  out of     24     4%
1800 
 
1801 
---------------------------
1802 
 
1803 
====================================================================================
1804 
#                            SYNTHESIS DONE
1805 
#####################################################################################
1806 
 
1807 
#####################################################################################
1808 
#                            START SYNTHESIS (SPEED optimized)
1809 
#====================================================================================
1810 
# spartan3e (xc3s500epq208), speedgrade: -5
1811 
#====================================================================================
1812 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1813 
#     12          10          1         1            0          0            0
1814 
#====================================================================================
1815 
Clock to Setup on destination clock dco_clk
1816 
---------------+---------+---------+---------+---------+
1817 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1818 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1819 
---------------+---------+---------+---------+---------+
1820 
dco_clk        |   30.921|   14.965|         |    1.836|
1821 
---------------+---------+---------+---------+---------+
1822 
 
1823 
====================================================================================
1824 
Device utilization summary:
1825 
---------------------------
1826 
 
1827 
Selected Device : 3s500epq208-5
1828 
 
1829 
 Number of Slices:                     1341  out of   4656    28%
1830 
 Number of Slice Flip Flops:            661  out of   9312     7%
1831 
 Number of 4 input LUTs:               2543  out of   9312    27%
1832 
 Number of IOs:                          80
1833 
 Number of bonded IOBs:                  80  out of    158    50%
1834 
 Number of BRAMs:                         6  out of     20    30%
1835 
 Number of GCLKs:                         1  out of     24     4%
1836 
 
1837 
---------------------------
1838 
 
1839 
====================================================================================
1840 
#                            SYNTHESIS DONE
1841 
#####################################################################################
1842 
 
1843 
#####################################################################################
1844 
#                            START SYNTHESIS (SPEED optimized)
1845 
#====================================================================================
1846 
# spartan3a (xc3s700aft256), speedgrade: -4
1847 
#====================================================================================
1848 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1849 
#     12          10          1         1            0          0            0
1850 
#====================================================================================
1851 
Clock to Setup on destination clock dco_clk
1852 
---------------+---------+---------+---------+---------+
1853 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1854 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1855 
---------------+---------+---------+---------+---------+
1856 
dco_clk        |   37.809|   18.679|         |    1.994|
1857 
---------------+---------+---------+---------+---------+
1858 
 
1859 
====================================================================================
1860 
Device utilization summary:
1861 
---------------------------
1862 
 
1863 
Selected Device : 3s700aft256-4
1864 
 
1865 
 Number of Slices:                     1295  out of   5888    21%
1866 
 Number of Slice Flip Flops:            662  out of  11776     5%
1867 
 Number of 4 input LUTs:               2458  out of  11776    20%
1868 
 Number of IOs:                          80
1869 
 Number of bonded IOBs:                  80  out of    161    49%
1870 
 Number of BRAMs:                         5  out of     20    25%
1871 
 Number of GCLKs:                         1  out of     24     4%
1872 
 
1873 
---------------------------
1874 
 
1875 
====================================================================================
1876 
#                            SYNTHESIS DONE
1877 
#####################################################################################
1878 
 
1879 
#####################################################################################
1880 
#                            START SYNTHESIS (SPEED optimized)
1881 
#====================================================================================
1882 
# spartan3a (xc3s700aft256), speedgrade: -5
1883 
#====================================================================================
1884 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1885 
#     12          10          1         1            0          0            0
1886 
#====================================================================================
1887 
Clock to Setup on destination clock dco_clk
1888 
---------------+---------+---------+---------+---------+
1889 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1890 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1891 
---------------+---------+---------+---------+---------+
1892 
dco_clk        |   32.632|   15.638|         |    1.440|
1893 
---------------+---------+---------+---------+---------+
1894 
 
1895 
====================================================================================
1896 
Device utilization summary:
1897 
---------------------------
1898 
 
1899 
Selected Device : 3s700aft256-5
1900 
 
1901 
 Number of Slices:                     1287  out of   5888    21%
1902 
 Number of Slice Flip Flops:            665  out of  11776     5%
1903 
 Number of 4 input LUTs:               2440  out of  11776    20%
1904 
 Number of IOs:                          80
1905 
 Number of bonded IOBs:                  80  out of    161    49%
1906 
 Number of BRAMs:                         5  out of     20    25%
1907 
 Number of GCLKs:                         1  out of     24     4%
1908 
 
1909 
---------------------------
1910 
 
1911 
====================================================================================
1912 
#                            SYNTHESIS DONE
1913 
#####################################################################################
1914 
 
1915 
#####################################################################################
1916 
#                            START SYNTHESIS (SPEED optimized)
1917 
#====================================================================================
1918 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
1919 
#====================================================================================
1920 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1921 
#     12          10          1         1            0          0            0
1922 
#====================================================================================
1923 
Clock to Setup on destination clock dco_clk
1924 
---------------+---------+---------+---------+---------+
1925 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1926 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1927 
---------------+---------+---------+---------+---------+
1928 
dco_clk        |   37.582|   18.019|         |    2.349|
1929 
---------------+---------+---------+---------+---------+
1930 
 
1931 
====================================================================================
1932 
Device utilization summary:
1933 
---------------------------
1934 
 
1935 
Selected Device : 3sd1800acs484-4
1936 
 
1937 
 Number of Slices:                     1308  out of  16640     7%
1938 
 Number of Slice Flip Flops:            661  out of  33280     1%
1939 
 Number of 4 input LUTs:               2475  out of  33280     7%
1940 
 Number of IOs:                          80
1941 
 Number of bonded IOBs:                  80  out of    309    25%
1942 
 Number of BRAMs:                         5  out of     84     5%
1943 
 Number of GCLKs:                         1  out of     24     4%
1944 
 
1945 
---------------------------
1946 
 
1947 
====================================================================================
1948 
#                            SYNTHESIS DONE
1949 
#####################################################################################
1950 
 
1951 
#####################################################################################
1952 
#                            START SYNTHESIS (SPEED optimized)
1953 
#====================================================================================
1954 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
1955 
#====================================================================================
1956 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1957 
#     12          10          1         1            0          0            0
1958 
#====================================================================================
1959 
Clock to Setup on destination clock dco_clk
1960 
---------------+---------+---------+---------+---------+
1961 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1962 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1963 
---------------+---------+---------+---------+---------+
1964 
dco_clk        |   30.668|   15.727|         |    1.405|
1965 
---------------+---------+---------+---------+---------+
1966 
 
1967 
====================================================================================
1968 
Device utilization summary:
1969 
---------------------------
1970 
 
1971 
Selected Device : 3sd1800acs484-5
1972 
 
1973 
 Number of Slices:                     1309  out of  16640     7%
1974 
 Number of Slice Flip Flops:            661  out of  33280     1%
1975 
 Number of 4 input LUTs:               2475  out of  33280     7%
1976 
 Number of IOs:                          80
1977 
 Number of bonded IOBs:                  80  out of    309    25%
1978 
 Number of BRAMs:                         5  out of     84     5%
1979 
 Number of GCLKs:                         1  out of     24     4%
1980 
 
1981 
---------------------------
1982 
 
1983 
====================================================================================
1984 
#                            SYNTHESIS DONE
1985 
#####################################################################################
1986 
 
1987 
#####################################################################################
1988 
#                            START SYNTHESIS (SPEED optimized)
1989 
#====================================================================================
1990 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
1991 
#====================================================================================
1992 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1993 
#     12          10          1         1            0          0            0
1994 
#====================================================================================
1995 
Clock to Setup on destination clock dco_clk
1996 
---------------+---------+---------+---------+---------+
1997 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1998 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1999 
---------------+---------+---------+---------+---------+
2000 
dco_clk        |   28.667|   13.539|    6.291|    2.666|
2001 
---------------+---------+---------+---------+---------+
2002 
 
2003 
====================================================================================
2004 
Device utilization summary:
2005 
---------------------------
2006 
 
2007 
Selected Device : 6slx45tfgg484-2
2008 
 
2009 
 
2010 
Slice Logic Utilization:
2011 
 Number of Slice Registers:             650  out of  54576     1%
2012 
 Number of Slice LUTs:                 1963  out of  27288     7%
2013 
    Number used as Logic:              1963  out of  27288     7%
2014 
 
2015 
Slice Logic Distribution:
2016 
 Number of LUT Flip Flop pairs used:   2252
2017 
   Number with an unused Flip Flop:    1602  out of   2252    71%
2018 
   Number with an unused LUT:           289  out of   2252    12%
2019 
   Number of fully used LUT-FF pairs:   361  out of   2252    16%
2020 
   Number of unique control sets:        58
2021 
 
2022 
IO Utilization:
2023 
 Number of IOs:                          80
2024 
 Number of bonded IOBs:                  80  out of    296    27%
2025 
 
2026 
Specific Feature Utilization:
2027 
 Number of Block RAM/FIFO:                5  out of    348     1%
2028 
    Number using Block RAM only:          5
2029 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2030 
 
2031 
---------------------------
2032 
 
2033 
====================================================================================
2034 
#                            SYNTHESIS DONE
2035 
#####################################################################################
2036 
 
2037 
#####################################################################################
2038 
#                            START SYNTHESIS (SPEED optimized)
2039 
#====================================================================================
2040 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
2041 
#====================================================================================
2042 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2043 
#     12          10          1         1            0          0            0
2044 
#====================================================================================
2045 
Clock to Setup on destination clock dco_clk
2046 
---------------+---------+---------+---------+---------+
2047 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2048 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2049 
---------------+---------+---------+---------+---------+
2050 
dco_clk        |   21.530|   10.191|    3.300|    2.136|
2051 
---------------+---------+---------+---------+---------+
2052 
 
2053 
====================================================================================
2054 
Device utilization summary:
2055 
---------------------------
2056 
 
2057 
Selected Device : 6slx45tfgg484-3
2058 
 
2059 
 
2060 
Slice Logic Utilization:
2061 
 Number of Slice Registers:             648  out of  54576     1%
2062 
 Number of Slice LUTs:                 1997  out of  27288     7%
2063 
    Number used as Logic:              1997  out of  27288     7%
2064 
 
2065 
Slice Logic Distribution:
2066 
 Number of LUT Flip Flop pairs used:   2238
2067 
   Number with an unused Flip Flop:    1590  out of   2238    71%
2068 
   Number with an unused LUT:           241  out of   2238    10%
2069 
   Number of fully used LUT-FF pairs:   407  out of   2238    18%
2070 
   Number of unique control sets:        58
2071 
 
2072 
IO Utilization:
2073 
 Number of IOs:                          80
2074 
 Number of bonded IOBs:                  80  out of    296    27%
2075 
 
2076 
Specific Feature Utilization:
2077 
 Number of Block RAM/FIFO:                5  out of    348     1%
2078 
    Number using Block RAM only:          5
2079 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2080 
 
2081 
---------------------------
2082 
 
2083 
====================================================================================
2084 
#                            SYNTHESIS DONE
2085 
#####################################################################################
2086 
 
2087 
#####################################################################################
2088 
#                            START SYNTHESIS (SPEED optimized)
2089 
#====================================================================================
2090 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
2091 
#====================================================================================
2092 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2093 
#     12          10          1         1            0          0            0
2094 
#====================================================================================
2095 
Clock to Setup on destination clock dco_clk
2096 
---------------+---------+---------+---------+---------+
2097 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2098 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2099 
---------------+---------+---------+---------+---------+
2100 
dco_clk        |   19.564|    8.450|    3.090|    1.780|
2101 
---------------+---------+---------+---------+---------+
2102 
 
2103 
====================================================================================
2104 
Device utilization summary:
2105 
---------------------------
2106 
 
2107 
Selected Device : 6slx45tfgg484-4
2108 
 
2109 
 
2110 
Slice Logic Utilization:
2111 
 Number of Slice Registers:             647  out of  54576     1%
2112 
 Number of Slice LUTs:                 1993  out of  27288     7%
2113 
    Number used as Logic:              1993  out of  27288     7%
2114 
 
2115 
Slice Logic Distribution:
2116 
 Number of LUT Flip Flop pairs used:   2273
2117 
   Number with an unused Flip Flop:    1626  out of   2273    71%
2118 
   Number with an unused LUT:           280  out of   2273    12%
2119 
   Number of fully used LUT-FF pairs:   367  out of   2273    16%
2120 
   Number of unique control sets:        58
2121 
 
2122 
IO Utilization:
2123 
 Number of IOs:                          80
2124 
 Number of bonded IOBs:                  80  out of    296    27%
2125 
 
2126 
Specific Feature Utilization:
2127 
 Number of Block RAM/FIFO:                5  out of    348     1%
2128 
    Number using Block RAM only:          5
2129 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2130 
 
2131 
---------------------------
2132 
 
2133 
====================================================================================
2134 
#                            SYNTHESIS DONE
2135 
#####################################################################################
2136 
 
2137 
#####################################################################################
2138 
#                            START SYNTHESIS (SPEED optimized)
2139 
#====================================================================================
2140 
# virtex4 (xc4vlx25sf363), speedgrade: -10
2141 
#====================================================================================
2142 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2143 
#     12          10          1         1            0          0            0
2144 
#====================================================================================
2145 
Clock to Setup on destination clock dco_clk
2146 
---------------+---------+---------+---------+---------+
2147 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2148 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2149 
---------------+---------+---------+---------+---------+
2150 
dco_clk        |   22.936|   11.389|         |    0.991|
2151 
---------------+---------+---------+---------+---------+
2152 
 
2153 
====================================================================================
2154 
Device utilization summary:
2155 
---------------------------
2156 
 
2157 
Selected Device : 4vlx25sf363-10
2158 
 
2159 
 Number of Slices:                     1291  out of  10752    12%
2160 
 Number of Slice Flip Flops:            669  out of  21504     3%
2161 
 Number of 4 input LUTs:               2453  out of  21504    11%
2162 
 Number of IOs:                          80
2163 
 Number of bonded IOBs:                  80  out of    240    33%
2164 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
2165 
    Number used as RAMB16s:               5
2166 
 Number of GCLKs:                         1  out of     32     3%
2167 
 
2168 
---------------------------
2169 
 
2170 
====================================================================================
2171 
#                            SYNTHESIS DONE
2172 
#####################################################################################
2173 
 
2174 
#####################################################################################
2175 
#                            START SYNTHESIS (SPEED optimized)
2176 
#====================================================================================
2177 
# virtex4 (xc4vlx25sf363), speedgrade: -11
2178 
#====================================================================================
2179 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2180 
#     12          10          1         1            0          0            0
2181 
#====================================================================================
2182 
Clock to Setup on destination clock dco_clk
2183 
---------------+---------+---------+---------+---------+
2184 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2185 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2186 
---------------+---------+---------+---------+---------+
2187 
dco_clk        |   20.482|   10.061|         |    1.043|
2188 
---------------+---------+---------+---------+---------+
2189 
 
2190 
====================================================================================
2191 
Device utilization summary:
2192 
---------------------------
2193 
 
2194 
Selected Device : 4vlx25sf363-11
2195 
 
2196 
 Number of Slices:                     1297  out of  10752    12%
2197 
 Number of Slice Flip Flops:            666  out of  21504     3%
2198 
 Number of 4 input LUTs:               2463  out of  21504    11%
2199 
 Number of IOs:                          80
2200 
 Number of bonded IOBs:                  80  out of    240    33%
2201 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
2202 
    Number used as RAMB16s:               5
2203 
 Number of GCLKs:                         1  out of     32     3%
2204 
 
2205 
---------------------------
2206 
 
2207 
====================================================================================
2208 
#                            SYNTHESIS DONE
2209 
#####################################################################################
2210 
 
2211 
#####################################################################################
2212 
#                            START SYNTHESIS (SPEED optimized)
2213 
#====================================================================================
2214 
# virtex4 (xc4vlx25sf363), speedgrade: -12
2215 
#====================================================================================
2216 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2217 
#     12          10          1         1            0          0            0
2218 
#====================================================================================
2219 
Clock to Setup on destination clock dco_clk
2220 
---------------+---------+---------+---------+---------+
2221 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2222 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2223 
---------------+---------+---------+---------+---------+
2224 
dco_clk        |   16.872|    8.361|         |    1.448|
2225 
---------------+---------+---------+---------+---------+
2226 
 
2227 
====================================================================================
2228 
Device utilization summary:
2229 
---------------------------
2230 
 
2231 
Selected Device : 4vlx25sf363-12
2232 
 
2233 
 Number of Slices:                     1295  out of  10752    12%
2234 
 Number of Slice Flip Flops:            664  out of  21504     3%
2235 
 Number of 4 input LUTs:               2458  out of  21504    11%
2236 
 Number of IOs:                          80
2237 
 Number of bonded IOBs:                  80  out of    240    33%
2238 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
2239 
    Number used as RAMB16s:               5
2240 
 Number of GCLKs:                         1  out of     32     3%
2241 
 
2242 
---------------------------
2243 
 
2244 
====================================================================================
2245 
#                            SYNTHESIS DONE
2246 
#####################################################################################
2247 
 
2248 
#####################################################################################
2249 
#                            START SYNTHESIS (SPEED optimized)
2250 
#====================================================================================
2251 
# virtex5 (xc5vlx30ff324), speedgrade: -1
2252 
#====================================================================================
2253 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2254 
#     12          10          1         1            0          0            0
2255 
#====================================================================================
2256 
Clock to Setup on destination clock dco_clk
2257 
---------------+---------+---------+---------+---------+
2258 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2259 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2260 
---------------+---------+---------+---------+---------+
2261 
dco_clk        |   15.850|    7.763|         |    0.968|
2262 
---------------+---------+---------+---------+---------+
2263 
 
2264 
====================================================================================
2265 
Device utilization summary:
2266 
---------------------------
2267 
 
2268 
Selected Device : 5vlx30ff324-1
2269 
 
2270 
 
2271 
Slice Logic Utilization:
2272 
 Number of Slice Registers:             653  out of  19200     3%
2273 
 Number of Slice LUTs:                 1931  out of  19200    10%
2274 
    Number used as Logic:              1931  out of  19200    10%
2275 
 
2276 
Slice Logic Distribution:
2277 
 Number of LUT Flip Flop pairs used:   2200
2278 
   Number with an unused Flip Flop:    1547  out of   2200    70%
2279 
   Number with an unused LUT:           269  out of   2200    12%
2280 
   Number of fully used LUT-FF pairs:   384  out of   2200    17%
2281 
   Number of unique control sets:        57
2282 
 
2283 
IO Utilization:
2284 
 Number of IOs:                          80
2285 
 Number of bonded IOBs:                  80  out of    220    36%
2286 
 
2287 
Specific Feature Utilization:
2288 
 Number of Block RAM/FIFO:                3  out of     32     9%
2289 
    Number using Block RAM only:          3
2290 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2291 
 
2292 
---------------------------
2293 
 
2294 
====================================================================================
2295 
#                            SYNTHESIS DONE
2296 
#####################################################################################
2297 
 
2298 
#####################################################################################
2299 
#                            START SYNTHESIS (SPEED optimized)
2300 
#====================================================================================
2301 
# virtex5 (xc5vlx30ff324), speedgrade: -2
2302 
#====================================================================================
2303 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2304 
#     12          10          1         1            0          0            0
2305 
#====================================================================================
2306 
Clock to Setup on destination clock dco_clk
2307 
---------------+---------+---------+---------+---------+
2308 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2309 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2310 
---------------+---------+---------+---------+---------+
2311 
dco_clk        |   14.479|    6.626|         |    0.808|
2312 
---------------+---------+---------+---------+---------+
2313 
 
2314 
====================================================================================
2315 
Device utilization summary:
2316 
---------------------------
2317 
 
2318 
Selected Device : 5vlx30ff324-2
2319 
 
2320 
 
2321 
Slice Logic Utilization:
2322 
 Number of Slice Registers:             653  out of  19200     3%
2323 
 Number of Slice LUTs:                 1930  out of  19200    10%
2324 
    Number used as Logic:              1930  out of  19200    10%
2325 
 
2326 
Slice Logic Distribution:
2327 
 Number of LUT Flip Flop pairs used:   2169
2328 
   Number with an unused Flip Flop:    1516  out of   2169    69%
2329 
   Number with an unused LUT:           239  out of   2169    11%
2330 
   Number of fully used LUT-FF pairs:   414  out of   2169    19%
2331 
   Number of unique control sets:        57
2332 
 
2333 
IO Utilization:
2334 
 Number of IOs:                          80
2335 
 Number of bonded IOBs:                  80  out of    220    36%
2336 
 
2337 
Specific Feature Utilization:
2338 
 Number of Block RAM/FIFO:                3  out of     32     9%
2339 
    Number using Block RAM only:          3
2340 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2341 
 
2342 
---------------------------
2343 
 
2344 
====================================================================================
2345 
#                            SYNTHESIS DONE
2346 
#####################################################################################
2347 
 
2348 
#####################################################################################
2349 
#                            START SYNTHESIS (SPEED optimized)
2350 
#====================================================================================
2351 
# virtex5 (xc5vlx30ff324), speedgrade: -3
2352 
#====================================================================================
2353 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2354 
#     12          10          1         1            0          0            0
2355 
#====================================================================================
2356 
Clock to Setup on destination clock dco_clk
2357 
---------------+---------+---------+---------+---------+
2358 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2359 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2360 
---------------+---------+---------+---------+---------+
2361 
dco_clk        |   13.826|    6.662|         |    0.598|
2362 
---------------+---------+---------+---------+---------+
2363 
 
2364 
====================================================================================
2365 
Device utilization summary:
2366 
---------------------------
2367 
 
2368 
Selected Device : 5vlx30ff324-3
2369 
 
2370 
 
2371 
Slice Logic Utilization:
2372 
 Number of Slice Registers:             645  out of  19200     3%
2373 
 Number of Slice LUTs:                 1914  out of  19200     9%
2374 
    Number used as Logic:              1914  out of  19200     9%
2375 
 
2376 
Slice Logic Distribution:
2377 
 Number of LUT Flip Flop pairs used:   2169
2378 
   Number with an unused Flip Flop:    1524  out of   2169    70%
2379 
   Number with an unused LUT:           255  out of   2169    11%
2380 
   Number of fully used LUT-FF pairs:   390  out of   2169    17%
2381 
   Number of unique control sets:        57
2382 
 
2383 
IO Utilization:
2384 
 Number of IOs:                          80
2385 
 Number of bonded IOBs:                  80  out of    220    36%
2386 
 
2387 
Specific Feature Utilization:
2388 
 Number of Block RAM/FIFO:                3  out of     32     9%
2389 
    Number using Block RAM only:          3
2390 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2391 
 
2392 
---------------------------
2393 
 
2394 
====================================================================================
2395 
#                            SYNTHESIS DONE
2396 
#####################################################################################
2397 
 
2398 
#####################################################################################
2399 
#                            START SYNTHESIS (SPEED optimized)
2400 
#====================================================================================
2401 
# virtex6 (xc6vlx75tff484), speedgrade: -1
2402 
#====================================================================================
2403 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2404 
#     12          10          1         1            0          0            0
2405 
#====================================================================================
2406 
Clock to Setup on destination clock dco_clk
2407 
---------------+---------+---------+---------+---------+
2408 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2409 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2410 
---------------+---------+---------+---------+---------+
2411 
dco_clk        |   14.580|    6.885|    2.742|    1.067|
2412 
---------------+---------+---------+---------+---------+
2413 
 
2414 
====================================================================================
2415 
Device utilization summary:
2416 
---------------------------
2417 
 
2418 
Selected Device : 6vlx75tff484-1
2419 
 
2420 
 
2421 
Slice Logic Utilization:
2422 
 Number of Slice Registers:             651  out of  93120     0%
2423 
 Number of Slice LUTs:                 1902  out of  46560     4%
2424 
    Number used as Logic:              1902  out of  46560     4%
2425 
 
2426 
Slice Logic Distribution:
2427 
 Number of LUT Flip Flop pairs used:   2031
2428 
   Number with an unused Flip Flop:    1380  out of   2031    67%
2429 
   Number with an unused LUT:           129  out of   2031     6%
2430 
   Number of fully used LUT-FF pairs:   522  out of   2031    25%
2431 
   Number of unique control sets:        57
2432 
 
2433 
IO Utilization:
2434 
 Number of IOs:                          80
2435 
 Number of bonded IOBs:                  80  out of    240    33%
2436 
 
2437 
Specific Feature Utilization:
2438 
 Number of Block RAM/FIFO:                3  out of    156     1%
2439 
    Number using Block RAM only:          3
2440 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2441 
 
2442 
---------------------------
2443 
 
2444 
====================================================================================
2445 
#                            SYNTHESIS DONE
2446 
#####################################################################################
2447 
 
2448 
#####################################################################################
2449 
#                            START SYNTHESIS (SPEED optimized)
2450 
#====================================================================================
2451 
# virtex6 (xc6vlx75tff484), speedgrade: -2
2452 
#====================================================================================
2453 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2454 
#     12          10          1         1            0          0            0
2455 
#====================================================================================
2456 
Clock to Setup on destination clock dco_clk
2457 
---------------+---------+---------+---------+---------+
2458 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2459 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2460 
---------------+---------+---------+---------+---------+
2461 
dco_clk        |   11.529|    5.015|    2.160|    0.508|
2462 
---------------+---------+---------+---------+---------+
2463 
 
2464 
====================================================================================
2465 
Device utilization summary:
2466 
---------------------------
2467 
 
2468 
Selected Device : 6vlx75tff484-2
2469 
 
2470 
 
2471 
Slice Logic Utilization:
2472 
 Number of Slice Registers:             648  out of  93120     0%
2473 
 Number of Slice LUTs:                 1871  out of  46560     4%
2474 
    Number used as Logic:              1871  out of  46560     4%
2475 
 
2476 
Slice Logic Distribution:
2477 
 Number of LUT Flip Flop pairs used:   1978
2478 
   Number with an unused Flip Flop:    1330  out of   1978    67%
2479 
   Number with an unused LUT:           107  out of   1978     5%
2480 
   Number of fully used LUT-FF pairs:   541  out of   1978    27%
2481 
   Number of unique control sets:        57
2482 
 
2483 
IO Utilization:
2484 
 Number of IOs:                          80
2485 
 Number of bonded IOBs:                  80  out of    240    33%
2486 
 
2487 
Specific Feature Utilization:
2488 
 Number of Block RAM/FIFO:                3  out of    156     1%
2489 
    Number using Block RAM only:          3
2490 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2491 
 
2492 
---------------------------
2493 
 
2494 
====================================================================================
2495 
#                            SYNTHESIS DONE
2496 
#####################################################################################
2497 
 
2498 
#####################################################################################
2499 
#                            START SYNTHESIS (SPEED optimized)
2500 
#====================================================================================
2501 
# virtex6 (xc6vlx75tff484), speedgrade: -3
2502 
#====================================================================================
2503 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2504 
#     12          10          1         1            0          0            0
2505 
#====================================================================================
2506 
Clock to Setup on destination clock dco_clk
2507 
---------------+---------+---------+---------+---------+
2508 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2509 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2510 
---------------+---------+---------+---------+---------+
2511 
dco_clk        |   11.245|    5.248|    2.230|    0.869|
2512 
---------------+---------+---------+---------+---------+
2513 
 
2514 
====================================================================================
2515 
Device utilization summary:
2516 
---------------------------
2517 
 
2518 
Selected Device : 6vlx75tff484-3
2519 
 
2520 
 
2521 
Slice Logic Utilization:
2522 
 Number of Slice Registers:             645  out of  93120     0%
2523 
 Number of Slice LUTs:                 1849  out of  46560     3%
2524 
    Number used as Logic:              1849  out of  46560     3%
2525 
 
2526 
Slice Logic Distribution:
2527 
 Number of LUT Flip Flop pairs used:   1943
2528 
   Number with an unused Flip Flop:    1298  out of   1943    66%
2529 
   Number with an unused LUT:            94  out of   1943     4%
2530 
   Number of fully used LUT-FF pairs:   551  out of   1943    28%
2531 
   Number of unique control sets:        57
2532 
 
2533 
IO Utilization:
2534 
 Number of IOs:                          80
2535 
 Number of bonded IOBs:                  80  out of    240    33%
2536 
 
2537 
Specific Feature Utilization:
2538 
 Number of Block RAM/FIFO:                3  out of    156     1%
2539 
    Number using Block RAM only:          3
2540 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2541 
 
2542 
---------------------------
2543 
 
2544 
====================================================================================
2545 
#                            SYNTHESIS DONE
2546 
#####################################################################################
2547 
 
2548 
#####################################################################################
2549 
#                            START SYNTHESIS (SPEED optimized)
2550 
#====================================================================================
2551 
# spartan3 (xc3s400pq208), speedgrade: -4
2552 
#====================================================================================
2553 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2554 
#     12          10          1         1            1          0            0
2555 
#====================================================================================
2556 
Clock to Setup on destination clock dco_clk
2557 
---------------+---------+---------+---------+---------+
2558 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2559 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2560 
---------------+---------+---------+---------+---------+
2561 
dco_clk        |   39.083|   19.525|         |    2.462|
2562 
---------------+---------+---------+---------+---------+
2563 
 
2564 
====================================================================================
2565 
Device utilization summary:
2566 
---------------------------
2567 
 
2568 
Selected Device : 3s400pq208-4
2569 
 
2570 
 Number of Slices:                     1364  out of   3584    38%
2571 
 Number of Slice Flip Flops:            705  out of   7168     9%
2572 
 Number of 4 input LUTs:               2587  out of   7168    36%
2573 
 Number of IOs:                          80
2574 
 Number of bonded IOBs:                  80  out of    141    56%
2575 
 Number of BRAMs:                         6  out of     16    37%
2576 
 Number of GCLKs:                         1  out of      8    12%
2577 
 
2578 
---------------------------
2579 
 
2580 
====================================================================================
2581 
#                            SYNTHESIS DONE
2582 
#####################################################################################
2583 
 
2584 
#####################################################################################
2585 
#                            START SYNTHESIS (SPEED optimized)
2586 
#====================================================================================
2587 
# spartan3 (xc3s400pq208), speedgrade: -5
2588 
#====================================================================================
2589 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2590 
#     12          10          1         1            1          0            0
2591 
#====================================================================================
2592 
Clock to Setup on destination clock dco_clk
2593 
---------------+---------+---------+---------+---------+
2594 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2595 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2596 
---------------+---------+---------+---------+---------+
2597 
dco_clk        |   34.597|   16.374|         |    2.028|
2598 
---------------+---------+---------+---------+---------+
2599 
 
2600 
====================================================================================
2601 
Device utilization summary:
2602 
---------------------------
2603 
 
2604 
Selected Device : 3s400pq208-5
2605 
 
2606 
 Number of Slices:                     1363  out of   3584    38%
2607 
 Number of Slice Flip Flops:            703  out of   7168     9%
2608 
 Number of 4 input LUTs:               2582  out of   7168    36%
2609 
 Number of IOs:                          80
2610 
 Number of bonded IOBs:                  80  out of    141    56%
2611 
 Number of BRAMs:                         6  out of     16    37%
2612 
 Number of GCLKs:                         1  out of      8    12%
2613 
 
2614 
---------------------------
2615 
 
2616 
====================================================================================
2617 
#                            SYNTHESIS DONE
2618 
#####################################################################################
2619 
 
2620 
#####################################################################################
2621 
#                            START SYNTHESIS (SPEED optimized)
2622 
#====================================================================================
2623 
# spartan3e (xc3s500epq208), speedgrade: -4
2624 
#====================================================================================
2625 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2626 
#     12          10          1         1            1          0            0
2627 
#====================================================================================
2628 
Clock to Setup on destination clock dco_clk
2629 
---------------+---------+---------+---------+---------+
2630 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2631 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2632 
---------------+---------+---------+---------+---------+
2633 
dco_clk        |   36.723|   17.550|         |    1.704|
2634 
---------------+---------+---------+---------+---------+
2635 
 
2636 
====================================================================================
2637 
Device utilization summary:
2638 
---------------------------
2639 
 
2640 
Selected Device : 3s500epq208-4
2641 
 
2642 
 Number of Slices:                     1375  out of   4656    29%
2643 
 Number of Slice Flip Flops:            704  out of   9312     7%
2644 
 Number of 4 input LUTs:               2598  out of   9312    27%
2645 
 Number of IOs:                          80
2646 
 Number of bonded IOBs:                  80  out of    158    50%
2647 
 Number of BRAMs:                         6  out of     20    30%
2648 
 Number of GCLKs:                         1  out of     24     4%
2649 
 
2650 
---------------------------
2651 
 
2652 
====================================================================================
2653 
#                            SYNTHESIS DONE
2654 
#####################################################################################
2655 
 
2656 
#####################################################################################
2657 
#                            START SYNTHESIS (SPEED optimized)
2658 
#====================================================================================
2659 
# spartan3e (xc3s500epq208), speedgrade: -5
2660 
#====================================================================================
2661 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2662 
#     12          10          1         1            1          0            0
2663 
#====================================================================================
2664 
Clock to Setup on destination clock dco_clk
2665 
---------------+---------+---------+---------+---------+
2666 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2667 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2668 
---------------+---------+---------+---------+---------+
2669 
dco_clk        |   33.892|   16.075|         |    1.531|
2670 
---------------+---------+---------+---------+---------+
2671 
 
2672 
====================================================================================
2673 
Device utilization summary:
2674 
---------------------------
2675 
 
2676 
Selected Device : 3s500epq208-5
2677 
 
2678 
 Number of Slices:                     1374  out of   4656    29%
2679 
 Number of Slice Flip Flops:            704  out of   9312     7%
2680 
 Number of 4 input LUTs:               2600  out of   9312    27%
2681 
 Number of IOs:                          80
2682 
 Number of bonded IOBs:                  80  out of    158    50%
2683 
 Number of BRAMs:                         6  out of     20    30%
2684 
 Number of GCLKs:                         1  out of     24     4%
2685 
 
2686 
---------------------------
2687 
 
2688 
====================================================================================
2689 
#                            SYNTHESIS DONE
2690 
#####################################################################################
2691 
 
2692 
#####################################################################################
2693 
#                            START SYNTHESIS (SPEED optimized)
2694 
#====================================================================================
2695 
# spartan3a (xc3s700aft256), speedgrade: -4
2696 
#====================================================================================
2697 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2698 
#     12          10          1         1            1          0            0
2699 
#====================================================================================
2700 
Clock to Setup on destination clock dco_clk
2701 
---------------+---------+---------+---------+---------+
2702 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2703 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2704 
---------------+---------+---------+---------+---------+
2705 
dco_clk        |   37.898|   18.834|         |    2.651|
2706 
---------------+---------+---------+---------+---------+
2707 
 
2708 
====================================================================================
2709 
Device utilization summary:
2710 
---------------------------
2711 
 
2712 
Selected Device : 3s700aft256-4
2713 
 
2714 
 Number of Slices:                     1366  out of   5888    23%
2715 
 Number of Slice Flip Flops:            705  out of  11776     5%
2716 
 Number of 4 input LUTs:               2579  out of  11776    21%
2717 
 Number of IOs:                          80
2718 
 Number of bonded IOBs:                  80  out of    161    49%
2719 
 Number of BRAMs:                         5  out of     20    25%
2720 
 Number of GCLKs:                         1  out of     24     4%
2721 
 
2722 
---------------------------
2723 
 
2724 
====================================================================================
2725 
#                            SYNTHESIS DONE
2726 
#####################################################################################
2727 
 
2728 
#####################################################################################
2729 
#                            START SYNTHESIS (SPEED optimized)
2730 
#====================================================================================
2731 
# spartan3a (xc3s700aft256), speedgrade: -5
2732 
#====================================================================================
2733 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2734 
#     12          10          1         1            1          0            0
2735 
#====================================================================================
2736 
Clock to Setup on destination clock dco_clk
2737 
---------------+---------+---------+---------+---------+
2738 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2739 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2740 
---------------+---------+---------+---------+---------+
2741 
dco_clk        |   32.481|   16.177|         |    1.899|
2742 
---------------+---------+---------+---------+---------+
2743 
 
2744 
====================================================================================
2745 
Device utilization summary:
2746 
---------------------------
2747 
 
2748 
Selected Device : 3s700aft256-5
2749 
 
2750 
 Number of Slices:                     1363  out of   5888    23%
2751 
 Number of Slice Flip Flops:            702  out of  11776     5%
2752 
 Number of 4 input LUTs:               2567  out of  11776    21%
2753 
 Number of IOs:                          80
2754 
 Number of bonded IOBs:                  80  out of    161    49%
2755 
 Number of BRAMs:                         5  out of     20    25%
2756 
 Number of GCLKs:                         1  out of     24     4%
2757 
 
2758 
---------------------------
2759 
 
2760 
====================================================================================
2761 
#                            SYNTHESIS DONE
2762 
#####################################################################################
2763 
 
2764 
#####################################################################################
2765 
#                            START SYNTHESIS (SPEED optimized)
2766 
#====================================================================================
2767 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
2768 
#====================================================================================
2769 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2770 
#     12          10          1         1            1          0            0
2771 
#====================================================================================
2772 
Clock to Setup on destination clock dco_clk
2773 
---------------+---------+---------+---------+---------+
2774 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2775 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2776 
---------------+---------+---------+---------+---------+
2777 
dco_clk        |   37.761|   18.799|         |    2.703|
2778 
---------------+---------+---------+---------+---------+
2779 
 
2780 
====================================================================================
2781 
Device utilization summary:
2782 
---------------------------
2783 
 
2784 
Selected Device : 3sd1800acs484-4
2785 
 
2786 
 Number of Slices:                     1399  out of  16640     8%
2787 
 Number of Slice Flip Flops:            703  out of  33280     2%
2788 
 Number of 4 input LUTs:               2644  out of  33280     7%
2789 
 Number of IOs:                          80
2790 
 Number of bonded IOBs:                  80  out of    309    25%
2791 
 Number of BRAMs:                         5  out of     84     5%
2792 
 Number of GCLKs:                         1  out of     24     4%
2793 
 
2794 
---------------------------
2795 
 
2796 
====================================================================================
2797 
#                            SYNTHESIS DONE
2798 
#####################################################################################
2799 
 
2800 
#####################################################################################
2801 
#                            START SYNTHESIS (SPEED optimized)
2802 
#====================================================================================
2803 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
2804 
#====================================================================================
2805 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2806 
#     12          10          1         1            1          0            0
2807 
#====================================================================================
2808 
Clock to Setup on destination clock dco_clk
2809 
---------------+---------+---------+---------+---------+
2810 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2811 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2812 
---------------+---------+---------+---------+---------+
2813 
dco_clk        |   30.304|   15.692|         |    2.161|
2814 
---------------+---------+---------+---------+---------+
2815 
 
2816 
====================================================================================
2817 
Device utilization summary:
2818 
---------------------------
2819 
 
2820 
Selected Device : 3sd1800acs484-5
2821 
 
2822 
 Number of Slices:                     1393  out of  16640     8%
2823 
 Number of Slice Flip Flops:            702  out of  33280     2%
2824 
 Number of 4 input LUTs:               2624  out of  33280     7%
2825 
 Number of IOs:                          80
2826 
 Number of bonded IOBs:                  80  out of    309    25%
2827 
 Number of BRAMs:                         5  out of     84     5%
2828 
 Number of GCLKs:                         1  out of     24     4%
2829 
 
2830 
---------------------------
2831 
 
2832 
====================================================================================
2833 
#                            SYNTHESIS DONE
2834 
#####################################################################################
2835 
 
2836 
#####################################################################################
2837 
#                            START SYNTHESIS (SPEED optimized)
2838 
#====================================================================================
2839 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
2840 
#====================================================================================
2841 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2842 
#     12          10          1         1            1          0            0
2843 
#====================================================================================
2844 
Clock to Setup on destination clock dco_clk
2845 
---------------+---------+---------+---------+---------+
2846 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2847 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2848 
---------------+---------+---------+---------+---------+
2849 
dco_clk        |   29.068|   13.044|    5.203|    2.681|
2850 
---------------+---------+---------+---------+---------+
2851 
 
2852 
====================================================================================
2853 
Device utilization summary:
2854 
---------------------------
2855 
 
2856 
Selected Device : 6slx45tfgg484-2
2857 
 
2858 
 
2859 
Slice Logic Utilization:
2860 
 Number of Slice Registers:             694  out of  54576     1%
2861 
 Number of Slice LUTs:                 2065  out of  27288     7%
2862 
    Number used as Logic:              2065  out of  27288     7%
2863 
 
2864 
Slice Logic Distribution:
2865 
 Number of LUT Flip Flop pairs used:   2394
2866 
   Number with an unused Flip Flop:    1700  out of   2394    71%
2867 
   Number with an unused LUT:           329  out of   2394    13%
2868 
   Number of fully used LUT-FF pairs:   365  out of   2394    15%
2869 
   Number of unique control sets:        60
2870 
 
2871 
IO Utilization:
2872 
 Number of IOs:                          80
2873 
 Number of bonded IOBs:                  80  out of    296    27%
2874 
 
2875 
Specific Feature Utilization:
2876 
 Number of Block RAM/FIFO:                5  out of    348     1%
2877 
    Number using Block RAM only:          5
2878 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2879 
 
2880 
---------------------------
2881 
 
2882 
====================================================================================
2883 
#                            SYNTHESIS DONE
2884 
#####################################################################################
2885 
 
2886 
#####################################################################################
2887 
#                            START SYNTHESIS (SPEED optimized)
2888 
#====================================================================================
2889 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
2890 
#====================================================================================
2891 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2892 
#     12          10          1         1            1          0            0
2893 
#====================================================================================
2894 
Clock to Setup on destination clock dco_clk
2895 
---------------+---------+---------+---------+---------+
2896 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2897 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2898 
---------------+---------+---------+---------+---------+
2899 
dco_clk        |   21.814|   10.080|    3.646|    2.136|
2900 
---------------+---------+---------+---------+---------+
2901 
 
2902 
====================================================================================
2903 
Device utilization summary:
2904 
---------------------------
2905 
 
2906 
Selected Device : 6slx45tfgg484-3
2907 
 
2908 
 
2909 
Slice Logic Utilization:
2910 
 Number of Slice Registers:             689  out of  54576     1%
2911 
 Number of Slice LUTs:                 2015  out of  27288     7%
2912 
    Number used as Logic:              2015  out of  27288     7%
2913 
 
2914 
Slice Logic Distribution:
2915 
 Number of LUT Flip Flop pairs used:   2307
2916 
   Number with an unused Flip Flop:    1618  out of   2307    70%
2917 
   Number with an unused LUT:           292  out of   2307    12%
2918 
   Number of fully used LUT-FF pairs:   397  out of   2307    17%
2919 
   Number of unique control sets:        60
2920 
 
2921 
IO Utilization:
2922 
 Number of IOs:                          80
2923 
 Number of bonded IOBs:                  80  out of    296    27%
2924 
 
2925 
Specific Feature Utilization:
2926 
 Number of Block RAM/FIFO:                5  out of    348     1%
2927 
    Number using Block RAM only:          5
2928 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2929 
 
2930 
---------------------------
2931 
 
2932 
====================================================================================
2933 
#                            SYNTHESIS DONE
2934 
#####################################################################################
2935 
 
2936 
#####################################################################################
2937 
#                            START SYNTHESIS (SPEED optimized)
2938 
#====================================================================================
2939 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
2940 
#====================================================================================
2941 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2942 
#     12          10          1         1            1          0            0
2943 
#====================================================================================
2944 
Clock to Setup on destination clock dco_clk
2945 
---------------+---------+---------+---------+---------+
2946 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2947 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2948 
---------------+---------+---------+---------+---------+
2949 
dco_clk        |   19.974|    8.376|    3.701|    1.950|
2950 
---------------+---------+---------+---------+---------+
2951 
 
2952 
====================================================================================
2953 
Device utilization summary:
2954 
---------------------------
2955 
 
2956 
Selected Device : 6slx45tfgg484-4
2957 
 
2958 
 
2959 
Slice Logic Utilization:
2960 
 Number of Slice Registers:             689  out of  54576     1%
2961 
 Number of Slice LUTs:                 2022  out of  27288     7%
2962 
    Number used as Logic:              2022  out of  27288     7%
2963 
 
2964 
Slice Logic Distribution:
2965 
 Number of LUT Flip Flop pairs used:   2362
2966 
   Number with an unused Flip Flop:    1673  out of   2362    70%
2967 
   Number with an unused LUT:           340  out of   2362    14%
2968 
   Number of fully used LUT-FF pairs:   349  out of   2362    14%
2969 
   Number of unique control sets:        60
2970 
 
2971 
IO Utilization:
2972 
 Number of IOs:                          80
2973 
 Number of bonded IOBs:                  80  out of    296    27%
2974 
 
2975 
Specific Feature Utilization:
2976 
 Number of Block RAM/FIFO:                5  out of    348     1%
2977 
    Number using Block RAM only:          5
2978 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2979 
 
2980 
---------------------------
2981 
 
2982 
====================================================================================
2983 
#                            SYNTHESIS DONE
2984 
#####################################################################################
2985 
 
2986 
#####################################################################################
2987 
#                            START SYNTHESIS (SPEED optimized)
2988 
#====================================================================================
2989 
# virtex4 (xc4vlx25sf363), speedgrade: -10
2990 
#====================================================================================
2991 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2992 
#     12          10          1         1            1          0            0
2993 
#====================================================================================
2994 
Clock to Setup on destination clock dco_clk
2995 
---------------+---------+---------+---------+---------+
2996 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2997 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2998 
---------------+---------+---------+---------+---------+
2999 
dco_clk        |   24.000|   11.966|         |    1.676|
3000 
---------------+---------+---------+---------+---------+
3001 
 
3002 
====================================================================================
3003 
Device utilization summary:
3004 
---------------------------
3005 
 
3006 
Selected Device : 4vlx25sf363-10
3007 
 
3008 
 Number of Slices:                     1345  out of  10752    12%
3009 
 Number of Slice Flip Flops:            707  out of  21504     3%
3010 
 Number of 4 input LUTs:               2552  out of  21504    11%
3011 
 Number of IOs:                          80
3012 
 Number of bonded IOBs:                  80  out of    240    33%
3013 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3014 
    Number used as RAMB16s:               5
3015 
 Number of GCLKs:                         1  out of     32     3%
3016 
 
3017 
---------------------------
3018 
 
3019 
====================================================================================
3020 
#                            SYNTHESIS DONE
3021 
#####################################################################################
3022 
 
3023 
#####################################################################################
3024 
#                            START SYNTHESIS (SPEED optimized)
3025 
#====================================================================================
3026 
# virtex4 (xc4vlx25sf363), speedgrade: -11
3027 
#====================================================================================
3028 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3029 
#     12          10          1         1            1          0            0
3030 
#====================================================================================
3031 
Clock to Setup on destination clock dco_clk
3032 
---------------+---------+---------+---------+---------+
3033 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3034 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3035 
---------------+---------+---------+---------+---------+
3036 
dco_clk        |   20.580|   10.256|         |    0.832|
3037 
---------------+---------+---------+---------+---------+
3038 
 
3039 
====================================================================================
3040 
Device utilization summary:
3041 
---------------------------
3042 
 
3043 
Selected Device : 4vlx25sf363-11
3044 
 
3045 
 Number of Slices:                     1352  out of  10752    12%
3046 
 Number of Slice Flip Flops:            711  out of  21504     3%
3047 
 Number of 4 input LUTs:               2565  out of  21504    11%
3048 
 Number of IOs:                          80
3049 
 Number of bonded IOBs:                  80  out of    240    33%
3050 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3051 
    Number used as RAMB16s:               5
3052 
 Number of GCLKs:                         1  out of     32     3%
3053 
 
3054 
---------------------------
3055 
 
3056 
====================================================================================
3057 
#                            SYNTHESIS DONE
3058 
#####################################################################################
3059 
 
3060 
#####################################################################################
3061 
#                            START SYNTHESIS (SPEED optimized)
3062 
#====================================================================================
3063 
# virtex4 (xc4vlx25sf363), speedgrade: -12
3064 
#====================================================================================
3065 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3066 
#     12          10          1         1            1          0            0
3067 
#====================================================================================
3068 
Clock to Setup on destination clock dco_clk
3069 
---------------+---------+---------+---------+---------+
3070 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3071 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3072 
---------------+---------+---------+---------+---------+
3073 
dco_clk        |   19.686|    9.406|         |    0.747|
3074 
---------------+---------+---------+---------+---------+
3075 
 
3076 
====================================================================================
3077 
Device utilization summary:
3078 
---------------------------
3079 
 
3080 
Selected Device : 4vlx25sf363-12
3081 
 
3082 
 Number of Slices:                     1348  out of  10752    12%
3083 
 Number of Slice Flip Flops:            708  out of  21504     3%
3084 
 Number of 4 input LUTs:               2557  out of  21504    11%
3085 
 Number of IOs:                          80
3086 
 Number of bonded IOBs:                  80  out of    240    33%
3087 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3088 
    Number used as RAMB16s:               5
3089 
 Number of GCLKs:                         1  out of     32     3%
3090 
 
3091 
---------------------------
3092 
 
3093 
====================================================================================
3094 
#                            SYNTHESIS DONE
3095 
#####################################################################################
3096 
 
3097 
#####################################################################################
3098 
#                            START SYNTHESIS (SPEED optimized)
3099 
#====================================================================================
3100 
# virtex5 (xc5vlx30ff324), speedgrade: -1
3101 
#====================================================================================
3102 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3103 
#     12          10          1         1            1          0            0
3104 
#====================================================================================
3105 
Clock to Setup on destination clock dco_clk
3106 
---------------+---------+---------+---------+---------+
3107 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3108 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3109 
---------------+---------+---------+---------+---------+
3110 
dco_clk        |   16.698|    7.658|         |    0.969|
3111 
---------------+---------+---------+---------+---------+
3112 
 
3113 
====================================================================================
3114 
Device utilization summary:
3115 
---------------------------
3116 
 
3117 
Selected Device : 5vlx30ff324-1
3118 
 
3119 
 
3120 
Slice Logic Utilization:
3121 
 Number of Slice Registers:             696  out of  19200     3%
3122 
 Number of Slice LUTs:                 1979  out of  19200    10%
3123 
    Number used as Logic:              1979  out of  19200    10%
3124 
 
3125 
Slice Logic Distribution:
3126 
 Number of LUT Flip Flop pairs used:   2269
3127 
   Number with an unused Flip Flop:    1573  out of   2269    69%
3128 
   Number with an unused LUT:           290  out of   2269    12%
3129 
   Number of fully used LUT-FF pairs:   406  out of   2269    17%
3130 
   Number of unique control sets:        60
3131 
 
3132 
IO Utilization:
3133 
 Number of IOs:                          80
3134 
 Number of bonded IOBs:                  80  out of    220    36%
3135 
 
3136 
Specific Feature Utilization:
3137 
 Number of Block RAM/FIFO:                3  out of     32     9%
3138 
    Number using Block RAM only:          3
3139 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3140 
 
3141 
---------------------------
3142 
 
3143 
====================================================================================
3144 
#                            SYNTHESIS DONE
3145 
#####################################################################################
3146 
 
3147 
#####################################################################################
3148 
#                            START SYNTHESIS (SPEED optimized)
3149 
#====================================================================================
3150 
# virtex5 (xc5vlx30ff324), speedgrade: -2
3151 
#====================================================================================
3152 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3153 
#     12          10          1         1            1          0            0
3154 
#====================================================================================
3155 
Clock to Setup on destination clock dco_clk
3156 
---------------+---------+---------+---------+---------+
3157 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3158 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3159 
---------------+---------+---------+---------+---------+
3160 
dco_clk        |   15.386|    6.898|         |    1.121|
3161 
---------------+---------+---------+---------+---------+
3162 
 
3163 
====================================================================================
3164 
Device utilization summary:
3165 
---------------------------
3166 
 
3167 
Selected Device : 5vlx30ff324-2
3168 
 
3169 
 
3170 
Slice Logic Utilization:
3171 
 Number of Slice Registers:             695  out of  19200     3%
3172 
 Number of Slice LUTs:                 1982  out of  19200    10%
3173 
    Number used as Logic:              1982  out of  19200    10%
3174 
 
3175 
Slice Logic Distribution:
3176 
 Number of LUT Flip Flop pairs used:   2257
3177 
   Number with an unused Flip Flop:    1562  out of   2257    69%
3178 
   Number with an unused LUT:           275  out of   2257    12%
3179 
   Number of fully used LUT-FF pairs:   420  out of   2257    18%
3180 
   Number of unique control sets:        60
3181 
 
3182 
IO Utilization:
3183 
 Number of IOs:                          80
3184 
 Number of bonded IOBs:                  80  out of    220    36%
3185 
 
3186 
Specific Feature Utilization:
3187 
 Number of Block RAM/FIFO:                3  out of     32     9%
3188 
    Number using Block RAM only:          3
3189 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3190 
 
3191 
---------------------------
3192 
 
3193 
====================================================================================
3194 
#                            SYNTHESIS DONE
3195 
#####################################################################################
3196 
 
3197 
#####################################################################################
3198 
#                            START SYNTHESIS (SPEED optimized)
3199 
#====================================================================================
3200 
# virtex5 (xc5vlx30ff324), speedgrade: -3
3201 
#====================================================================================
3202 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3203 
#     12          10          1         1            1          0            0
3204 
#====================================================================================
3205 
Clock to Setup on destination clock dco_clk
3206 
---------------+---------+---------+---------+---------+
3207 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3208 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3209 
---------------+---------+---------+---------+---------+
3210 
dco_clk        |   12.988|    6.250|         |    0.606|
3211 
---------------+---------+---------+---------+---------+
3212 
 
3213 
====================================================================================
3214 
Device utilization summary:
3215 
---------------------------
3216 
 
3217 
Selected Device : 5vlx30ff324-3
3218 
 
3219 
 
3220 
Slice Logic Utilization:
3221 
 Number of Slice Registers:             687  out of  19200     3%
3222 
 Number of Slice LUTs:                 1957  out of  19200    10%
3223 
    Number used as Logic:              1957  out of  19200    10%
3224 
 
3225 
Slice Logic Distribution:
3226 
 Number of LUT Flip Flop pairs used:   2238
3227 
   Number with an unused Flip Flop:    1551  out of   2238    69%
3228 
   Number with an unused LUT:           281  out of   2238    12%
3229 
   Number of fully used LUT-FF pairs:   406  out of   2238    18%
3230 
   Number of unique control sets:        60
3231 
 
3232 
IO Utilization:
3233 
 Number of IOs:                          80
3234 
 Number of bonded IOBs:                  80  out of    220    36%
3235 
 
3236 
Specific Feature Utilization:
3237 
 Number of Block RAM/FIFO:                3  out of     32     9%
3238 
    Number using Block RAM only:          3
3239 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3240 
 
3241 
---------------------------
3242 
 
3243 
====================================================================================
3244 
#                            SYNTHESIS DONE
3245 
#####################################################################################
3246 
 
3247 
#####################################################################################
3248 
#                            START SYNTHESIS (SPEED optimized)
3249 
#====================================================================================
3250 
# virtex6 (xc6vlx75tff484), speedgrade: -1
3251 
#====================================================================================
3252 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3253 
#     12          10          1         1            1          0            0
3254 
#====================================================================================
3255 
Clock to Setup on destination clock dco_clk
3256 
---------------+---------+---------+---------+---------+
3257 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3258 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3259 
---------------+---------+---------+---------+---------+
3260 
dco_clk        |   12.982|    6.215|    3.219|    0.798|
3261 
---------------+---------+---------+---------+---------+
3262 
 
3263 
====================================================================================
3264 
Device utilization summary:
3265 
---------------------------
3266 
 
3267 
Selected Device : 6vlx75tff484-1
3268 
 
3269 
 
3270 
Slice Logic Utilization:
3271 
 Number of Slice Registers:             692  out of  93120     0%
3272 
 Number of Slice LUTs:                 1949  out of  46560     4%
3273 
    Number used as Logic:              1949  out of  46560     4%
3274 
 
3275 
Slice Logic Distribution:
3276 
 Number of LUT Flip Flop pairs used:   2113
3277 
   Number with an unused Flip Flop:    1421  out of   2113    67%
3278 
   Number with an unused LUT:           164  out of   2113     7%
3279 
   Number of fully used LUT-FF pairs:   528  out of   2113    24%
3280 
   Number of unique control sets:        60
3281 
 
3282 
IO Utilization:
3283 
 Number of IOs:                          80
3284 
 Number of bonded IOBs:                  80  out of    240    33%
3285 
 
3286 
Specific Feature Utilization:
3287 
 Number of Block RAM/FIFO:                3  out of    156     1%
3288 
    Number using Block RAM only:          3
3289 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3290 
 
3291 
---------------------------
3292 
 
3293 
====================================================================================
3294 
#                            SYNTHESIS DONE
3295 
#####################################################################################
3296 
 
3297 
#####################################################################################
3298 
#                            START SYNTHESIS (SPEED optimized)
3299 
#====================================================================================
3300 
# virtex6 (xc6vlx75tff484), speedgrade: -2
3301 
#====================================================================================
3302 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3303 
#     12          10          1         1            1          0            0
3304 
#====================================================================================
3305 
Clock to Setup on destination clock dco_clk
3306 
---------------+---------+---------+---------+---------+
3307 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3308 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3309 
---------------+---------+---------+---------+---------+
3310 
dco_clk        |   12.508|    5.907|    2.273|    1.135|
3311 
---------------+---------+---------+---------+---------+
3312 
 
3313 
====================================================================================
3314 
Device utilization summary:
3315 
---------------------------
3316 
 
3317 
Selected Device : 6vlx75tff484-2
3318 
 
3319 
 
3320 
Slice Logic Utilization:
3321 
 Number of Slice Registers:             691  out of  93120     0%
3322 
 Number of Slice LUTs:                 1942  out of  46560     4%
3323 
    Number used as Logic:              1942  out of  46560     4%
3324 
 
3325 
Slice Logic Distribution:
3326 
 Number of LUT Flip Flop pairs used:   2099
3327 
   Number with an unused Flip Flop:    1408  out of   2099    67%
3328 
   Number with an unused LUT:           157  out of   2099     7%
3329 
   Number of fully used LUT-FF pairs:   534  out of   2099    25%
3330 
   Number of unique control sets:        60
3331 
 
3332 
IO Utilization:
3333 
 Number of IOs:                          80
3334 
 Number of bonded IOBs:                  80  out of    240    33%
3335 
 
3336 
Specific Feature Utilization:
3337 
 Number of Block RAM/FIFO:                3  out of    156     1%
3338 
    Number using Block RAM only:          3
3339 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3340 
 
3341 
---------------------------
3342 
 
3343 
====================================================================================
3344 
#                            SYNTHESIS DONE
3345 
#####################################################################################
3346 
 
3347 
#####################################################################################
3348 
#                            START SYNTHESIS (SPEED optimized)
3349 
#====================================================================================
3350 
# virtex6 (xc6vlx75tff484), speedgrade: -3
3351 
#====================================================================================
3352 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3353 
#     12          10          1         1            1          0            0
3354 
#====================================================================================
3355 
Clock to Setup on destination clock dco_clk
3356 
---------------+---------+---------+---------+---------+
3357 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3358 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3359 
---------------+---------+---------+---------+---------+
3360 
dco_clk        |   11.123|    5.148|    2.809|    0.757|
3361 
---------------+---------+---------+---------+---------+
3362 
 
3363 
====================================================================================
3364 
Device utilization summary:
3365 
---------------------------
3366 
 
3367 
Selected Device : 6vlx75tff484-3
3368 
 
3369 
 
3370 
Slice Logic Utilization:
3371 
 Number of Slice Registers:             688  out of  93120     0%
3372 
 Number of Slice LUTs:                 1911  out of  46560     4%
3373 
    Number used as Logic:              1911  out of  46560     4%
3374 
 
3375 
Slice Logic Distribution:
3376 
 Number of LUT Flip Flop pairs used:   2050
3377 
   Number with an unused Flip Flop:    1362  out of   2050    66%
3378 
   Number with an unused LUT:           139  out of   2050     6%
3379 
   Number of fully used LUT-FF pairs:   549  out of   2050    26%
3380 
   Number of unique control sets:        60
3381 
 
3382 
IO Utilization:
3383 
 Number of IOs:                          80
3384 
 Number of bonded IOBs:                  80  out of    240    33%
3385 
 
3386 
Specific Feature Utilization:
3387 
 Number of Block RAM/FIFO:                3  out of    156     1%
3388 
    Number using Block RAM only:          3
3389 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3390 
 
3391 
---------------------------
3392 
 
3393 
====================================================================================
3394 
#                            SYNTHESIS DONE
3395 
#####################################################################################
3396 
 
3397 
#####################################################################################
3398 
#                            START SYNTHESIS (SPEED optimized)
3399 
#====================================================================================
3400 
# spartan3 (xc3s400pq208), speedgrade: -4
3401 
#====================================================================================
3402 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3403 
#     12          10          1         1            1          1            0
3404 
#====================================================================================
3405 
Clock to Setup on destination clock dco_clk
3406 
---------------+---------+---------+---------+---------+
3407 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3408 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3409 
---------------+---------+---------+---------+---------+
3410 
dco_clk        |   39.704|   19.787|         |    3.074|
3411 
---------------+---------+---------+---------+---------+
3412 
 
3413 
====================================================================================
3414 
Device utilization summary:
3415 
---------------------------
3416 
 
3417 
Selected Device : 3s400pq208-4
3418 
 
3419 
 Number of Slices:                     1407  out of   3584    39%
3420 
 Number of Slice Flip Flops:            745  out of   7168    10%
3421 
 Number of 4 input LUTs:               2665  out of   7168    37%
3422 
 Number of IOs:                          80
3423 
 Number of bonded IOBs:                  80  out of    141    56%
3424 
 Number of BRAMs:                         6  out of     16    37%
3425 
 Number of GCLKs:                         1  out of      8    12%
3426 
 
3427 
---------------------------
3428 
 
3429 
====================================================================================
3430 
#                            SYNTHESIS DONE
3431 
#####################################################################################
3432 
 
3433 
#####################################################################################
3434 
#                            START SYNTHESIS (SPEED optimized)
3435 
#====================================================================================
3436 
# spartan3 (xc3s400pq208), speedgrade: -5
3437 
#====================================================================================
3438 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3439 
#     12          10          1         1            1          1            0
3440 
#====================================================================================
3441 
Clock to Setup on destination clock dco_clk
3442 
---------------+---------+---------+---------+---------+
3443 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3444 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3445 
---------------+---------+---------+---------+---------+
3446 
dco_clk        |   36.126|   17.381|         |    2.467|
3447 
---------------+---------+---------+---------+---------+
3448 
 
3449 
====================================================================================
3450 
Device utilization summary:
3451 
---------------------------
3452 
 
3453 
Selected Device : 3s400pq208-5
3454 
 
3455 
 Number of Slices:                     1408  out of   3584    39%
3456 
 Number of Slice Flip Flops:            749  out of   7168    10%
3457 
 Number of 4 input LUTs:               2666  out of   7168    37%
3458 
 Number of IOs:                          80
3459 
 Number of bonded IOBs:                  80  out of    141    56%
3460 
 Number of BRAMs:                         6  out of     16    37%
3461 
 Number of GCLKs:                         1  out of      8    12%
3462 
 
3463 
---------------------------
3464 
 
3465 
====================================================================================
3466 
#                            SYNTHESIS DONE
3467 
#####################################################################################
3468 
 
3469 
#####################################################################################
3470 
#                            START SYNTHESIS (SPEED optimized)
3471 
#====================================================================================
3472 
# spartan3e (xc3s500epq208), speedgrade: -4
3473 
#====================================================================================
3474 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3475 
#     12          10          1         1            1          1            0
3476 
#====================================================================================
3477 
Clock to Setup on destination clock dco_clk
3478 
---------------+---------+---------+---------+---------+
3479 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3480 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3481 
---------------+---------+---------+---------+---------+
3482 
dco_clk        |   36.551|   18.269|         |    1.541|
3483 
---------------+---------+---------+---------+---------+
3484 
 
3485 
====================================================================================
3486 
Device utilization summary:
3487 
---------------------------
3488 
 
3489 
Selected Device : 3s500epq208-4
3490 
 
3491 
 Number of Slices:                     1413  out of   4656    30%
3492 
 Number of Slice Flip Flops:            740  out of   9312     7%
3493 
 Number of 4 input LUTs:               2673  out of   9312    28%
3494 
 Number of IOs:                          80
3495 
 Number of bonded IOBs:                  80  out of    158    50%
3496 
 Number of BRAMs:                         6  out of     20    30%
3497 
 Number of GCLKs:                         1  out of     24     4%
3498 
 
3499 
---------------------------
3500 
 
3501 
====================================================================================
3502 
#                            SYNTHESIS DONE
3503 
#####################################################################################
3504 
 
3505 
#####################################################################################
3506 
#                            START SYNTHESIS (SPEED optimized)
3507 
#====================================================================================
3508 
# spartan3e (xc3s500epq208), speedgrade: -5
3509 
#====================================================================================
3510 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3511 
#     12          10          1         1            1          1            0
3512 
#====================================================================================
3513 
Clock to Setup on destination clock dco_clk
3514 
---------------+---------+---------+---------+---------+
3515 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3516 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3517 
---------------+---------+---------+---------+---------+
3518 
dco_clk        |   33.042|   16.542|         |    1.590|
3519 
---------------+---------+---------+---------+---------+
3520 
 
3521 
====================================================================================
3522 
Device utilization summary:
3523 
---------------------------
3524 
 
3525 
Selected Device : 3s500epq208-5
3526 
 
3527 
 Number of Slices:                     1414  out of   4656    30%
3528 
 Number of Slice Flip Flops:            740  out of   9312     7%
3529 
 Number of 4 input LUTs:               2675  out of   9312    28%
3530 
 Number of IOs:                          80
3531 
 Number of bonded IOBs:                  80  out of    158    50%
3532 
 Number of BRAMs:                         6  out of     20    30%
3533 
 Number of GCLKs:                         1  out of     24     4%
3534 
 
3535 
---------------------------
3536 
 
3537 
====================================================================================
3538 
#                            SYNTHESIS DONE
3539 
#####################################################################################
3540 
 
3541 
#####################################################################################
3542 
#                            START SYNTHESIS (SPEED optimized)
3543 
#====================================================================================
3544 
# spartan3a (xc3s700aft256), speedgrade: -4
3545 
#====================================================================================
3546 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3547 
#     12          10          1         1            1          1            0
3548 
#====================================================================================
3549 
Clock to Setup on destination clock dco_clk
3550 
---------------+---------+---------+---------+---------+
3551 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3552 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3553 
---------------+---------+---------+---------+---------+
3554 
dco_clk        |   40.202|   20.226|         |    1.744|
3555 
---------------+---------+---------+---------+---------+
3556 
 
3557 
====================================================================================
3558 
Device utilization summary:
3559 
---------------------------
3560 
 
3561 
Selected Device : 3s700aft256-4
3562 
 
3563 
 Number of Slices:                     1392  out of   5888    23%
3564 
 Number of Slice Flip Flops:            744  out of  11776     6%
3565 
 Number of 4 input LUTs:               2630  out of  11776    22%
3566 
 Number of IOs:                          80
3567 
 Number of bonded IOBs:                  80  out of    161    49%
3568 
 Number of BRAMs:                         5  out of     20    25%
3569 
 Number of GCLKs:                         1  out of     24     4%
3570 
 
3571 
---------------------------
3572 
 
3573 
====================================================================================
3574 
#                            SYNTHESIS DONE
3575 
#####################################################################################
3576 
 
3577 
#####################################################################################
3578 
#                            START SYNTHESIS (SPEED optimized)
3579 
#====================================================================================
3580 
# spartan3a (xc3s700aft256), speedgrade: -5
3581 
#====================================================================================
3582 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3583 
#     12          10          1         1            1          1            0
3584 
#====================================================================================
3585 
Clock to Setup on destination clock dco_clk
3586 
---------------+---------+---------+---------+---------+
3587 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3588 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3589 
---------------+---------+---------+---------+---------+
3590 
dco_clk        |   33.669|   16.672|         |    1.350|
3591 
---------------+---------+---------+---------+---------+
3592 
 
3593 
====================================================================================
3594 
Device utilization summary:
3595 
---------------------------
3596 
 
3597 
Selected Device : 3s700aft256-5
3598 
 
3599 
 Number of Slices:                     1400  out of   5888    23%
3600 
 Number of Slice Flip Flops:            749  out of  11776     6%
3601 
 Number of 4 input LUTs:               2654  out of  11776    22%
3602 
 Number of IOs:                          80
3603 
 Number of bonded IOBs:                  80  out of    161    49%
3604 
 Number of BRAMs:                         5  out of     20    25%
3605 
 Number of GCLKs:                         1  out of     24     4%
3606 
 
3607 
---------------------------
3608 
 
3609 
====================================================================================
3610 
#                            SYNTHESIS DONE
3611 
#####################################################################################
3612 
 
3613 
#####################################################################################
3614 
#                            START SYNTHESIS (SPEED optimized)
3615 
#====================================================================================
3616 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
3617 
#====================================================================================
3618 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3619 
#     12          10          1         1            1          1            0
3620 
#====================================================================================
3621 
Clock to Setup on destination clock dco_clk
3622 
---------------+---------+---------+---------+---------+
3623 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3624 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3625 
---------------+---------+---------+---------+---------+
3626 
dco_clk        |   41.154|   19.523|         |    1.712|
3627 
---------------+---------+---------+---------+---------+
3628 
 
3629 
====================================================================================
3630 
Device utilization summary:
3631 
---------------------------
3632 
 
3633 
Selected Device : 3sd1800acs484-4
3634 
 
3635 
 Number of Slices:                     1393  out of  16640     8%
3636 
 Number of Slice Flip Flops:            743  out of  33280     2%
3637 
 Number of 4 input LUTs:               2631  out of  33280     7%
3638 
 Number of IOs:                          80
3639 
 Number of bonded IOBs:                  80  out of    309    25%
3640 
 Number of BRAMs:                         5  out of     84     5%
3641 
 Number of GCLKs:                         1  out of     24     4%
3642 
 
3643 
---------------------------
3644 
 
3645 
====================================================================================
3646 
#                            SYNTHESIS DONE
3647 
#####################################################################################
3648 
 
3649 
#####################################################################################
3650 
#                            START SYNTHESIS (SPEED optimized)
3651 
#====================================================================================
3652 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
3653 
#====================================================================================
3654 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3655 
#     12          10          1         1            1          1            0
3656 
#====================================================================================
3657 
Clock to Setup on destination clock dco_clk
3658 
---------------+---------+---------+---------+---------+
3659 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3660 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3661 
---------------+---------+---------+---------+---------+
3662 
dco_clk        |   34.646|   17.254|         |    1.440|
3663 
---------------+---------+---------+---------+---------+
3664 
 
3665 
====================================================================================
3666 
Device utilization summary:
3667 
---------------------------
3668 
 
3669 
Selected Device : 3sd1800acs484-5
3670 
 
3671 
 Number of Slices:                     1411  out of  16640     8%
3672 
 Number of Slice Flip Flops:            743  out of  33280     2%
3673 
 Number of 4 input LUTs:               2666  out of  33280     8%
3674 
 Number of IOs:                          80
3675 
 Number of bonded IOBs:                  80  out of    309    25%
3676 
 Number of BRAMs:                         5  out of     84     5%
3677 
 Number of GCLKs:                         1  out of     24     4%
3678 
 
3679 
---------------------------
3680 
 
3681 
====================================================================================
3682 
#                            SYNTHESIS DONE
3683 
#####################################################################################
3684 
 
3685 
#####################################################################################
3686 
#                            START SYNTHESIS (SPEED optimized)
3687 
#====================================================================================
3688 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
3689 
#====================================================================================
3690 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3691 
#     12          10          1         1            1          1            0
3692 
#====================================================================================
3693 
Clock to Setup on destination clock dco_clk
3694 
---------------+---------+---------+---------+---------+
3695 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3696 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3697 
---------------+---------+---------+---------+---------+
3698 
dco_clk        |   37.179|   16.588|    5.255|    2.769|
3699 
---------------+---------+---------+---------+---------+
3700 
 
3701 
====================================================================================
3702 
Device utilization summary:
3703 
---------------------------
3704 
 
3705 
Selected Device : 6slx45tfgg484-2
3706 
 
3707 
 
3708 
Slice Logic Utilization:
3709 
 Number of Slice Registers:             733  out of  54576     1%
3710 
 Number of Slice LUTs:                 2129  out of  27288     7%
3711 
    Number used as Logic:              2129  out of  27288     7%
3712 
 
3713 
Slice Logic Distribution:
3714 
 Number of LUT Flip Flop pairs used:   2484
3715 
   Number with an unused Flip Flop:    1751  out of   2484    70%
3716 
   Number with an unused LUT:           355  out of   2484    14%
3717 
   Number of fully used LUT-FF pairs:   378  out of   2484    15%
3718 
   Number of unique control sets:        64
3719 
 
3720 
IO Utilization:
3721 
 Number of IOs:                          80
3722 
 Number of bonded IOBs:                  80  out of    296    27%
3723 
 
3724 
Specific Feature Utilization:
3725 
 Number of Block RAM/FIFO:                5  out of    348     1%
3726 
    Number using Block RAM only:          5
3727 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3728 
 
3729 
---------------------------
3730 
 
3731 
====================================================================================
3732 
#                            SYNTHESIS DONE
3733 
#####################################################################################
3734 
 
3735 
#####################################################################################
3736 
#                            START SYNTHESIS (SPEED optimized)
3737 
#====================================================================================
3738 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
3739 
#====================================================================================
3740 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3741 
#     12          10          1         1            1          1            0
3742 
#====================================================================================
3743 
Clock to Setup on destination clock dco_clk
3744 
---------------+---------+---------+---------+---------+
3745 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3746 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3747 
---------------+---------+---------+---------+---------+
3748 
dco_clk        |   23.944|   10.602|    4.122|    2.062|
3749 
---------------+---------+---------+---------+---------+
3750 
 
3751 
====================================================================================
3752 
Device utilization summary:
3753 
---------------------------
3754 
 
3755 
Selected Device : 6slx45tfgg484-3
3756 
 
3757 
 
3758 
Slice Logic Utilization:
3759 
 Number of Slice Registers:             731  out of  54576     1%
3760 
 Number of Slice LUTs:                 2069  out of  27288     7%
3761 
    Number used as Logic:              2069  out of  27288     7%
3762 
 
3763 
Slice Logic Distribution:
3764 
 Number of LUT Flip Flop pairs used:   2455
3765 
   Number with an unused Flip Flop:    1724  out of   2455    70%
3766 
   Number with an unused LUT:           386  out of   2455    15%
3767 
   Number of fully used LUT-FF pairs:   345  out of   2455    14%
3768 
   Number of unique control sets:        64
3769 
 
3770 
IO Utilization:
3771 
 Number of IOs:                          80
3772 
 Number of bonded IOBs:                  80  out of    296    27%
3773 
 
3774 
Specific Feature Utilization:
3775 
 Number of Block RAM/FIFO:                5  out of    348     1%
3776 
    Number using Block RAM only:          5
3777 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3778 
 
3779 
---------------------------
3780 
 
3781 
====================================================================================
3782 
#                            SYNTHESIS DONE
3783 
#####################################################################################
3784 
 
3785 
#####################################################################################
3786 
#                            START SYNTHESIS (SPEED optimized)
3787 
#====================================================================================
3788 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
3789 
#====================================================================================
3790 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3791 
#     12          10          1         1            1          1            0
3792 
#====================================================================================
3793 
Clock to Setup on destination clock dco_clk
3794 
---------------+---------+---------+---------+---------+
3795 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3796 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3797 
---------------+---------+---------+---------+---------+
3798 
dco_clk        |   23.273|    9.827|    4.275|    1.961|
3799 
---------------+---------+---------+---------+---------+
3800 
 
3801 
====================================================================================
3802 
Device utilization summary:
3803 
---------------------------
3804 
 
3805 
Selected Device : 6slx45tfgg484-4
3806 
 
3807 
 
3808 
Slice Logic Utilization:
3809 
 Number of Slice Registers:             732  out of  54576     1%
3810 
 Number of Slice LUTs:                 2077  out of  27288     7%
3811 
    Number used as Logic:              2077  out of  27288     7%
3812 
 
3813 
Slice Logic Distribution:
3814 
 Number of LUT Flip Flop pairs used:   2435
3815 
   Number with an unused Flip Flop:    1703  out of   2435    69%
3816 
   Number with an unused LUT:           358  out of   2435    14%
3817 
   Number of fully used LUT-FF pairs:   374  out of   2435    15%
3818 
   Number of unique control sets:        64
3819 
 
3820 
IO Utilization:
3821 
 Number of IOs:                          80
3822 
 Number of bonded IOBs:                  80  out of    296    27%
3823 
 
3824 
Specific Feature Utilization:
3825 
 Number of Block RAM/FIFO:                5  out of    348     1%
3826 
    Number using Block RAM only:          5
3827 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3828 
 
3829 
---------------------------
3830 
 
3831 
====================================================================================
3832 
#                            SYNTHESIS DONE
3833 
#####################################################################################
3834 
 
3835 
#####################################################################################
3836 
#                            START SYNTHESIS (SPEED optimized)
3837 
#====================================================================================
3838 
# virtex4 (xc4vlx25sf363), speedgrade: -10
3839 
#====================================================================================
3840 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3841 
#     12          10          1         1            1          1            0
3842 
#====================================================================================
3843 
Clock to Setup on destination clock dco_clk
3844 
---------------+---------+---------+---------+---------+
3845 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3846 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3847 
---------------+---------+---------+---------+---------+
3848 
dco_clk        |   23.616|   11.532|         |    1.218|
3849 
---------------+---------+---------+---------+---------+
3850 
 
3851 
====================================================================================
3852 
Device utilization summary:
3853 
---------------------------
3854 
 
3855 
Selected Device : 4vlx25sf363-10
3856 
 
3857 
 Number of Slices:                     1401  out of  10752    13%
3858 
 Number of Slice Flip Flops:            744  out of  21504     3%
3859 
 Number of 4 input LUTs:               2653  out of  21504    12%
3860 
 Number of IOs:                          80
3861 
 Number of bonded IOBs:                  80  out of    240    33%
3862 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3863 
    Number used as RAMB16s:               5
3864 
 Number of GCLKs:                         1  out of     32     3%
3865 
 
3866 
---------------------------
3867 
 
3868 
====================================================================================
3869 
#                            SYNTHESIS DONE
3870 
#####################################################################################
3871 
 
3872 
#####################################################################################
3873 
#                            START SYNTHESIS (SPEED optimized)
3874 
#====================================================================================
3875 
# virtex4 (xc4vlx25sf363), speedgrade: -11
3876 
#====================================================================================
3877 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3878 
#     12          10          1         1            1          1            0
3879 
#====================================================================================
3880 
Clock to Setup on destination clock dco_clk
3881 
---------------+---------+---------+---------+---------+
3882 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3883 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3884 
---------------+---------+---------+---------+---------+
3885 
dco_clk        |   20.532|   10.117|         |    1.215|
3886 
---------------+---------+---------+---------+---------+
3887 
 
3888 
====================================================================================
3889 
Device utilization summary:
3890 
---------------------------
3891 
 
3892 
Selected Device : 4vlx25sf363-11
3893 
 
3894 
 Number of Slices:                     1383  out of  10752    12%
3895 
 Number of Slice Flip Flops:            746  out of  21504     3%
3896 
 Number of 4 input LUTs:               2615  out of  21504    12%
3897 
 Number of IOs:                          80
3898 
 Number of bonded IOBs:                  80  out of    240    33%
3899 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3900 
    Number used as RAMB16s:               5
3901 
 Number of GCLKs:                         1  out of     32     3%
3902 
 
3903 
---------------------------
3904 
 
3905 
====================================================================================
3906 
#                            SYNTHESIS DONE
3907 
#####################################################################################
3908 
 
3909 
#####################################################################################
3910 
#                            START SYNTHESIS (SPEED optimized)
3911 
#====================================================================================
3912 
# virtex4 (xc4vlx25sf363), speedgrade: -12
3913 
#====================================================================================
3914 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3915 
#     12          10          1         1            1          1            0
3916 
#====================================================================================
3917 
Clock to Setup on destination clock dco_clk
3918 
---------------+---------+---------+---------+---------+
3919 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3920 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3921 
---------------+---------+---------+---------+---------+
3922 
dco_clk        |   18.383|    8.899|         |    1.262|
3923 
---------------+---------+---------+---------+---------+
3924 
 
3925 
====================================================================================
3926 
Device utilization summary:
3927 
---------------------------
3928 
 
3929 
Selected Device : 4vlx25sf363-12
3930 
 
3931 
 Number of Slices:                     1384  out of  10752    12%
3932 
 Number of Slice Flip Flops:            748  out of  21504     3%
3933 
 Number of 4 input LUTs:               2618  out of  21504    12%
3934 
 Number of IOs:                          80
3935 
 Number of bonded IOBs:                  80  out of    240    33%
3936 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3937 
    Number used as RAMB16s:               5
3938 
 Number of GCLKs:                         1  out of     32     3%
3939 
 
3940 
---------------------------
3941 
 
3942 
====================================================================================
3943 
#                            SYNTHESIS DONE
3944 
#####################################################################################
3945 
 
3946 
#####################################################################################
3947 
#                            START SYNTHESIS (SPEED optimized)
3948 
#====================================================================================
3949 
# virtex5 (xc5vlx30ff324), speedgrade: -1
3950 
#====================================================================================
3951 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3952 
#     12          10          1         1            1          1            0
3953 
#====================================================================================
3954 
Clock to Setup on destination clock dco_clk
3955 
---------------+---------+---------+---------+---------+
3956 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3957 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3958 
---------------+---------+---------+---------+---------+
3959 
dco_clk        |   18.869|    8.889|         |    0.874|
3960 
---------------+---------+---------+---------+---------+
3961 
 
3962 
====================================================================================
3963 
Device utilization summary:
3964 
---------------------------
3965 
 
3966 
Selected Device : 5vlx30ff324-1
3967 
 
3968 
 
3969 
Slice Logic Utilization:
3970 
 Number of Slice Registers:             736  out of  19200     3%
3971 
 Number of Slice LUTs:                 2075  out of  19200    10%
3972 
    Number used as Logic:              2075  out of  19200    10%
3973 
 
3974 
Slice Logic Distribution:
3975 
 Number of LUT Flip Flop pairs used:   2470
3976 
   Number with an unused Flip Flop:    1734  out of   2470    70%
3977 
   Number with an unused LUT:           395  out of   2470    15%
3978 
   Number of fully used LUT-FF pairs:   341  out of   2470    13%
3979 
   Number of unique control sets:        63
3980 
 
3981 
IO Utilization:
3982 
 Number of IOs:                          80
3983 
 Number of bonded IOBs:                  80  out of    220    36%
3984 
 
3985 
Specific Feature Utilization:
3986 
 Number of Block RAM/FIFO:                3  out of     32     9%
3987 
    Number using Block RAM only:          3
3988 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3989 
 
3990 
---------------------------
3991 
 
3992 
====================================================================================
3993 
#                            SYNTHESIS DONE
3994 
#####################################################################################
3995 
 
3996 
#####################################################################################
3997 
#                            START SYNTHESIS (SPEED optimized)
3998 
#====================================================================================
3999 
# virtex5 (xc5vlx30ff324), speedgrade: -2
4000 
#====================================================================================
4001 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4002 
#     12          10          1         1            1          1            0
4003 
#====================================================================================
4004 
Clock to Setup on destination clock dco_clk
4005 
---------------+---------+---------+---------+---------+
4006 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4007 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4008 
---------------+---------+---------+---------+---------+
4009 
dco_clk        |   17.123|    8.222|         |    1.070|
4010 
---------------+---------+---------+---------+---------+
4011 
 
4012 
====================================================================================
4013 
Device utilization summary:
4014 
---------------------------
4015 
 
4016 
Selected Device : 5vlx30ff324-2
4017 
 
4018 
 
4019 
Slice Logic Utilization:
4020 
 Number of Slice Registers:             735  out of  19200     3%
4021 
 Number of Slice LUTs:                 2035  out of  19200    10%
4022 
    Number used as Logic:              2035  out of  19200    10%
4023 
 
4024 
Slice Logic Distribution:
4025 
 Number of LUT Flip Flop pairs used:   2337
4026 
   Number with an unused Flip Flop:    1602  out of   2337    68%
4027 
   Number with an unused LUT:           302  out of   2337    12%
4028 
   Number of fully used LUT-FF pairs:   433  out of   2337    18%
4029 
   Number of unique control sets:        63
4030 
 
4031 
IO Utilization:
4032 
 Number of IOs:                          80
4033 
 Number of bonded IOBs:                  80  out of    220    36%
4034 
 
4035 
Specific Feature Utilization:
4036 
 Number of Block RAM/FIFO:                3  out of     32     9%
4037 
    Number using Block RAM only:          3
4038 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4039 
 
4040 
---------------------------
4041 
 
4042 
====================================================================================
4043 
#                            SYNTHESIS DONE
4044 
#####################################################################################
4045 
 
4046 
#####################################################################################
4047 
#                            START SYNTHESIS (SPEED optimized)
4048 
#====================================================================================
4049 
# virtex5 (xc5vlx30ff324), speedgrade: -3
4050 
#====================================================================================
4051 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4052 
#     12          10          1         1            1          1            0
4053 
#====================================================================================
4054 
Clock to Setup on destination clock dco_clk
4055 
---------------+---------+---------+---------+---------+
4056 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4057 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4058 
---------------+---------+---------+---------+---------+
4059 
dco_clk        |   14.045|    6.978|         |    0.992|
4060 
---------------+---------+---------+---------+---------+
4061 
 
4062 
====================================================================================
4063 
Device utilization summary:
4064 
---------------------------
4065 
 
4066 
Selected Device : 5vlx30ff324-3
4067 
 
4068 
 
4069 
Slice Logic Utilization:
4070 
 Number of Slice Registers:             730  out of  19200     3%
4071 
 Number of Slice LUTs:                 2024  out of  19200    10%
4072 
    Number used as Logic:              2024  out of  19200    10%
4073 
 
4074 
Slice Logic Distribution:
4075 
 Number of LUT Flip Flop pairs used:   2376
4076 
   Number with an unused Flip Flop:    1646  out of   2376    69%
4077 
   Number with an unused LUT:           352  out of   2376    14%
4078 
   Number of fully used LUT-FF pairs:   378  out of   2376    15%
4079 
   Number of unique control sets:        63
4080 
 
4081 
IO Utilization:
4082 
 Number of IOs:                          80
4083 
 Number of bonded IOBs:                  80  out of    220    36%
4084 
 
4085 
Specific Feature Utilization:
4086 
 Number of Block RAM/FIFO:                3  out of     32     9%
4087 
    Number using Block RAM only:          3
4088 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4089 
 
4090 
---------------------------
4091 
 
4092 
====================================================================================
4093 
#                            SYNTHESIS DONE
4094 
#####################################################################################
4095 
 
4096 
#####################################################################################
4097 
#                            START SYNTHESIS (SPEED optimized)
4098 
#====================================================================================
4099 
# virtex6 (xc6vlx75tff484), speedgrade: -1
4100 
#====================================================================================
4101 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4102 
#     12          10          1         1            1          1            0
4103 
#====================================================================================
4104 
Clock to Setup on destination clock dco_clk
4105 
---------------+---------+---------+---------+---------+
4106 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4107 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4108 
---------------+---------+---------+---------+---------+
4109 
dco_clk        |   13.595|    6.668|    2.831|    1.136|
4110 
---------------+---------+---------+---------+---------+
4111 
 
4112 
====================================================================================
4113 
Device utilization summary:
4114 
---------------------------
4115 
 
4116 
Selected Device : 6vlx75tff484-1
4117 
 
4118 
 
4119 
Slice Logic Utilization:
4120 
 Number of Slice Registers:             734  out of  93120     0%
4121 
 Number of Slice LUTs:                 2030  out of  46560     4%
4122 
    Number used as Logic:              2030  out of  46560     4%
4123 
 
4124 
Slice Logic Distribution:
4125 
 Number of LUT Flip Flop pairs used:   2217
4126 
   Number with an unused Flip Flop:    1483  out of   2217    66%
4127 
   Number with an unused LUT:           187  out of   2217     8%
4128 
   Number of fully used LUT-FF pairs:   547  out of   2217    24%
4129 
   Number of unique control sets:        63
4130 
 
4131 
IO Utilization:
4132 
 Number of IOs:                          80
4133 
 Number of bonded IOBs:                  80  out of    240    33%
4134 
 
4135 
Specific Feature Utilization:
4136 
 Number of Block RAM/FIFO:                3  out of    156     1%
4137 
    Number using Block RAM only:          3
4138 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4139 
 
4140 
---------------------------
4141 
 
4142 
====================================================================================
4143 
#                            SYNTHESIS DONE
4144 
#####################################################################################
4145 
 
4146 
#####################################################################################
4147 
#                            START SYNTHESIS (SPEED optimized)
4148 
#====================================================================================
4149 
# virtex6 (xc6vlx75tff484), speedgrade: -2
4150 
#====================================================================================
4151 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4152 
#     12          10          1         1            1          1            0
4153 
#====================================================================================
4154 
Clock to Setup on destination clock dco_clk
4155 
---------------+---------+---------+---------+---------+
4156 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4157 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4158 
---------------+---------+---------+---------+---------+
4159 
dco_clk        |   12.954|    6.088|    2.275|    0.666|
4160 
---------------+---------+---------+---------+---------+
4161 
 
4162 
====================================================================================
4163 
Device utilization summary:
4164 
---------------------------
4165 
 
4166 
Selected Device : 6vlx75tff484-2
4167 
 
4168 
 
4169 
Slice Logic Utilization:
4170 
 Number of Slice Registers:             732  out of  93120     0%
4171 
 Number of Slice LUTs:                 2050  out of  46560     4%
4172 
    Number used as Logic:              2050  out of  46560     4%
4173 
 
4174 
Slice Logic Distribution:
4175 
 Number of LUT Flip Flop pairs used:   2228
4176 
   Number with an unused Flip Flop:    1496  out of   2228    67%
4177 
   Number with an unused LUT:           178  out of   2228     7%
4178 
   Number of fully used LUT-FF pairs:   554  out of   2228    24%
4179 
   Number of unique control sets:        63
4180 
 
4181 
IO Utilization:
4182 
 Number of IOs:                          80
4183 
 Number of bonded IOBs:                  80  out of    240    33%
4184 
 
4185 
Specific Feature Utilization:
4186 
 Number of Block RAM/FIFO:                3  out of    156     1%
4187 
    Number using Block RAM only:          3
4188 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4189 
 
4190 
---------------------------
4191 
 
4192 
====================================================================================
4193 
#                            SYNTHESIS DONE
4194 
#####################################################################################
4195 
 
4196 
#####################################################################################
4197 
#                            START SYNTHESIS (SPEED optimized)
4198 
#====================================================================================
4199 
# virtex6 (xc6vlx75tff484), speedgrade: -3
4200 
#====================================================================================
4201 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4202 
#     12          10          1         1            1          1            0
4203 
#====================================================================================
4204 
Clock to Setup on destination clock dco_clk
4205 
---------------+---------+---------+---------+---------+
4206 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4207 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4208 
---------------+---------+---------+---------+---------+
4209 
dco_clk        |   11.838|    5.749|    1.970|    0.610|
4210 
---------------+---------+---------+---------+---------+
4211 
 
4212 
====================================================================================
4213 
Device utilization summary:
4214 
---------------------------
4215 
 
4216 
Selected Device : 6vlx75tff484-3
4217 
 
4218 
 
4219 
Slice Logic Utilization:
4220 
 Number of Slice Registers:             730  out of  93120     0%
4221 
 Number of Slice LUTs:                 1989  out of  46560     4%
4222 
    Number used as Logic:              1989  out of  46560     4%
4223 
 
4224 
Slice Logic Distribution:
4225 
 Number of LUT Flip Flop pairs used:   2160
4226 
   Number with an unused Flip Flop:    1430  out of   2160    66%
4227 
   Number with an unused LUT:           171  out of   2160     7%
4228 
   Number of fully used LUT-FF pairs:   559  out of   2160    25%
4229 
   Number of unique control sets:        63
4230 
 
4231 
IO Utilization:
4232 
 Number of IOs:                          80
4233 
 Number of bonded IOBs:                  80  out of    240    33%
4234 
 
4235 
Specific Feature Utilization:
4236 
 Number of Block RAM/FIFO:                3  out of    156     1%
4237 
    Number using Block RAM only:          3
4238 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4239 
 
4240 
---------------------------
4241 
 
4242 
====================================================================================
4243 
#                            SYNTHESIS DONE
4244 
#####################################################################################
4245 
 
4246 
#####################################################################################
4247 
#                            START SYNTHESIS (SPEED optimized)
4248 
#====================================================================================
4249 
# spartan3 (xc3s400pq208), speedgrade: -4
4250 
#====================================================================================
4251 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4252 
#     12          10          1         1            1          1            1
4253 
#====================================================================================
4254 
Clock to Setup on destination clock dco_clk
4255 
---------------+---------+---------+---------+---------+
4256 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4257 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4258 
---------------+---------+---------+---------+---------+
4259 
dco_clk        |   42.561|   19.205|         |    1.728|
4260 
---------------+---------+---------+---------+---------+
4261 
 
4262 
====================================================================================
4263 
Device utilization summary:
4264 
---------------------------
4265 
 
4266 
Selected Device : 3s400pq208-4
4267 
 
4268 
 Number of Slices:                     1463  out of   3584    40%
4269 
 Number of Slice Flip Flops:            789  out of   7168    11%
4270 
 Number of 4 input LUTs:               2781  out of   7168    38%
4271 
 Number of IOs:                          80
4272 
 Number of bonded IOBs:                  80  out of    141    56%
4273 
 Number of BRAMs:                         6  out of     16    37%
4274 
 Number of GCLKs:                         1  out of      8    12%
4275 
 
4276 
---------------------------
4277 
 
4278 
====================================================================================
4279 
#                            SYNTHESIS DONE
4280 
#####################################################################################
4281 
 
4282 
#####################################################################################
4283 
#                            START SYNTHESIS (SPEED optimized)
4284 
#====================================================================================
4285 
# spartan3 (xc3s400pq208), speedgrade: -5
4286 
#====================================================================================
4287 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4288 
#     12          10          1         1            1          1            1
4289 
#====================================================================================
4290 
Clock to Setup on destination clock dco_clk
4291 
---------------+---------+---------+---------+---------+
4292 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4293 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4294 
---------------+---------+---------+---------+---------+
4295 
dco_clk        |   36.184|   16.807|         |    1.469|
4296 
---------------+---------+---------+---------+---------+
4297 
 
4298 
====================================================================================
4299 
Device utilization summary:
4300 
---------------------------
4301 
 
4302 
Selected Device : 3s400pq208-5
4303 
 
4304 
 Number of Slices:                     1462  out of   3584    40%
4305 
 Number of Slice Flip Flops:            789  out of   7168    11%
4306 
 Number of 4 input LUTs:               2780  out of   7168    38%
4307 
 Number of IOs:                          80
4308 
 Number of bonded IOBs:                  80  out of    141    56%
4309 
 Number of BRAMs:                         6  out of     16    37%
4310 
 Number of GCLKs:                         1  out of      8    12%
4311 
 
4312 
---------------------------
4313 
 
4314 
====================================================================================
4315 
#                            SYNTHESIS DONE
4316 
#####################################################################################
4317 
 
4318 
#####################################################################################
4319 
#                            START SYNTHESIS (SPEED optimized)
4320 
#====================================================================================
4321 
# spartan3e (xc3s500epq208), speedgrade: -4
4322 
#====================================================================================
4323 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4324 
#     12          10          1         1            1          1            1
4325 
#====================================================================================
4326 
Clock to Setup on destination clock dco_clk
4327 
---------------+---------+---------+---------+---------+
4328 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4329 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4330 
---------------+---------+---------+---------+---------+
4331 
dco_clk        |   40.325|   18.287|         |    1.769|
4332 
---------------+---------+---------+---------+---------+
4333 
 
4334 
====================================================================================
4335 
Device utilization summary:
4336 
---------------------------
4337 
 
4338 
Selected Device : 3s500epq208-4
4339 
 
4340 
 Number of Slices:                     1461  out of   4656    31%
4341 
 Number of Slice Flip Flops:            788  out of   9312     8%
4342 
 Number of 4 input LUTs:               2775  out of   9312    29%
4343 
 Number of IOs:                          80
4344 
 Number of bonded IOBs:                  80  out of    158    50%
4345 
 Number of BRAMs:                         6  out of     20    30%
4346 
 Number of GCLKs:                         1  out of     24     4%
4347 
 
4348 
---------------------------
4349 
 
4350 
====================================================================================
4351 
#                            SYNTHESIS DONE
4352 
#####################################################################################
4353 
 
4354 
#####################################################################################
4355 
#                            START SYNTHESIS (SPEED optimized)
4356 
#====================================================================================
4357 
# spartan3e (xc3s500epq208), speedgrade: -5
4358 
#====================================================================================
4359 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4360 
#     12          10          1         1            1          1            1
4361 
#====================================================================================
4362 
Clock to Setup on destination clock dco_clk
4363 
---------------+---------+---------+---------+---------+
4364 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4365 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4366 
---------------+---------+---------+---------+---------+
4367 
dco_clk        |   34.139|   15.738|         |    1.663|
4368 
---------------+---------+---------+---------+---------+
4369 
 
4370 
====================================================================================
4371 
Device utilization summary:
4372 
---------------------------
4373 
 
4374 
Selected Device : 3s500epq208-5
4375 
 
4376 
 Number of Slices:                     1456  out of   4656    31%
4377 
 Number of Slice Flip Flops:            788  out of   9312     8%
4378 
 Number of 4 input LUTs:               2763  out of   9312    29%
4379 
 Number of IOs:                          80
4380 
 Number of bonded IOBs:                  80  out of    158    50%
4381 
 Number of BRAMs:                         6  out of     20    30%
4382 
 Number of GCLKs:                         1  out of     24     4%
4383 
 
4384 
---------------------------
4385 
 
4386 
====================================================================================
4387 
#                            SYNTHESIS DONE
4388 
#####################################################################################
4389 
 
4390 
#####################################################################################
4391 
#                            START SYNTHESIS (SPEED optimized)
4392 
#====================================================================================
4393 
# spartan3a (xc3s700aft256), speedgrade: -4
4394 
#====================================================================================
4395 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4396 
#     12          10          1         1            1          1            1
4397 
#====================================================================================
4398 
Clock to Setup on destination clock dco_clk
4399 
---------------+---------+---------+---------+---------+
4400 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4401 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4402 
---------------+---------+---------+---------+---------+
4403 
dco_clk        |   40.868|   20.027|         |    1.646|
4404 
---------------+---------+---------+---------+---------+
4405 
 
4406 
====================================================================================
4407 
Device utilization summary:
4408 
---------------------------
4409 
 
4410 
Selected Device : 3s700aft256-4
4411 
 
4412 
 Number of Slices:                     1444  out of   5888    24%
4413 
 Number of Slice Flip Flops:            786  out of  11776     6%
4414 
 Number of 4 input LUTs:               2736  out of  11776    23%
4415 
 Number of IOs:                          80
4416 
 Number of bonded IOBs:                  80  out of    161    49%
4417 
 Number of BRAMs:                         5  out of     20    25%
4418 
 Number of GCLKs:                         1  out of     24     4%
4419 
 
4420 
---------------------------
4421 
 
4422 
====================================================================================
4423 
#                            SYNTHESIS DONE
4424 
#####################################################################################
4425 
 
4426 
#####################################################################################
4427 
#                            START SYNTHESIS (SPEED optimized)
4428 
#====================================================================================
4429 
# spartan3a (xc3s700aft256), speedgrade: -5
4430 
#====================================================================================
4431 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4432 
#     12          10          1         1            1          1            1
4433 
#====================================================================================
4434 
Clock to Setup on destination clock dco_clk
4435 
---------------+---------+---------+---------+---------+
4436 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4437 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4438 
---------------+---------+---------+---------+---------+
4439 
dco_clk        |   36.100|   17.592|         |    1.473|
4440 
---------------+---------+---------+---------+---------+
4441 
 
4442 
====================================================================================
4443 
Device utilization summary:
4444 
---------------------------
4445 
 
4446 
Selected Device : 3s700aft256-5
4447 
 
4448 
 Number of Slices:                     1446  out of   5888    24%
4449 
 Number of Slice Flip Flops:            790  out of  11776     6%
4450 
 Number of 4 input LUTs:               2739  out of  11776    23%
4451 
 Number of IOs:                          80
4452 
 Number of bonded IOBs:                  80  out of    161    49%
4453 
 Number of BRAMs:                         5  out of     20    25%
4454 
 Number of GCLKs:                         1  out of     24     4%
4455 
 
4456 
---------------------------
4457 
 
4458 
====================================================================================
4459 
#                            SYNTHESIS DONE
4460 
#####################################################################################
4461 
 
4462 
#####################################################################################
4463 
#                            START SYNTHESIS (SPEED optimized)
4464 
#====================================================================================
4465 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
4466 
#====================================================================================
4467 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4468 
#     12          10          1         1            1          1            1
4469 
#====================================================================================
4470 
Clock to Setup on destination clock dco_clk
4471 
---------------+---------+---------+---------+---------+
4472 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4473 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4474 
---------------+---------+---------+---------+---------+
4475 
dco_clk        |   40.711|   20.043|         |    1.600|
4476 
---------------+---------+---------+---------+---------+
4477 
 
4478 
====================================================================================
4479 
Device utilization summary:
4480 
---------------------------
4481 
 
4482 
Selected Device : 3sd1800acs484-4
4483 
 
4484 
 Number of Slices:                     1473  out of  16640     8%
4485 
 Number of Slice Flip Flops:            785  out of  33280     2%
4486 
 Number of 4 input LUTs:               2791  out of  33280     8%
4487 
 Number of IOs:                          80
4488 
 Number of bonded IOBs:                  80  out of    309    25%
4489 
 Number of BRAMs:                         5  out of     84     5%
4490 
 Number of GCLKs:                         1  out of     24     4%
4491 
 
4492 
---------------------------
4493 
 
4494 
====================================================================================
4495 
#                            SYNTHESIS DONE
4496 
#####################################################################################
4497 
 
4498 
#####################################################################################
4499 
#                            START SYNTHESIS (SPEED optimized)
4500 
#====================================================================================
4501 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
4502 
#====================================================================================
4503 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4504 
#     12          10          1         1            1          1            1
4505 
#====================================================================================
4506 
Clock to Setup on destination clock dco_clk
4507 
---------------+---------+---------+---------+---------+
4508 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4509 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4510 
---------------+---------+---------+---------+---------+
4511 
dco_clk        |   35.096|   17.864|         |    2.215|
4512 
---------------+---------+---------+---------+---------+
4513 
 
4514 
====================================================================================
4515 
Device utilization summary:
4516 
---------------------------
4517 
 
4518 
Selected Device : 3sd1800acs484-5
4519 
 
4520 
 Number of Slices:                     1485  out of  16640     8%
4521 
 Number of Slice Flip Flops:            787  out of  33280     2%
4522 
 Number of 4 input LUTs:               2810  out of  33280     8%
4523 
 Number of IOs:                          80
4524 
 Number of bonded IOBs:                  80  out of    309    25%
4525 
 Number of BRAMs:                         5  out of     84     5%
4526 
 Number of GCLKs:                         1  out of     24     4%
4527 
 
4528 
---------------------------
4529 
 
4530 
====================================================================================
4531 
#                            SYNTHESIS DONE
4532 
#####################################################################################
4533 
 
4534 
#####################################################################################
4535 
#                            START SYNTHESIS (SPEED optimized)
4536 
#====================================================================================
4537 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
4538 
#====================================================================================
4539 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4540 
#     12          10          1         1            1          1            1
4541 
#====================================================================================
4542 
Clock to Setup on destination clock dco_clk
4543 
---------------+---------+---------+---------+---------+
4544 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4545 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4546 
---------------+---------+---------+---------+---------+
4547 
dco_clk        |   29.530|   14.036|    7.081|    2.770|
4548 
---------------+---------+---------+---------+---------+
4549 
 
4550 
====================================================================================
4551 
Device utilization summary:
4552 
---------------------------
4553 
 
4554 
Selected Device : 6slx45tfgg484-2
4555 
 
4556 
 
4557 
Slice Logic Utilization:
4558 
 Number of Slice Registers:             777  out of  54576     1%
4559 
 Number of Slice LUTs:                 2187  out of  27288     8%
4560 
    Number used as Logic:              2187  out of  27288     8%
4561 
 
4562 
Slice Logic Distribution:
4563 
 Number of LUT Flip Flop pairs used:   2579
4564 
   Number with an unused Flip Flop:    1802  out of   2579    69%
4565 
   Number with an unused LUT:           392  out of   2579    15%
4566 
   Number of fully used LUT-FF pairs:   385  out of   2579    14%
4567 
   Number of unique control sets:        66
4568 
 
4569 
IO Utilization:
4570 
 Number of IOs:                          80
4571 
 Number of bonded IOBs:                  80  out of    296    27%
4572 
 
4573 
Specific Feature Utilization:
4574 
 Number of Block RAM/FIFO:                5  out of    348     1%
4575 
    Number using Block RAM only:          5
4576 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
4577 
 
4578 
---------------------------
4579 
 
4580 
====================================================================================
4581 
#                            SYNTHESIS DONE
4582 
#####################################################################################
4583 
 
4584 
#####################################################################################
4585 
#                            START SYNTHESIS (SPEED optimized)
4586 
#====================================================================================
4587 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
4588 
#====================================================================================
4589 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4590 
#     12          10          1         1            1          1            1
4591 
#====================================================================================
4592 
Clock to Setup on destination clock dco_clk
4593 
---------------+---------+---------+---------+---------+
4594 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4595 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4596 
---------------+---------+---------+---------+---------+
4597 
dco_clk        |   23.080|   10.700|    2.690|    2.071|
4598 
---------------+---------+---------+---------+---------+
4599 
 
4600 
====================================================================================
4601 
Device utilization summary:
4602 
---------------------------
4603 
 
4604 
Selected Device : 6slx45tfgg484-3
4605 
 
4606 
 
4607 
Slice Logic Utilization:
4608 
 Number of Slice Registers:             773  out of  54576     1%
4609 
 Number of Slice LUTs:                 2112  out of  27288     7%
4610 
    Number used as Logic:              2112  out of  27288     7%
4611 
 
4612 
Slice Logic Distribution:
4613 
 Number of LUT Flip Flop pairs used:   2548
4614 
   Number with an unused Flip Flop:    1775  out of   2548    69%
4615 
   Number with an unused LUT:           436  out of   2548    17%
4616 
   Number of fully used LUT-FF pairs:   337  out of   2548    13%
4617 
   Number of unique control sets:        67
4618 
 
4619 
IO Utilization:
4620 
 Number of IOs:                          80
4621 
 Number of bonded IOBs:                  80  out of    296    27%
4622 
 
4623 
Specific Feature Utilization:
4624 
 Number of Block RAM/FIFO:                5  out of    348     1%
4625 
    Number using Block RAM only:          5
4626 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
4627 
 
4628 
---------------------------
4629 
 
4630 
====================================================================================
4631 
#                            SYNTHESIS DONE
4632 
#####################################################################################
4633 
 
4634 
#####################################################################################
4635 
#                            START SYNTHESIS (SPEED optimized)
4636 
#====================================================================================
4637 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
4638 
#====================================================================================
4639 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4640 
#     12          10          1         1            1          1            1
4641 
#====================================================================================
4642 
Clock to Setup on destination clock dco_clk
4643 
---------------+---------+---------+---------+---------+
4644 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4645 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4646 
---------------+---------+---------+---------+---------+
4647 
dco_clk        |   22.929|    8.541|    3.393|    1.743|
4648 
---------------+---------+---------+---------+---------+
4649 
 
4650 
====================================================================================
4651 
Device utilization summary:
4652 
---------------------------
4653 
 
4654 
Selected Device : 6slx45tfgg484-4
4655 
 
4656 
 
4657 
Slice Logic Utilization:
4658 
 Number of Slice Registers:             774  out of  54576     1%
4659 
 Number of Slice LUTs:                 2123  out of  27288     7%
4660 
    Number used as Logic:              2123  out of  27288     7%
4661 
 
4662 
Slice Logic Distribution:
4663 
 Number of LUT Flip Flop pairs used:   2536
4664 
   Number with an unused Flip Flop:    1762  out of   2536    69%
4665 
   Number with an unused LUT:           413  out of   2536    16%
4666 
   Number of fully used LUT-FF pairs:   361  out of   2536    14%
4667 
   Number of unique control sets:        66
4668 
 
4669 
IO Utilization:
4670 
 Number of IOs:                          80
4671 
 Number of bonded IOBs:                  80  out of    296    27%
4672 
 
4673 
Specific Feature Utilization:
4674 
 Number of Block RAM/FIFO:                5  out of    348     1%
4675 
    Number using Block RAM only:          5
4676 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
4677 
 
4678 
---------------------------
4679 
 
4680 
====================================================================================
4681 
#                            SYNTHESIS DONE
4682 
#####################################################################################
4683 
 
4684 
#####################################################################################
4685 
#                            START SYNTHESIS (SPEED optimized)
4686 
#====================================================================================
4687 
# virtex4 (xc4vlx25sf363), speedgrade: -10
4688 
#====================================================================================
4689 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4690 
#     12          10          1         1            1          1            1
4691 
#====================================================================================
4692 
Clock to Setup on destination clock dco_clk
4693 
---------------+---------+---------+---------+---------+
4694 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4695 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4696 
---------------+---------+---------+---------+---------+
4697 
dco_clk        |   25.522|   11.495|         |    1.677|
4698 
---------------+---------+---------+---------+---------+
4699 
 
4700 
====================================================================================
4701 
Device utilization summary:
4702 
---------------------------
4703 
 
4704 
Selected Device : 4vlx25sf363-10
4705 
 
4706 
 Number of Slices:                     1462  out of  10752    13%
4707 
 Number of Slice Flip Flops:            794  out of  21504     3%
4708 
 Number of 4 input LUTs:               2779  out of  21504    12%
4709 
 Number of IOs:                          80
4710 
 Number of bonded IOBs:                  80  out of    240    33%
4711 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4712 
    Number used as RAMB16s:               5
4713 
 Number of GCLKs:                         1  out of     32     3%
4714 
 
4715 
---------------------------
4716 
 
4717 
====================================================================================
4718 
#                            SYNTHESIS DONE
4719 
#####################################################################################
4720 
 
4721 
#####################################################################################
4722 
#                            START SYNTHESIS (SPEED optimized)
4723 
#====================================================================================
4724 
# virtex4 (xc4vlx25sf363), speedgrade: -11
4725 
#====================================================================================
4726 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4727 
#     12          10          1         1            1          1            1
4728 
#====================================================================================
4729 
Clock to Setup on destination clock dco_clk
4730 
---------------+---------+---------+---------+---------+
4731 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4732 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4733 
---------------+---------+---------+---------+---------+
4734 
dco_clk        |   21.103|   10.381|         |    0.851|
4735 
---------------+---------+---------+---------+---------+
4736 
 
4737 
====================================================================================
4738 
Device utilization summary:
4739 
---------------------------
4740 
 
4741 
Selected Device : 4vlx25sf363-11
4742 
 
4743 
 Number of Slices:                     1464  out of  10752    13%
4744 
 Number of Slice Flip Flops:            792  out of  21504     3%
4745 
 Number of 4 input LUTs:               2781  out of  21504    12%
4746 
 Number of IOs:                          80
4747 
 Number of bonded IOBs:                  80  out of    240    33%
4748 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4749 
    Number used as RAMB16s:               5
4750 
 Number of GCLKs:                         1  out of     32     3%
4751 
 
4752 
---------------------------
4753 
 
4754 
====================================================================================
4755 
#                            SYNTHESIS DONE
4756 
#####################################################################################
4757 
 
4758 
#####################################################################################
4759 
#                            START SYNTHESIS (SPEED optimized)
4760 
#====================================================================================
4761 
# virtex4 (xc4vlx25sf363), speedgrade: -12
4762 
#====================================================================================
4763 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4764 
#     12          10          1         1            1          1            1
4765 
#====================================================================================
4766 
Clock to Setup on destination clock dco_clk
4767 
---------------+---------+---------+---------+---------+
4768 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4769 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4770 
---------------+---------+---------+---------+---------+
4771 
dco_clk        |   18.563|    8.688|         |    0.748|
4772 
---------------+---------+---------+---------+---------+
4773 
 
4774 
====================================================================================
4775 
Device utilization summary:
4776 
---------------------------
4777 
 
4778 
Selected Device : 4vlx25sf363-12
4779 
 
4780 
 Number of Slices:                     1461  out of  10752    13%
4781 
 Number of Slice Flip Flops:            793  out of  21504     3%
4782 
 Number of 4 input LUTs:               2775  out of  21504    12%
4783 
 Number of IOs:                          80
4784 
 Number of bonded IOBs:                  80  out of    240    33%
4785 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4786 
    Number used as RAMB16s:               5
4787 
 Number of GCLKs:                         1  out of     32     3%
4788 
 
4789 
---------------------------
4790 
 
4791 
====================================================================================
4792 
#                            SYNTHESIS DONE
4793 
#####################################################################################
4794 
 
4795 
#####################################################################################
4796 
#                            START SYNTHESIS (SPEED optimized)
4797 
#====================================================================================
4798 
# virtex5 (xc5vlx30ff324), speedgrade: -1
4799 
#====================================================================================
4800 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4801 
#     12          10          1         1            1          1            1
4802 
#====================================================================================
4803 
Clock to Setup on destination clock dco_clk
4804 
---------------+---------+---------+---------+---------+
4805 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4806 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4807 
---------------+---------+---------+---------+---------+
4808 
dco_clk        |   18.680|    8.472|         |    1.313|
4809 
---------------+---------+---------+---------+---------+
4810 
 
4811 
====================================================================================
4812 
Device utilization summary:
4813 
---------------------------
4814 
 
4815 
Selected Device : 5vlx30ff324-1
4816 
 
4817 
 
4818 
Slice Logic Utilization:
4819 
 Number of Slice Registers:             774  out of  19200     4%
4820 
 Number of Slice LUTs:                 2170  out of  19200    11%
4821 
    Number used as Logic:              2170  out of  19200    11%
4822 
 
4823 
Slice Logic Distribution:
4824 
 Number of LUT Flip Flop pairs used:   2589
4825 
   Number with an unused Flip Flop:    1815  out of   2589    70%
4826 
   Number with an unused LUT:           419  out of   2589    16%
4827 
   Number of fully used LUT-FF pairs:   355  out of   2589    13%
4828 
   Number of unique control sets:        66
4829 
 
4830 
IO Utilization:
4831 
 Number of IOs:                          80
4832 
 Number of bonded IOBs:                  80  out of    220    36%
4833 
 
4834 
Specific Feature Utilization:
4835 
 Number of Block RAM/FIFO:                3  out of     32     9%
4836 
    Number using Block RAM only:          3
4837 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4838 
 
4839 
---------------------------
4840 
 
4841 
====================================================================================
4842 
#                            SYNTHESIS DONE
4843 
#####################################################################################
4844 
 
4845 
#####################################################################################
4846 
#                            START SYNTHESIS (SPEED optimized)
4847 
#====================================================================================
4848 
# virtex5 (xc5vlx30ff324), speedgrade: -2
4849 
#====================================================================================
4850 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4851 
#     12          10          1         1            1          1            1
4852 
#====================================================================================
4853 
Clock to Setup on destination clock dco_clk
4854 
---------------+---------+---------+---------+---------+
4855 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4856 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4857 
---------------+---------+---------+---------+---------+
4858 
dco_clk        |   14.274|    6.394|         |    0.680|
4859 
---------------+---------+---------+---------+---------+
4860 
 
4861 
====================================================================================
4862 
Device utilization summary:
4863 
---------------------------
4864 
 
4865 
Selected Device : 5vlx30ff324-2
4866 
 
4867 
 
4868 
Slice Logic Utilization:
4869 
 Number of Slice Registers:             773  out of  19200     4%
4870 
 Number of Slice LUTs:                 2173  out of  19200    11%
4871 
    Number used as Logic:              2173  out of  19200    11%
4872 
 
4873 
Slice Logic Distribution:
4874 
 Number of LUT Flip Flop pairs used:   2509
4875 
   Number with an unused Flip Flop:    1736  out of   2509    69%
4876 
   Number with an unused LUT:           336  out of   2509    13%
4877 
   Number of fully used LUT-FF pairs:   437  out of   2509    17%
4878 
   Number of unique control sets:        66
4879 
 
4880 
IO Utilization:
4881 
 Number of IOs:                          80
4882 
 Number of bonded IOBs:                  80  out of    220    36%
4883 
 
4884 
Specific Feature Utilization:
4885 
 Number of Block RAM/FIFO:                3  out of     32     9%
4886 
    Number using Block RAM only:          3
4887 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4888 
 
4889 
---------------------------
4890 
 
4891 
====================================================================================
4892 
#                            SYNTHESIS DONE
4893 
#####################################################################################
4894 
 
4895 
#####################################################################################
4896 
#                            START SYNTHESIS (SPEED optimized)
4897 
#====================================================================================
4898 
# virtex5 (xc5vlx30ff324), speedgrade: -3
4899 
#====================================================================================
4900 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4901 
#     12          10          1         1            1          1            1
4902 
#====================================================================================
4903 
Clock to Setup on destination clock dco_clk
4904 
---------------+---------+---------+---------+---------+
4905 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4906 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4907 
---------------+---------+---------+---------+---------+
4908 
dco_clk        |   14.481|    6.419|         |    0.605|
4909 
---------------+---------+---------+---------+---------+
4910 
 
4911 
====================================================================================
4912 
Device utilization summary:
4913 
---------------------------
4914 
 
4915 
Selected Device : 5vlx30ff324-3
4916 
 
4917 
 
4918 
Slice Logic Utilization:
4919 
 Number of Slice Registers:             771  out of  19200     4%
4920 
 Number of Slice LUTs:                 2143  out of  19200    11%
4921 
    Number used as Logic:              2143  out of  19200    11%
4922 
 
4923 
Slice Logic Distribution:
4924 
 Number of LUT Flip Flop pairs used:   2571
4925 
   Number with an unused Flip Flop:    1800  out of   2571    70%
4926 
   Number with an unused LUT:           428  out of   2571    16%
4927 
   Number of fully used LUT-FF pairs:   343  out of   2571    13%
4928 
   Number of unique control sets:        66
4929 
 
4930 
IO Utilization:
4931 
 Number of IOs:                          80
4932 
 Number of bonded IOBs:                  80  out of    220    36%
4933 
 
4934 
Specific Feature Utilization:
4935 
 Number of Block RAM/FIFO:                3  out of     32     9%
4936 
    Number using Block RAM only:          3
4937 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4938 
 
4939 
---------------------------
4940 
 
4941 
====================================================================================
4942 
#                            SYNTHESIS DONE
4943 
#####################################################################################
4944 
 
4945 
#####################################################################################
4946 
#                            START SYNTHESIS (SPEED optimized)
4947 
#====================================================================================
4948 
# virtex6 (xc6vlx75tff484), speedgrade: -1
4949 
#====================================================================================
4950 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4951 
#     12          10          1         1            1          1            1
4952 
#====================================================================================
4953 
Clock to Setup on destination clock dco_clk
4954 
---------------+---------+---------+---------+---------+
4955 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4956 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4957 
---------------+---------+---------+---------+---------+
4958 
dco_clk        |   15.044|    6.354|    2.500|    1.022|
4959 
---------------+---------+---------+---------+---------+
4960 
 
4961 
====================================================================================
4962 
Device utilization summary:
4963 
---------------------------
4964 
 
4965 
Selected Device : 6vlx75tff484-1
4966 
 
4967 
 
4968 
Slice Logic Utilization:
4969 
 Number of Slice Registers:             776  out of  93120     0%
4970 
 Number of Slice LUTs:                 2043  out of  46560     4%
4971 
    Number used as Logic:              2043  out of  46560     4%
4972 
 
4973 
Slice Logic Distribution:
4974 
 Number of LUT Flip Flop pairs used:   2266
4975 
   Number with an unused Flip Flop:    1490  out of   2266    65%
4976 
   Number with an unused LUT:           223  out of   2266     9%
4977 
   Number of fully used LUT-FF pairs:   553  out of   2266    24%
4978 
   Number of unique control sets:        66
4979 
 
4980 
IO Utilization:
4981 
 Number of IOs:                          80
4982 
 Number of bonded IOBs:                  80  out of    240    33%
4983 
 
4984 
Specific Feature Utilization:
4985 
 Number of Block RAM/FIFO:                3  out of    156     1%
4986 
    Number using Block RAM only:          3
4987 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4988 
 
4989 
---------------------------
4990 
 
4991 
====================================================================================
4992 
#                            SYNTHESIS DONE
4993 
#####################################################################################
4994 
 
4995 
#####################################################################################
4996 
#                            START SYNTHESIS (SPEED optimized)
4997 
#====================================================================================
4998 
# virtex6 (xc6vlx75tff484), speedgrade: -2
4999 
#====================================================================================
5000 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
5001 
#     12          10          1         1            1          1            1
5002 
#====================================================================================
5003 
Clock to Setup on destination clock dco_clk
5004 
---------------+---------+---------+---------+---------+
5005 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
5006 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
5007 
---------------+---------+---------+---------+---------+
5008 
dco_clk        |   13.344|    6.146|    2.734|    0.906|
5009 
---------------+---------+---------+---------+---------+
5010 
 
5011 
====================================================================================
5012 
Device utilization summary:
5013 
---------------------------
5014 
 
5015 
Selected Device : 6vlx75tff484-2
5016 
 
5017 
 
5018 
Slice Logic Utilization:
5019 
 Number of Slice Registers:             774  out of  93120     0%
5020 
 Number of Slice LUTs:                 2071  out of  46560     4%
5021 
    Number used as Logic:              2071  out of  46560     4%
5022 
 
5023 
Slice Logic Distribution:
5024 
 Number of LUT Flip Flop pairs used:   2284
5025 
   Number with an unused Flip Flop:    1510  out of   2284    66%
5026 
   Number with an unused LUT:           213  out of   2284     9%
5027 
   Number of fully used LUT-FF pairs:   561  out of   2284    24%
5028 
   Number of unique control sets:        66
5029 
 
5030 
IO Utilization:
5031 
 Number of IOs:                          80
5032 
 Number of bonded IOBs:                  80  out of    240    33%
5033 
 
5034 
Specific Feature Utilization:
5035 
 Number of Block RAM/FIFO:                3  out of    156     1%
5036 
    Number using Block RAM only:          3
5037 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5038 
 
5039 
---------------------------
5040 
 
5041 
====================================================================================
5042 
#                            SYNTHESIS DONE
5043 
#####################################################################################
5044 
 
5045 
#####################################################################################
5046 
#                            START SYNTHESIS (SPEED optimized)
5047 
#====================================================================================
5048 
# virtex6 (xc6vlx75tff484), speedgrade: -3
5049 
#====================================================================================
5050 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
5051 
#     12          10          1         1            1          1            1
5052 
#====================================================================================
5053 
Clock to Setup on destination clock dco_clk
5054 
---------------+---------+---------+---------+---------+
5055 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
5056 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
5057 
---------------+---------+---------+---------+---------+
5058 
dco_clk        |   11.013|    5.057|    1.808|    0.463|
5059 
---------------+---------+---------+---------+---------+
5060 
 
5061 
====================================================================================
5062 
Device utilization summary:
5063 
---------------------------
5064 
 
5065 
Selected Device : 6vlx75tff484-3
5066 
 
5067 
 
5068 
Slice Logic Utilization:
5069 
 Number of Slice Registers:             771  out of  93120     0%
5070 
 Number of Slice LUTs:                 2031  out of  46560     4%
5071 
    Number used as Logic:              2031  out of  46560     4%
5072 
 
5073 
Slice Logic Distribution:
5074 
 Number of LUT Flip Flop pairs used:   2241
5075 
   Number with an unused Flip Flop:    1470  out of   2241    65%
5076 
   Number with an unused LUT:           210  out of   2241     9%
5077 
   Number of fully used LUT-FF pairs:   561  out of   2241    25%
5078 
   Number of unique control sets:        66
5079 
 
5080 
IO Utilization:
5081 
 Number of IOs:                          80
5082 
 Number of bonded IOBs:                  80  out of    240    33%
5083 
 
5084 
Specific Feature Utilization:
5085 
 Number of Block RAM/FIFO:                3  out of    156     1%
5086 
    Number using Block RAM only:          3
5087 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5088 
 
5089 
---------------------------
5090 
 
5091 
====================================================================================
5092 
#                            SYNTHESIS DONE
5093 
#####################################################################################
5094 
 

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