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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.speed.mpy.log] - Blame information for rev 181

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Line No. Rev Author Line
1 68 olivier.gi 
#####################################################################################
2 
#                            START SYNTHESIS (SPEED optimized)
3 
#====================================================================================
4 
# spartan3 (xc3s400pq208), speedgrade: -4
5 
#====================================================================================
6 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
7 
#     12          10          0         0            0          0            0         1
8 
#====================================================================================
9 
Clock to Setup on destination clock dco_clk
10 
---------------+---------+---------+---------+---------+
11 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
12 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
13 
---------------+---------+---------+---------+---------+
14 
dco_clk        |   33.283|         |         |    1.675|
15 
---------------+---------+---------+---------+---------+
16 
 
17 
====================================================================================
18 
Device utilization summary:
19 
---------------------------
20 
 
21 
Selected Device : 3s400pq208-4
22 
 
23 
 Number of Slices:                     1030  out of   3584    28%
24 
 Number of Slice Flip Flops:            548  out of   7168     7%
25 
 Number of 4 input LUTs:               1967  out of   7168    27%
26 
 Number of IOs:                          80
27 
 Number of bonded IOBs:                  79  out of    141    56%
28 
 Number of BRAMs:                         6  out of     16    37%
29 
 Number of MULT18X18s:                    1  out of     16     6%
30 
 Number of GCLKs:                         1  out of      8    12%
31 
 
32 
---------------------------
33 
 
34 
====================================================================================
35 
#                            SYNTHESIS DONE
36 
#####################################################################################
37 
 
38 
#####################################################################################
39 
#                            START SYNTHESIS (SPEED optimized)
40 
#====================================================================================
41 
# spartan3 (xc3s400pq208), speedgrade: -5
42 
#====================================================================================
43 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
44 
#     12          10          0         0            0          0            0         1
45 
#====================================================================================
46 
Clock to Setup on destination clock dco_clk
47 
---------------+---------+---------+---------+---------+
48 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
49 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
50 
---------------+---------+---------+---------+---------+
51 
dco_clk        |   29.319|         |         |    1.687|
52 
---------------+---------+---------+---------+---------+
53 
 
54 
====================================================================================
55 
Device utilization summary:
56 
---------------------------
57 
 
58 
Selected Device : 3s400pq208-5
59 
 
60 
 Number of Slices:                     1028  out of   3584    28%
61 
 Number of Slice Flip Flops:            546  out of   7168     7%
62 
 Number of 4 input LUTs:               1965  out of   7168    27%
63 
 Number of IOs:                          80
64 
 Number of bonded IOBs:                  79  out of    141    56%
65 
 Number of BRAMs:                         6  out of     16    37%
66 
 Number of MULT18X18s:                    1  out of     16     6%
67 
 Number of GCLKs:                         1  out of      8    12%
68 
 
69 
---------------------------
70 
 
71 
====================================================================================
72 
#                            SYNTHESIS DONE
73 
#####################################################################################
74 
 
75 
#####################################################################################
76 
#                            START SYNTHESIS (SPEED optimized)
77 
#====================================================================================
78 
# spartan3e (xc3s500epq208), speedgrade: -4
79 
#====================================================================================
80 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
81 
#     12          10          0         0            0          0            0         1
82 
#====================================================================================
83 
Clock to Setup on destination clock dco_clk
84 
---------------+---------+---------+---------+---------+
85 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
86 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
87 
---------------+---------+---------+---------+---------+
88 
dco_clk        |   31.162|         |         |    1.457|
89 
---------------+---------+---------+---------+---------+
90 
 
91 
====================================================================================
92 
Device utilization summary:
93 
---------------------------
94 
 
95 
Selected Device : 3s500epq208-4
96 
 
97 
 Number of Slices:                     1054  out of   4656    22%
98 
 Number of Slice Flip Flops:            548  out of   9312     5%
99 
 Number of 4 input LUTs:               2007  out of   9312    21%
100 
 Number of IOs:                          80
101 
 Number of bonded IOBs:                  79  out of    158    50%
102 
 Number of BRAMs:                         6  out of     20    30%
103 
 Number of MULT18X18SIOs:                 1  out of     20     5%
104 
 Number of GCLKs:                         1  out of     24     4%
105 
 
106 
---------------------------
107 
 
108 
====================================================================================
109 
#                            SYNTHESIS DONE
110 
#####################################################################################
111 
 
112 
#####################################################################################
113 
#                            START SYNTHESIS (SPEED optimized)
114 
#====================================================================================
115 
# spartan3e (xc3s500epq208), speedgrade: -5
116 
#====================================================================================
117 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
118 
#     12          10          0         0            0          0            0         1
119 
#====================================================================================
120 
Clock to Setup on destination clock dco_clk
121 
---------------+---------+---------+---------+---------+
122 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
123 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
124 
---------------+---------+---------+---------+---------+
125 
dco_clk        |   26.516|         |         |    1.819|
126 
---------------+---------+---------+---------+---------+
127 
 
128 
====================================================================================
129 
Device utilization summary:
130 
---------------------------
131 
 
132 
Selected Device : 3s500epq208-5
133 
 
134 
 Number of Slices:                     1054  out of   4656    22%
135 
 Number of Slice Flip Flops:            548  out of   9312     5%
136 
 Number of 4 input LUTs:               2008  out of   9312    21%
137 
 Number of IOs:                          80
138 
 Number of bonded IOBs:                  79  out of    158    50%
139 
 Number of BRAMs:                         6  out of     20    30%
140 
 Number of MULT18X18SIOs:                 1  out of     20     5%
141 
 Number of GCLKs:                         1  out of     24     4%
142 
 
143 
---------------------------
144 
 
145 
====================================================================================
146 
#                            SYNTHESIS DONE
147 
#####################################################################################
148 
 
149 
#####################################################################################
150 
#                            START SYNTHESIS (SPEED optimized)
151 
#====================================================================================
152 
# spartan3a (xc3s700aft256), speedgrade: -4
153 
#====================================================================================
154 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
155 
#     12          10          0         0            0          0            0         1
156 
#====================================================================================
157 
Clock to Setup on destination clock dco_clk
158 
---------------+---------+---------+---------+---------+
159 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
160 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
161 
---------------+---------+---------+---------+---------+
162 
dco_clk        |   32.202|         |         |    2.032|
163 
---------------+---------+---------+---------+---------+
164 
 
165 
====================================================================================
166 
Device utilization summary:
167 
---------------------------
168 
 
169 
Selected Device : 3s700aft256-4
170 
 
171 
 Number of Slices:                     1035  out of   5888    17%
172 
 Number of Slice Flip Flops:            551  out of  11776     4%
173 
 Number of 4 input LUTs:               1972  out of  11776    16%
174 
 Number of IOs:                          80
175 
 Number of bonded IOBs:                  79  out of    161    49%
176 
 Number of BRAMs:                         5  out of     20    25%
177 
 Number of MULT18X18SIOs:                 1  out of     20     5%
178 
 Number of GCLKs:                         1  out of     24     4%
179 
 
180 
---------------------------
181 
 
182 
====================================================================================
183 
#                            SYNTHESIS DONE
184 
#####################################################################################
185 
 
186 
#####################################################################################
187 
#                            START SYNTHESIS (SPEED optimized)
188 
#====================================================================================
189 
# spartan3a (xc3s700aft256), speedgrade: -5
190 
#====================================================================================
191 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
192 
#     12          10          0         0            0          0            0         1
193 
#====================================================================================
194 
Clock to Setup on destination clock dco_clk
195 
---------------+---------+---------+---------+---------+
196 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
197 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
198 
---------------+---------+---------+---------+---------+
199 
dco_clk        |   27.667|         |         |    1.760|
200 
---------------+---------+---------+---------+---------+
201 
 
202 
====================================================================================
203 
Device utilization summary:
204 
---------------------------
205 
 
206 
Selected Device : 3s700aft256-5
207 
 
208 
 Number of Slices:                     1031  out of   5888    17%
209 
 Number of Slice Flip Flops:            543  out of  11776     4%
210 
 Number of 4 input LUTs:               1965  out of  11776    16%
211 
 Number of IOs:                          80
212 
 Number of bonded IOBs:                  79  out of    161    49%
213 
 Number of BRAMs:                         5  out of     20    25%
214 
 Number of MULT18X18SIOs:                 1  out of     20     5%
215 
 Number of GCLKs:                         1  out of     24     4%
216 
 
217 
---------------------------
218 
 
219 
====================================================================================
220 
#                            SYNTHESIS DONE
221 
#####################################################################################
222 
 
223 
#####################################################################################
224 
#                            START SYNTHESIS (SPEED optimized)
225 
#====================================================================================
226 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
227 
#====================================================================================
228 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
229 
#     12          10          0         0            0          0            0         1
230 
#====================================================================================
231 
Clock to Setup on destination clock dco_clk
232 
---------------+---------+---------+---------+---------+
233 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
234 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
235 
---------------+---------+---------+---------+---------+
236 
dco_clk        |   31.993|         |         |    2.000|
237 
---------------+---------+---------+---------+---------+
238 
 
239 
====================================================================================
240 
Device utilization summary:
241 
---------------------------
242 
 
243 
Selected Device : 3sd1800acs484-4
244 
 
245 
 Number of Slices:                     1049  out of  16640     6%
246 
 Number of Slice Flip Flops:            549  out of  33280     1%
247 
 Number of 4 input LUTs:               1988  out of  33280     5%
248 
 Number of IOs:                          80
249 
 Number of bonded IOBs:                  79  out of    309    25%
250 
 Number of BRAMs:                         5  out of     84     5%
251 
 Number of GCLKs:                         1  out of     24     4%
252 
 Number of DSP48s:                        1  out of     84     1%
253 
 
254 
---------------------------
255 
 
256 
====================================================================================
257 
#                            SYNTHESIS DONE
258 
#####################################################################################
259 
 
260 
#####################################################################################
261 
#                            START SYNTHESIS (SPEED optimized)
262 
#====================================================================================
263 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
264 
#====================================================================================
265 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
266 
#     12          10          0         0            0          0            0         1
267 
#====================================================================================
268 
Clock to Setup on destination clock dco_clk
269 
---------------+---------+---------+---------+---------+
270 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
271 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
272 
---------------+---------+---------+---------+---------+
273 
dco_clk        |   26.605|         |         |    1.346|
274 
---------------+---------+---------+---------+---------+
275 
 
276 
====================================================================================
277 
Device utilization summary:
278 
---------------------------
279 
 
280 
Selected Device : 3sd1800acs484-5
281 
 
282 
 Number of Slices:                     1034  out of  16640     6%
283 
 Number of Slice Flip Flops:            550  out of  33280     1%
284 
 Number of 4 input LUTs:               1967  out of  33280     5%
285 
 Number of IOs:                          80
286 
 Number of bonded IOBs:                  79  out of    309    25%
287 
 Number of BRAMs:                         5  out of     84     5%
288 
 Number of GCLKs:                         1  out of     24     4%
289 
 Number of DSP48s:                        1  out of     84     1%
290 
 
291 
---------------------------
292 
 
293 
====================================================================================
294 
#                            SYNTHESIS DONE
295 
#####################################################################################
296 
 
297 
#####################################################################################
298 
#                            START SYNTHESIS (SPEED optimized)
299 
#====================================================================================
300 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
301 
#====================================================================================
302 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
303 
#     12          10          0         0            0          0            0         1
304 
#====================================================================================
305 
Clock to Setup on destination clock dco_clk
306 
---------------+---------+---------+---------+---------+
307 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
308 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
309 
---------------+---------+---------+---------+---------+
310 
dco_clk        |   24.371|    6.986|    3.176|    2.681|
311 
---------------+---------+---------+---------+---------+
312 
 
313 
====================================================================================
314 
Device utilization summary:
315 
---------------------------
316 
 
317 
Selected Device : 6slx45tfgg484-2
318 
 
319 
 
320 
Slice Logic Utilization:
321 
 Number of Slice Registers:             537  out of  54576     0%
322 
 Number of Slice LUTs:                 1714  out of  27288     6%
323 
    Number used as Logic:              1714  out of  27288     6%
324 
 
325 
Slice Logic Distribution:
326 
 Number of LUT Flip Flop pairs used:   1827
327 
   Number with an unused Flip Flop:    1290  out of   1827    70%
328 
   Number with an unused LUT:           113  out of   1827     6%
329 
   Number of fully used LUT-FF pairs:   424  out of   1827    23%
330 
   Number of unique control sets:        46
331 
 
332 
IO Utilization:
333 
 Number of IOs:                          80
334 
 Number of bonded IOBs:                  79  out of    296    26%
335 
 
336 
Specific Feature Utilization:
337 
 Number of Block RAM/FIFO:                5  out of    348     1%
338 
    Number using Block RAM only:          5
339 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
340 
 Number of DSP48A1s:                      1  out of     58     1%
341 
 
342 
---------------------------
343 
 
344 
====================================================================================
345 
#                            SYNTHESIS DONE
346 
#####################################################################################
347 
 
348 
#####################################################################################
349 
#                            START SYNTHESIS (SPEED optimized)
350 
#====================================================================================
351 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
352 
#====================================================================================
353 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
354 
#     12          10          0         0            0          0            0         1
355 
#====================================================================================
356 
Clock to Setup on destination clock dco_clk
357 
---------------+---------+---------+---------+---------+
358 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
359 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
360 
---------------+---------+---------+---------+---------+
361 
dco_clk        |   17.180|    5.946|    2.019|    1.844|
362 
---------------+---------+---------+---------+---------+
363 
 
364 
====================================================================================
365 
Device utilization summary:
366 
---------------------------
367 
 
368 
Selected Device : 6slx45tfgg484-3
369 
 
370 
 
371 
Slice Logic Utilization:
372 
 Number of Slice Registers:             535  out of  54576     0%
373 
 Number of Slice LUTs:                 1740  out of  27288     6%
374 
    Number used as Logic:              1740  out of  27288     6%
375 
 
376 
Slice Logic Distribution:
377 
 Number of LUT Flip Flop pairs used:   1836
378 
   Number with an unused Flip Flop:    1301  out of   1836    70%
379 
   Number with an unused LUT:            96  out of   1836     5%
380 
   Number of fully used LUT-FF pairs:   439  out of   1836    23%
381 
   Number of unique control sets:        48
382 
 
383 
IO Utilization:
384 
 Number of IOs:                          80
385 
 Number of bonded IOBs:                  79  out of    296    26%
386 
 
387 
Specific Feature Utilization:
388 
 Number of Block RAM/FIFO:                5  out of    348     1%
389 
    Number using Block RAM only:          5
390 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
391 
 Number of DSP48A1s:                      1  out of     58     1%
392 
 
393 
---------------------------
394 
 
395 
====================================================================================
396 
#                            SYNTHESIS DONE
397 
#####################################################################################
398 
 
399 
#####################################################################################
400 
#                            START SYNTHESIS (SPEED optimized)
401 
#====================================================================================
402 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
403 
#====================================================================================
404 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
405 
#     12          10          0         0            0          0            0         1
406 
#====================================================================================
407 
Clock to Setup on destination clock dco_clk
408 
---------------+---------+---------+---------+---------+
409 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
410 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
411 
---------------+---------+---------+---------+---------+
412 
dco_clk        |   14.789|    4.575|    2.236|    1.813|
413 
---------------+---------+---------+---------+---------+
414 
 
415 
====================================================================================
416 
Device utilization summary:
417 
---------------------------
418 
 
419 
Selected Device : 6slx45tfgg484-4
420 
 
421 
 
422 
Slice Logic Utilization:
423 
 Number of Slice Registers:             535  out of  54576     0%
424 
 Number of Slice LUTs:                 1815  out of  27288     6%
425 
    Number used as Logic:              1815  out of  27288     6%
426 
 
427 
Slice Logic Distribution:
428 
 Number of LUT Flip Flop pairs used:   1933
429 
   Number with an unused Flip Flop:    1398  out of   1933    72%
430 
   Number with an unused LUT:           118  out of   1933     6%
431 
   Number of fully used LUT-FF pairs:   417  out of   1933    21%
432 
   Number of unique control sets:        47
433 
 
434 
IO Utilization:
435 
 Number of IOs:                          80
436 
 Number of bonded IOBs:                  79  out of    296    26%
437 
 
438 
Specific Feature Utilization:
439 
 Number of Block RAM/FIFO:                5  out of    348     1%
440 
    Number using Block RAM only:          5
441 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
442 
 Number of DSP48A1s:                      1  out of     58     1%
443 
 
444 
---------------------------
445 
 
446 
====================================================================================
447 
#                            SYNTHESIS DONE
448 
#####################################################################################
449 
 
450 
#####################################################################################
451 
#                            START SYNTHESIS (SPEED optimized)
452 
#====================================================================================
453 
# virtex4 (xc4vlx25sf363), speedgrade: -10
454 
#====================================================================================
455 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
456 
#     12          10          0         0            0          0            0         1
457 
#====================================================================================
458 
Clock to Setup on destination clock dco_clk
459 
---------------+---------+---------+---------+---------+
460 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
461 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
462 
---------------+---------+---------+---------+---------+
463 
dco_clk        |   19.543|         |         |    0.967|
464 
---------------+---------+---------+---------+---------+
465 
 
466 
====================================================================================
467 
Device utilization summary:
468 
---------------------------
469 
 
470 
Selected Device : 4vlx25sf363-10
471 
 
472 
 Number of Slices:                     1040  out of  10752     9%
473 
 Number of Slice Flip Flops:            547  out of  21504     2%
474 
 Number of 4 input LUTs:               1975  out of  21504     9%
475 
 Number of IOs:                          80
476 
 Number of bonded IOBs:                  79  out of    240    32%
477 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
478 
    Number used as RAMB16s:               5
479 
 Number of GCLKs:                         1  out of     32     3%
480 
 Number of DSP48s:                        1  out of     48     2%
481 
 
482 
---------------------------
483 
 
484 
====================================================================================
485 
#                            SYNTHESIS DONE
486 
#####################################################################################
487 
 
488 
#####################################################################################
489 
#                            START SYNTHESIS (SPEED optimized)
490 
#====================================================================================
491 
# virtex4 (xc4vlx25sf363), speedgrade: -11
492 
#====================================================================================
493 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
494 
#     12          10          0         0            0          0            0         1
495 
#====================================================================================
496 
Clock to Setup on destination clock dco_clk
497 
---------------+---------+---------+---------+---------+
498 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
499 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
500 
---------------+---------+---------+---------+---------+
501 
dco_clk        |   17.812|         |         |    1.014|
502 
---------------+---------+---------+---------+---------+
503 
 
504 
====================================================================================
505 
Device utilization summary:
506 
---------------------------
507 
 
508 
Selected Device : 4vlx25sf363-11
509 
 
510 
 Number of Slices:                     1039  out of  10752     9%
511 
 Number of Slice Flip Flops:            549  out of  21504     2%
512 
 Number of 4 input LUTs:               1973  out of  21504     9%
513 
 Number of IOs:                          80
514 
 Number of bonded IOBs:                  79  out of    240    32%
515 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
516 
    Number used as RAMB16s:               5
517 
 Number of GCLKs:                         1  out of     32     3%
518 
 Number of DSP48s:                        1  out of     48     2%
519 
 
520 
---------------------------
521 
 
522 
====================================================================================
523 
#                            SYNTHESIS DONE
524 
#####################################################################################
525 
 
526 
#####################################################################################
527 
#                            START SYNTHESIS (SPEED optimized)
528 
#====================================================================================
529 
# virtex4 (xc4vlx25sf363), speedgrade: -12
530 
#====================================================================================
531 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
532 
#     12          10          0         0            0          0            0         1
533 
#====================================================================================
534 
Clock to Setup on destination clock dco_clk
535 
---------------+---------+---------+---------+---------+
536 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
537 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
538 
---------------+---------+---------+---------+---------+
539 
dco_clk        |   15.481|         |         |    0.914|
540 
---------------+---------+---------+---------+---------+
541 
 
542 
====================================================================================
543 
Device utilization summary:
544 
---------------------------
545 
 
546 
Selected Device : 4vlx25sf363-12
547 
 
548 
 Number of Slices:                     1040  out of  10752     9%
549 
 Number of Slice Flip Flops:            549  out of  21504     2%
550 
 Number of 4 input LUTs:               1974  out of  21504     9%
551 
 Number of IOs:                          80
552 
 Number of bonded IOBs:                  79  out of    240    32%
553 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
554 
    Number used as RAMB16s:               5
555 
 Number of GCLKs:                         1  out of     32     3%
556 
 Number of DSP48s:                        1  out of     48     2%
557 
 
558 
---------------------------
559 
 
560 
====================================================================================
561 
#                            SYNTHESIS DONE
562 
#####################################################################################
563 
 
564 
#####################################################################################
565 
#                            START SYNTHESIS (SPEED optimized)
566 
#====================================================================================
567 
# virtex5 (xc5vlx30ff324), speedgrade: -1
568 
#====================================================================================
569 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
570 
#     12          10          0         0            0          0            0         1
571 
#====================================================================================
572 
Clock to Setup on destination clock dco_clk
573 
---------------+---------+---------+---------+---------+
574 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
575 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
576 
---------------+---------+---------+---------+---------+
577 
dco_clk        |   13.389|         |         |    1.305|
578 
---------------+---------+---------+---------+---------+
579 
 
580 
====================================================================================
581 
Device utilization summary:
582 
---------------------------
583 
 
584 
Selected Device : 5vlx30ff324-1
585 
 
586 
 
587 
Slice Logic Utilization:
588 
 Number of Slice Registers:             538  out of  19200     2%
589 
 Number of Slice LUTs:                 1607  out of  19200     8%
590 
    Number used as Logic:              1607  out of  19200     8%
591 
 
592 
Slice Logic Distribution:
593 
 Number of LUT Flip Flop pairs used:   1730
594 
   Number with an unused Flip Flop:    1192  out of   1730    68%
595 
   Number with an unused LUT:           123  out of   1730     7%
596 
   Number of fully used LUT-FF pairs:   415  out of   1730    23%
597 
   Number of unique control sets:        47
598 
 
599 
IO Utilization:
600 
 Number of IOs:                          80
601 
 Number of bonded IOBs:                  79  out of    220    35%
602 
 
603 
Specific Feature Utilization:
604 
 Number of Block RAM/FIFO:                3  out of     32     9%
605 
    Number using Block RAM only:          3
606 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
607 
 Number of DSP48Es:                       1  out of     32     3%
608 
 
609 
---------------------------
610 
 
611 
====================================================================================
612 
#                            SYNTHESIS DONE
613 
#####################################################################################
614 
 
615 
#####################################################################################
616 
#                            START SYNTHESIS (SPEED optimized)
617 
#====================================================================================
618 
# virtex5 (xc5vlx30ff324), speedgrade: -2
619 
#====================================================================================
620 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
621 
#     12          10          0         0            0          0            0         1
622 
#====================================================================================
623 
Clock to Setup on destination clock dco_clk
624 
---------------+---------+---------+---------+---------+
625 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
626 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
627 
---------------+---------+---------+---------+---------+
628 
dco_clk        |   12.178|         |         |    0.677|
629 
---------------+---------+---------+---------+---------+
630 
 
631 
====================================================================================
632 
Device utilization summary:
633 
---------------------------
634 
 
635 
Selected Device : 5vlx30ff324-2
636 
 
637 
 
638 
Slice Logic Utilization:
639 
 Number of Slice Registers:             537  out of  19200     2%
640 
 Number of Slice LUTs:                 1606  out of  19200     8%
641 
    Number used as Logic:              1606  out of  19200     8%
642 
 
643 
Slice Logic Distribution:
644 
 Number of LUT Flip Flop pairs used:   1709
645 
   Number with an unused Flip Flop:    1172  out of   1709    68%
646 
   Number with an unused LUT:           103  out of   1709     6%
647 
   Number of fully used LUT-FF pairs:   434  out of   1709    25%
648 
   Number of unique control sets:        47
649 
 
650 
IO Utilization:
651 
 Number of IOs:                          80
652 
 Number of bonded IOBs:                  79  out of    220    35%
653 
 
654 
Specific Feature Utilization:
655 
 Number of Block RAM/FIFO:                3  out of     32     9%
656 
    Number using Block RAM only:          3
657 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
658 
 Number of DSP48Es:                       1  out of     32     3%
659 
 
660 
---------------------------
661 
 
662 
====================================================================================
663 
#                            SYNTHESIS DONE
664 
#####################################################################################
665 
 
666 
#####################################################################################
667 
#                            START SYNTHESIS (SPEED optimized)
668 
#====================================================================================
669 
# virtex5 (xc5vlx30ff324), speedgrade: -3
670 
#====================================================================================
671 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
672 
#     12          10          0         0            0          0            0         1
673 
#====================================================================================
674 
Clock to Setup on destination clock dco_clk
675 
---------------+---------+---------+---------+---------+
676 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
677 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
678 
---------------+---------+---------+---------+---------+
679 
dco_clk        |   10.283|         |         |    0.589|
680 
---------------+---------+---------+---------+---------+
681 
 
682 
====================================================================================
683 
Device utilization summary:
684 
---------------------------
685 
 
686 
Selected Device : 5vlx30ff324-3
687 
 
688 
 
689 
Slice Logic Utilization:
690 
 Number of Slice Registers:             534  out of  19200     2%
691 
 Number of Slice LUTs:                 1590  out of  19200     8%
692 
    Number used as Logic:              1590  out of  19200     8%
693 
 
694 
Slice Logic Distribution:
695 
 Number of LUT Flip Flop pairs used:   1680
696 
   Number with an unused Flip Flop:    1146  out of   1680    68%
697 
   Number with an unused LUT:            90  out of   1680     5%
698 
   Number of fully used LUT-FF pairs:   444  out of   1680    26%
699 
   Number of unique control sets:        47
700 
 
701 
IO Utilization:
702 
 Number of IOs:                          80
703 
 Number of bonded IOBs:                  79  out of    220    35%
704 
 
705 
Specific Feature Utilization:
706 
 Number of Block RAM/FIFO:                3  out of     32     9%
707 
    Number using Block RAM only:          3
708 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
709 
 Number of DSP48Es:                       1  out of     32     3%
710 
 
711 
---------------------------
712 
 
713 
====================================================================================
714 
#                            SYNTHESIS DONE
715 
#####################################################################################
716 
 
717 
#####################################################################################
718 
#                            START SYNTHESIS (SPEED optimized)
719 
#====================================================================================
720 
# virtex6 (xc6vlx75tff484), speedgrade: -1
721 
#====================================================================================
722 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
723 
#     12          10          0         0            0          0            0         1
724 
#====================================================================================
725 
Clock to Setup on destination clock dco_clk
726 
---------------+---------+---------+---------+---------+
727 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
728 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
729 
---------------+---------+---------+---------+---------+
730 
dco_clk        |   10.800|    3.353|    3.579|    0.591|
731 
---------------+---------+---------+---------+---------+
732 
 
733 
====================================================================================
734 
Device utilization summary:
735 
---------------------------
736 
 
737 
Selected Device : 6vlx75tff484-1
738 
 
739 
 
740 
Slice Logic Utilization:
741 
 Number of Slice Registers:             538  out of  93120     0%
742 
 Number of Slice LUTs:                 1691  out of  46560     3%
743 
    Number used as Logic:              1691  out of  46560     3%
744 
 
745 
Slice Logic Distribution:
746 
 Number of LUT Flip Flop pairs used:   1760
747 
   Number with an unused Flip Flop:    1222  out of   1760    69%
748 
   Number with an unused LUT:            69  out of   1760     3%
749 
   Number of fully used LUT-FF pairs:   469  out of   1760    26%
750 
   Number of unique control sets:        47
751 
 
752 
IO Utilization:
753 
 Number of IOs:                          80
754 
 Number of bonded IOBs:                  79  out of    240    32%
755 
 
756 
Specific Feature Utilization:
757 
 Number of Block RAM/FIFO:                3  out of    156     1%
758 
    Number using Block RAM only:          3
759 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
760 
 Number of DSP48E1s:                      1  out of    288     0%
761 
 
762 
---------------------------
763 
 
764 
====================================================================================
765 
#                            SYNTHESIS DONE
766 
#####################################################################################
767 
 
768 
#####################################################################################
769 
#                            START SYNTHESIS (SPEED optimized)
770 
#====================================================================================
771 
# virtex6 (xc6vlx75tff484), speedgrade: -2
772 
#====================================================================================
773 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
774 
#     12          10          0         0            0          0            0         1
775 
#====================================================================================
776 
Clock to Setup on destination clock dco_clk
777 
---------------+---------+---------+---------+---------+
778 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
779 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
780 
---------------+---------+---------+---------+---------+
781 
dco_clk        |   10.255|    3.286|    1.471|    0.601|
782 
---------------+---------+---------+---------+---------+
783 
 
784 
====================================================================================
785 
Device utilization summary:
786 
---------------------------
787 
 
788 
Selected Device : 6vlx75tff484-2
789 
 
790 
 
791 
Slice Logic Utilization:
792 
 Number of Slice Registers:             536  out of  93120     0%
793 
 Number of Slice LUTs:                 1613  out of  46560     3%
794 
    Number used as Logic:              1613  out of  46560     3%
795 
 
796 
Slice Logic Distribution:
797 
 Number of LUT Flip Flop pairs used:   1678
798 
   Number with an unused Flip Flop:    1142  out of   1678    68%
799 
   Number with an unused LUT:            65  out of   1678     3%
800 
   Number of fully used LUT-FF pairs:   471  out of   1678    28%
801 
   Number of unique control sets:        48
802 
 
803 
IO Utilization:
804 
 Number of IOs:                          80
805 
 Number of bonded IOBs:                  79  out of    240    32%
806 
 
807 
Specific Feature Utilization:
808 
 Number of Block RAM/FIFO:                3  out of    156     1%
809 
    Number using Block RAM only:          3
810 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
811 
 Number of DSP48E1s:                      1  out of    288     0%
812 
 
813 
---------------------------
814 
 
815 
====================================================================================
816 
#                            SYNTHESIS DONE
817 
#####################################################################################
818 
 
819 
#####################################################################################
820 
#                            START SYNTHESIS (SPEED optimized)
821 
#====================================================================================
822 
# virtex6 (xc6vlx75tff484), speedgrade: -3
823 
#====================================================================================
824 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
825 
#     12          10          0         0            0          0            0         1
826 
#====================================================================================
827 
Clock to Setup on destination clock dco_clk
828 
---------------+---------+---------+---------+---------+
829 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
830 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
831 
---------------+---------+---------+---------+---------+
832 
dco_clk        |    8.642|    3.262|    1.174|    0.518|
833 
---------------+---------+---------+---------+---------+
834 
 
835 
====================================================================================
836 
Device utilization summary:
837 
---------------------------
838 
 
839 
Selected Device : 6vlx75tff484-3
840 
 
841 
 
842 
Slice Logic Utilization:
843 
 Number of Slice Registers:             534  out of  93120     0%
844 
 Number of Slice LUTs:                 1632  out of  46560     3%
845 
    Number used as Logic:              1632  out of  46560     3%
846 
 
847 
Slice Logic Distribution:
848 
 Number of LUT Flip Flop pairs used:   1690
849 
   Number with an unused Flip Flop:    1156  out of   1690    68%
850 
   Number with an unused LUT:            58  out of   1690     3%
851 
   Number of fully used LUT-FF pairs:   476  out of   1690    28%
852 
   Number of unique control sets:        48
853 
 
854 
IO Utilization:
855 
 Number of IOs:                          80
856 
 Number of bonded IOBs:                  79  out of    240    32%
857 
 
858 
Specific Feature Utilization:
859 
 Number of Block RAM/FIFO:                3  out of    156     1%
860 
    Number using Block RAM only:          3
861 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
862 
 Number of DSP48E1s:                      1  out of    288     0%
863 
 
864 
---------------------------
865 
 
866 
====================================================================================
867 
#                            SYNTHESIS DONE
868 
#####################################################################################
869 
 

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