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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.tcl] - Blame information for rev 200

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1 62 olivier.gi
#!/usr/bin/tclsh
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#------------------------------------------------------------------------------
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# Copyright (C) 2001 Authors
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#
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# This source file may be used and distributed without restriction provided
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# that this copyright statement is not removed from the file and that any
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# derivative work contains the original copyright notice and the associated
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# disclaimer.
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#
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# This source file is free software; you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as published
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# by the Free Software Foundation; either version 2.1 of the License, or
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# (at your option) any later version.
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#
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public License
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# along with this source; if not, write to the Free Software Foundation,
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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#
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#------------------------------------------------------------------------------
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# 
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# File Name: run_analysis.tcl
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# 
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# Author(s):
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#             - Olivier Girard,    olgirard@gmail.com
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#
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#------------------------------------------------------------------------------
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# $Rev: 17 $
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# $LastChangedBy: olivier.girard $
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# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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#------------------------------------------------------------------------------
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###############################################################################
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#                         SET SOME GLOBAL VARIABLES                           #
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###############################################################################
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# Analysis type
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set analysisType SPEED
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#set analysisType AREA
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# Set the different FPGA architectures & models to be checked
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set fpgaConfigs {{spartan3     xc3s400pq208    {4 5}      {30.0 34.0}}
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                 {spartan3e    xc3s500epq208   {4 5}      {32.0 38.0}}
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                 {spartan3a    xc3s700aft256   {4 5}      {31.0 36.0}}
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                 {spartan3adsp xc3sd1800acs484 {4 5}      {31.0 39.0}}
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                 {spartan6     xc6slx45tfgg484 {2 3 4}    {41.0 58.0 68.0}}
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                 {virtex4      xc4vlx25sf363   {10 11 12} {51.0 57.0 69.0}}
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                 {virtex5      xc5vlx30ff324   {1 2 3}    {75.0 82.0 97.0}}
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                 {virtex6      xc6vlx75tff484  {1 2 3}    {92.0 102.0 115.0}}}
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# Set the different RTL configurations to be analysed
57 68 olivier.gi
set rtlDefines  {PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}
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set rtlConfigs {{    12          10          0         0            0          0            0         0}
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                {    12          10          1         0            0          0            0         0}
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                {    12          10          1         1            0          0            0         0}
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                {    12          10          1         1            1          0            0         0}
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                {    12          10          1         1            1          1            0         0}
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                {    12          10          1         1            1          1            1         0}}
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set clkRatios  {1.00 0.95 0.85 0.85 0.85 0.85}
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set rtlConfigs {{    12          10          0         0            0          0            0         1}}
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set clkRatios  {1.00}
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# RTL configuration files
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set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
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set rtlConfigFile  "./src/arch.v"
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###############################################################################
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#                              PERFORM ANALYSIS                               #
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###############################################################################
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foreach rtlConfig $rtlConfigs clkRatio $clkRatios {
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    #-------------------------------------------------------------------------#
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    #                        Generate RTL configuration                       #
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    #-------------------------------------------------------------------------#
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    # Read original define file
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    if [catch {open $omspConfigFile r} f_omspConfigFile] {
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        puts "ERROR: Cannot open file $omspConfigFile"
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        exit 1
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    }
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    set configFile [read $f_omspConfigFile]
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    close $f_omspConfigFile
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    # Update defines
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    set idx 0
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    foreach rtlDefine $rtlDefines {
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        if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} {
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        } else {
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            if {[lindex $rtlConfig $idx]==0} {
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                regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile
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            }
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        }
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        set idx [expr $idx+1]
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    }
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    # Write the new file
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    set f_configFile [open "./src/[file tail $omspConfigFile]" w]
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    puts $f_configFile $configFile
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    close $f_configFile
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    #-------------------------------------------------------------------------#
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    #                      Perform analysis for each FPGA                     #
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    #-------------------------------------------------------------------------#
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    foreach fpgaConfig $fpgaConfigs {
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        foreach speedGrade [lindex $fpgaConfig 2] clkFreq [lindex $fpgaConfig 3] {
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            # Create verilog arch define
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            set f_configFile [open $rtlConfigFile w]
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            puts $f_configFile "\n`define [string toupper [lindex $fpgaConfig 0]]\n"
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            close $f_configFile
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            # Cleanup
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            file delete -force ./WORK
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            file mkdir ./WORK
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            cd ./WORK
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            # Create links for RAM ngc files
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            file link "[lindex $fpgaConfig 0]_pmem.ngc" "../src/coregen/[lindex $fpgaConfig 0]_pmem.ngc"
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            file link "[lindex $fpgaConfig 0]_dmem.ngc" "../src/coregen/[lindex $fpgaConfig 0]_dmem.ngc"
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            # Create link to the Xilinx constraints file
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            if [catch {open "../openMSP430_fpga.ucf" r} f_ucf] {
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                puts "ERROR: Cannot open constrain file ../openMSP430_fpga.ucf"
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                exit 1
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            }
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            set ucf [read $f_ucf]
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            close $f_ucf
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            if {[string eq $analysisType "AREA"] || [string eq $clkFreq "-1"]} {
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                regsub {<COMMENT>} $ucf "\#" ucf
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            } else {
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                regsub {<COMMENT>} $ucf "" ucf
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            }
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            regsub {<PERIOD>}      $ucf "[expr 1000/($clkFreq*$clkRatio)]"     ucf
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            regsub {<HALF_PERIOD>} $ucf "[expr (1000/($clkFreq*$clkRatio))/2]" ucf
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            set f_ucf [open "openMSP430_fpga.ucf" w]
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            puts $f_ucf $ucf
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            close $f_ucf
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            # Copy synthesis configuration script
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            if [catch {open "../xst_verilog_[lindex $fpgaConfig 0].opt" r} f_xst_verilog] {
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                puts "ERROR: Cannot open timing file ../xst_verilog_[lindex $fpgaConfig 0].opt"
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                exit 1
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            }
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            set xst_verilog [read $f_xst_verilog]
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            close $f_xst_verilog
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            regsub {\"-opt_mode SPEED\";} $xst_verilog "\"-opt_mode $analysisType\";" xst_verilog
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            set f_xst_verilog [open "xst_verilog.opt" w]
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            puts $f_xst_verilog $xst_verilog
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            close $f_xst_verilog
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            # Run synthesis
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            puts "#####################################################################################"
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            puts "#                            START SYNTHESIS ($analysisType optimized)"
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            puts "#===================================================================================="
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            puts "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: -$speedGrade"
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            puts "#===================================================================================="
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            puts "# $rtlDefines"
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            puts "# $rtlConfig"
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            puts "#===================================================================================="
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            set fpgaName "[lindex $fpgaConfig 1]-$speedGrade"
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            if {[catch "exec xflow -p $fpgaName -implement high_effort.opt    \
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                                   -config    bitgen.opt         \
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                                   -synth     ./xst_verilog.opt  \
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                                   ../openMSP430_fpga.prj"]} {
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                puts "ERROR: Synthesis error !!!!!!"
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                exit 1
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            }
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            # Extract timing information
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            if [catch {open "openMSP430_fpga.twr" r} f_timing] {
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                puts "ERROR: Cannot open timing file openMSP430_fpga.twr"
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                exit 1
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            }
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            set timingFile [read $f_timing]
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            close $f_timing
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            regexp {Clock to Setup on destination.*\+\n} $timingFile whole_match
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            puts $whole_match
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            puts "===================================================================================="
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            # Extract size information
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            if [catch {open "openMSP430_fpga_xst.log" r} f_log] {
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                puts "ERROR: Cannot open timing file openMSP430_fpga_xst.log"
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                exit 1
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            }
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            set logFile [read $f_log]
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            close $f_log
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            regexp {(Device utilization summary:.*\n)Partition Resource Summary:} $logFile whole_match area
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            puts $area
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            puts "===================================================================================="
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            puts "#                            SYNTHESIS DONE"
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            puts "#####################################################################################"
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            puts ""
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            cd ../
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        }
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    }
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}
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exit 0

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