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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [spartan3adsp_pmem.vho] - Blame information for rev 62

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1 62 olivier.gi
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--     This file is owned and controlled by Xilinx and must be used           --
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--     solely for design, simulation, implementation and creation of          --
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--     design files limited to Xilinx devices or technologies. Use            --
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--     with non-Xilinx devices or technologies is expressly prohibited        --
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--     and immediately terminates your license.                               --
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--                                                                            --
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--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
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--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
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--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
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--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
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--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
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--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
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--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
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--     FOR A PARTICULAR PURPOSE.                                              --
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--                                                                            --
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--     Xilinx products are not intended for use in life support               --
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--     appliances, devices, or systems. Use in such applications are          --
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--     expressly prohibited.                                                  --
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--                                                                            --
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--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
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--     All rights reserved.                                                   --
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--------------------------------------------------------------------------------
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-- The following code must appear in the VHDL architecture header:
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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component spartan3adsp_pmem
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        port (
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        clka: IN std_logic;
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        ena: IN std_logic;
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        wea: IN std_logic_VECTOR(1 downto 0);
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        addra: IN std_logic_VECTOR(11 downto 0);
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        dina: IN std_logic_VECTOR(15 downto 0);
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        douta: OUT std_logic_VECTOR(15 downto 0));
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end component;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : spartan3adsp_pmem
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                port map (
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                        clka => clka,
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                        ena => ena,
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                        wea => wea,
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                        addra => addra,
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                        dina => dina,
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                        douta => douta);
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-- INST_TAG_END ------ End INSTANTIATION Template ------------
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-- You must compile the wrapper file spartan3adsp_pmem.vhd when simulating
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-- the core, spartan3adsp_pmem. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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