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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [virtex4lx.cgp] - Blame information for rev 100

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Line No. Rev Author Line
1 62 olivier.gi 
# Date: Sat Jan 30 22:09:56 2010
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SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc5vlx20t
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SET devicefamily = virtex5
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff323
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = False
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SET vhdlsim = True
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SET workingdirectory = ./tmp/
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# CRC: 4cfc2e68

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