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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [virtex6.cgp] - Blame information for rev 62

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Line No. Rev Author Line
1 62 olivier.gi 
# Date: Sun Jan 17 12:43:52 2010
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = Verilog
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SET device = xc6vcx75t
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SET devicefamily = virtex6
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SET flowvendor = Foundation_ISE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff484
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = True
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SET vhdlsim = False
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SET workingdirectory = ./tmp/
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# CRC: 77b862b1

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