OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [virtex6_pmem_readme.txt] - Blame information for rev 62

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 62 olivier.gi
The following files were generated for 'virtex6_pmem' in directory
2
/home/pitchu/Projects/verilog/openMSP430/core/synthesis/xilinx/src/coregen/
3
 
4
virtex6_pmem_flist.txt:
5
   Text file listing all of the output files produced when a customized
6
   core was generated in the CORE Generator.
7
 
8
blk_mem_gen_ds512.pdf:
9
   Please see the core data sheet.
10
 
11
virtex6_pmem.gise:
12
   ISE Project Navigator support file. This is a generated file and should
13
   not be edited directly.
14
 
15
virtex6_pmem.ise:
16
   ISE Project Navigator support file. This is a generated file and should
17
   not be edited directly.
18
 
19
virtex6_pmem.ngc:
20
   Binary Xilinx implementation netlist file containing the information
21
   required to implement the module in a Xilinx (R) FPGA.
22
 
23
virtex6_pmem.v:
24
   Verilog wrapper file provided to support functional simulation.
25
   This file contains simulation model customization data that is
26
   passed to a parameterized simulation model for the core.
27
 
28
virtex6_pmem.veo:
29
   VEO template file containing code that can be used as a model for
30
   instantiating a CORE Generator module in a Verilog design.
31
 
32
virtex6_pmem.xco:
33
   CORE Generator input file containing the parameters used to
34
   regenerate a core.
35
 
36
virtex6_pmem.xise:
37
   ISE Project Navigator support file. This is a generated file and should
38
   not be edited directly.
39
 
40
virtex6_pmem_readme.txt:
41
   Text file indicating the files generated and how they are used.
42
 
43
virtex6_pmem_xmdf.tcl:
44
   ISE Project Navigator interface file. ISE uses this file to determine
45
   how the files output by CORE Generator for the core can be integrated
46
   into your ISE project.
47
 
48
 
49
Please see the Xilinx CORE Generator online help for further details on
50
generated files and how to use them.
51
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.