Subversion Repositories openmsp430

FLOWTYPE = FPGA_SYNTHESIS;

#########################################################

## Filename: xst_verilog.opt

##

## Verilog Option File for XST targeted for speed

## This works for FPGA devices.

##

## Version: 11.1

## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_verilog_speed.opt,v 1.14 2008/10/20 23:47:14 rvklair Exp $

#########################################################

#

# Options for XST

#

#

Program xst

-ifn _xst.scr;            # input XST script file

-ofn _xst.log;            # output XST log file

-intstyle xflow;                  # Message Reporting Style: ise, xflow, or silent

#

# The options listed under ParamFile are the XST Properties that can be set by the

# user. To turn on an option, uncomment by removing the '#' in front of the switch.

#

ParamFile: _xst.scr

"run";

#

# Global Synthesis Options

#

"-ifn ";             # Input/Project File Name

"-ifmt Verilog";                  # Input Format

"-ofn ";                  # Output File Name

"-ofmt ngc";                      # Output File Format

"-p ";                  # Target Device

"-verilog2001 YES";               # Enables the use of Verilog 2001 Constructs

                                  # YES, NO

"-opt_level 2";                   # Optimization Effort Criteria

                                  # 1 (Normal) or 2 (High)

"-opt_mode SPEED";                # Optimization Criteria

                                  # AREA or SPEED

"-vlgincdir ../src/";

#"-uc .xcf";              # Constraint File name

#"-case maintain";                # Specifies how to handle source name case

                                  # upper, lower, maintain

#"-keep_hierarchy NO";            # Prevents optimization across module boundaries

                                  # CPLD default YES, FPGA default NO

#"-write_timing_constraints NO";  # Write Timing Constraints

                                  # YES, NO

#"-cross_clock_analysis NO";      # Cross Clock Option

                                  # YES, NO

#"-iobuf YES";                    # Add I/O Buffers to top level ports

                                  # YES, NO

#

# The following are HDL Options

#

# The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2

#

#"-register_balancing NO";        # Register Balancing

                                  # YES, NO, Forward, Backward

#"-move_first_stage YES";         # Move First Flip-Flop Stage

                                  # YES, NO

#"-move_last_stage YES";          # Move Last Flip-Flop Stage

                                  # YES, NO

End ParamFile

End Program xst

#

# See XST USER Guide Chapter 8 (Command Line Mode) for all XST options

#