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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 ASIC Implementation</title>
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  <meta http-equiv="content-type" content="text/html; charset=utf-8">
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  <meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body>
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<h3>Table of content</h3>
29 
 
30 
<ul>
31 
 
32 
  <li><a href="#1_Introduction">1. Introduction</a></li>
33 
  <li><a href="#2_RTL_Configuration"> 2. RTL Configuration</a>
34 
    <ul>
35 
      <li><a href="#2_1_1_Low_Frequency_Clock_Domain"> 2.1 Basic Clock
36 
Module</a></li>
37 
      <ul>
38 
        <li><a href="#2_1_1_Low_Frequency_Clock_Domain"> 2.1.1
39 
Low-frequency clock domain</a></li>
40 
      </ul>
41 
      <ul>
42 
        <li><a href="#2_1_2_Clock_Muxes"> 2.1.2 Clock muxes</a></li>
43 
      </ul>
44 
      <ul>
45 
        <li><a href="#2_1_3_Clock_Dividers"> 2.1.3 Clock dividers</a></li>
46 
      </ul>
47 
      <ul>
48 
        <li><a href="#2_1_4_Low_Power_Modes">2.1.4 Low-Power modes</a></li>
49 
        <ul>
50 
          <li><a href="#2_1_4_1_Internal_clocks">2.1.4.1 Internal
51 
clocks ( MCLK / SMCLK )</a><br>
52 
          </li>
53 
          <li><a href="#2_1_4_2_Clock_oscillators">2.1.4.2 Clock
54 
oscillators ( DCO_CLK / LFXT_CLK )</a><br>
55 
          </li>
56 
        </ul>
57 
      </ul>
58 
      <li><a href="#2_2_Other_configuration_options">2.2 Other
59 
configuration options</a><br>
60 
      </li>
61 
      <ul>
62 
        <li><a href="#2_2_1_Fine_Grained_Clock_Gating"> 2.2.1 Fine
63 
grained clock gating</a></li>
64 
      </ul>
65 
      <ul>
66 
        <li><a href="#2_2_2_Watchdog_Clock_Mux"> 2.2.2 Watchdog clock
67 
mux</a></li>
68 
      </ul>
69 
    </ul>
70 
  </li>
71 
  <li><a href="#3._DFT_Considerations"> 3. DFT&nbsp; considerations</a></li>
72 
  <ul>
73 
    <li><a href="#3_1_Resets">3.1 Resets</a></li>
74 
    <li><a href="#3_2_Clock_Gates">3.2 Clock Gates</a></li>
75 
    <li><a href="#3_3_Clock_Muxes">3.3 Clock Muxes</a></li>
76 
    <li><a href="#3_4_Coverage">3.4 Coverage</a></li>
77 
  </ul>
78 
  <li><a href="#4_Sensitive_Modules"> 4. Sensitive modules</a><br>
79 
    <ul>
80 
      <li><a href="#4_1_AND_Gate"> 4.1 AND Gate ( <span style="font-style: italic;">omsp_and_gate.v</span> )<br>
81 
        </a></li>
82 
      <li><a href="#4_2_Clock_Gate">4.2 Clock Gate ( <span style="font-style: italic;">omsp_clock_gate.v</span> )</a></li>
83 
      <li><a href="#4_3_Clock_Mux">4.3 Clock Mux ( <span style="font-style: italic;">omsp_clock_mux.v</span> )</a></li>
84 
      <li><a href="#4_4_Scan_Mux">4.4 Scan Mux ( <span style="font-style: italic;">omsp_scan_mux.v</span> )</a></li>
85 
      <li><a href="#4_5_Sync_Cell">4.5 Sync Cell ( <span style="font-style: italic;">omsp_sync_cell.v</span> )</a></li>
86 
      <li><a href="#4_6_Sync_Reset">4.6 Sync Reset ( <span style="font-style: italic;">omsp_sync_reset.v</span> )</a></li>
87 
      <li><a href="#4_7_Wakeup_Cell">4.7 Wakeup Cell
88 
( <span style="font-style: italic;">omsp_wakeup_cell.v</span> )</a></li>
89 
    </ul>
90 
  </li>
91 
</ul>
92 
 
93 
<a name="1_Introduction"></a>
94 
<h1>1. Introduction</h1>
95 
 
96 
This section covers specific points of the openMSP430 ASIC
97 
implementation, in particular:<br>
98 
 
99 
<ul>
100 
 
101 
  <ul>
102 
    <ul>
103 
      <li>The ASIC specific RTL configuration options.</li>
104 
      <li>Some DFT
105 
considerations.</li>
106 
      <li>A description of each ASIC sensitive module.<br>
107 
      </li>
108 
    </ul>
109 
  </ul>
110 
</ul>
111 
 
112 
Keep in mind that as no exotic design technique were used in the
113 
openMSP430,
114 
following a standard implementation flow from
115 
Synthesis to P&amp;R is the best way to go.<br>
116 
 
117 
&nbsp;<br>
118 
 
119 
<br>
120 
 
121 
<a name="2_RTL_Configuration"></a>
122 
<h1>2. RTL Configuration</h1>
123 
 
124 
Whenever the "<span style="font-weight: bold; font-style: italic;">`define
125 
ASIC</span>" statement of the <a style="font-style: italic;" href="http://opencores.org/project,openmsp430,core#2.1.3.3%20Expert%20System%20Configuration">Expert
126 
System Configuration</a> section is uncommented, all ASIC specific
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configuration options are enabled.<br>
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129 
<a name="2_1_Basic_Clock_Module"></a>
130 
<h2>2.1 Basic Clock Module</h2>
131 
 
132 
In its ASIC configuration, the Basic clock module of the openMSP430 can
133 
support <span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space">&nbsp;</span>up to all features
134 
described
135 
in the<span class="Apple-converted-space">&nbsp;</span><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's
136 
Guide</a><span class="Apple-converted-space">&nbsp;</span>(Chapter 4).<br>
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</span><br>
138 
In particular,  the <span style="font-weight: bold; font-style: italic;">ASIC_CLOCKING</span>
139 
option activates all advancd clocking options (note that formal equivalence with
140 
the FPGA version is achieved by commenting this option out):<br>
141 
<br>
142 
 
143 
 
144 
<table border="0" cellpadding="0" cellspacing="4">
145 
 
146 
 
147 
  <tbody>
148 
    <tr>
149 
      <td width="35"><br>
150 
      </td>
151 
      <td bgcolor="#d0d0d0" width="3"><br>
152 
      </td>
153 
      <td width="15"><br>
154 
      </td>
155 
      <td> <code>//===============================================================<br>
156 
// ASIC CLOCKING<br>
157 
//===============================================================<br>
158 
      <br>
159 
//-------------------------------------------------------<br>
160 
// When uncommented, this define will enable the ASIC<br>
161 
// architectural clock gating as well as the advanced low<br>
162 
// power modes support (most common).<br>
163 
// Comment this out in order to get FPGA-like clocking.<br>
164 
//-------------------------------------------------------<br>
165 
`define ASIC_CLOCKING<br>
166 
<br>
167 
      </code></td>
168 
    </tr>
169 
  </tbody>
170 
</table>
171 
 
172 
 
173 
<br>
174 
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">All these advanced clocking options are highlighted in the following diagram and
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discussed below:<br>
176 
<br>
177 
</span>
178 
<div style="text-align: center;"><img alt="Clock Module ASIC configuration" src="http://opencores.org/usercontent,img,1321995017" width="80%"><br>
179 
</div>
180 
 
181 
<a name="2_1_1_Low_Frequency_Clock_Domain"></a>
182 
<h3>2.1.1 Low-Frequency Clock Domain</h3>
183 
 
184 
The LFXT clock domain can be enabled thanks to the following
185 
configuration
186 
option:<br>
187 
 
188 
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span></span><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span></span><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span></span><br>
189 
 
190 
<table border="0" cellpadding="0" cellspacing="4">
191 
 
192 
  <tbody>
193 
    <tr>
194 
      <td width="35"><br>
195 
      </td>
196 
      <td bgcolor="#d0d0d0" width="3"><br>
197 
      </td>
198 
      <td width="15"><br>
199 
      </td>
200 
      <td> <code>//============================================================================<br>
201 
// LFXT CLOCK DOMAIN<br>
202 
//============================================================================<br>
203 
      <br>
204 
//-------------------------------------------------------<br>
205 
// When uncommented, this define will enable the lfxt_clk<br>
206 
// clock domain.<br>
207 
// When commented out, the whole chip is clocked with dco_clk.<br>
208 
//-------------------------------------------------------<br>
209 
`define LFXT_DOMAIN<br>
210 
      <br>
211 
      </code></td>
212 
    </tr>
213 
  </tbody>
214 
</table>
215 
 
216 
<br>
217 
 
218 
<span style="font-style: italic; font-weight: bold; text-decoration: underline;">Note
219 
1:</span> When commented-out:<br>
220 
 
221 
<ul>
222 
 
223 
  <ul>
224 
    <ul>
225 
      <li><span style="font-style: italic;">ACLK</span> is running on <span style="font-style: italic;">DCO_CLK</span></li>
226 
      <li>MCLK_MUX and SMCLK_MUX options are not supported</li>
227 
      <li>OSCOFF_EN low power mode is not supported<span style="font-style: italic;"><br>
228 
        </span></li>
229 
    </ul>
230 
  </ul>
231 
</ul>
232 
 
233 
<span style="font-weight: bold; font-style: italic; text-decoration: underline;">Note
234 
2:</span> Unlike its name suggest, there is no frequency limitation on <span style="font-style: italic;">LFXT_CLK</span>. The name was simply kept
235 
in order to be consistent with the original MSP430 documentation, where
236 
<span style="font-style: italic;">LFXT_CLK</span> is
237 
typically connected to a 32 kHz crystal oscillator.<br>
238 
 
239 
<br>
240 
 
241 
<a name="2_1_2_Clock_Muxes"></a><br>
242 
 
243 
<h3>2.1.2 Clock Muxes</h3>
244 
 
245 
The <span style="font-style: italic;">MCLK</span> and <span style="font-style: italic;">SMCLK</span> clock muxes can be enabled or
246 
disabled with the following options:<br>
247 
 
248 
<br>
249 
 
250 
<table border="0" cellpadding="0" cellspacing="4">
251 
 
252 
  <tbody>
253 
    <tr>
254 
      <td width="35"><br>
255 
      </td>
256 
      <td bgcolor="#d0d0d0" width="3"><br>
257 
      </td>
258 
      <td width="15"><br>
259 
      </td>
260 
      <td> <code>//============================================================================<br>
261 
// CLOCK MUXES<br>
262 
//============================================================================<br>
263 
      <br>
264 
//-------------------------------------------------------<br>
265 
// MCLK: Clock Mux<br>
266 
//-------------------------------------------------------<br>
267 
// When uncommented, this define will enable the<br>
268 
// MCLK clock MUX allowing the selection between<br>
269 
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.<br>
270 
// When commented, DCO_CLK is selected.<br>
271 
//-------------------------------------------------------<br>
272 
`define MCLK_MUX<br>
273 
      <br>
274 
//-------------------------------------------------------<br>
275 
// SMCLK: Clock Mux<br>
276 
//-------------------------------------------------------<br>
277 
// When uncommented, this define will enable the<br>
278 
// SMCLK clock MUX allowing the selection between<br>
279 
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.<br>
280 
// When commented, DCO_CLK is selected.<br>
281 
//-------------------------------------------------------<br>
282 
`define SMCLK_MUX<br>
283 
      <br>
284 
      </code></td>
285 
    </tr>
286 
  </tbody>
287 
</table>
288 
 
289 
<br>
290 
 
291 
<span style="font-style: italic; font-weight: bold; text-decoration: underline;">Note
292 
1:</span> When a MUX is excluded, the concerned clock (<span style="font-style: italic;">MCLK</span> and/or <span style="font-style: italic;">SMCLK) is</span> running with <span style="font-style: italic;">DCO_CLK</span>.<br>
293 
 
294 
<br>
295 
 
296 
<span style="font-weight: bold; font-style: italic; text-decoration: underline;">Note
297 
2:</span> If a MUX is included, the implementation and sign-off tools
298 
(in particular CTS and STA) must be aware
299 
that a new clock needs to be defined on the MUX output.<br>
300 
 
301 
<br>
302 
 
303 
<br>
304 
 
305 
<a name="2_1_3_Clock_Dividers"></a>
306 
<h3>2.1.3 Clock Dividers</h3>
307 
 
308 
The <span style="font-style: italic;">MCLK</span>, <span style="font-style: italic;">SMCLK</span> and ACLK clock dividers can
309 
be enabled or disabled with the following options:<br>
310 
 
311 
<br>
312 
 
313 
<table border="0" cellpadding="0" cellspacing="4">
314 
 
315 
  <tbody>
316 
    <tr>
317 
      <td width="35"><br>
318 
      </td>
319 
      <td bgcolor="#d0d0d0" width="3"><br>
320 
      </td>
321 
      <td width="15"><br>
322 
      </td>
323 
      <td> <code>//============================================================================<br>
324 
// CLOCK DIVIDERS<br>
325 
//============================================================================<br>
326 
      <br>
327 
//-------------------------------------------------------<br>
328 
// MCLK: Clock divider<br>
329 
//-------------------------------------------------------<br>
330 
// When uncommented, this define will enable the<br>
331 
// MCLK clock divider (/1/2/4/8)<br>
332 
//-------------------------------------------------------<br>
333 
`define MCLK_DIVIDER<br>
334 
      <br>
335 
//-------------------------------------------------------<br>
336 
// SMCLK: Clock divider (/1/2/4/8)<br>
337 
//-------------------------------------------------------<br>
338 
// When uncommented, this define will enable the<br>
339 
// SMCLK clock divider<br>
340 
//-------------------------------------------------------<br>
341 
`define SMCLK_DIVIDER<br>
342 
      <br>
343 
//-------------------------------------------------------<br>
344 
// ACLK: Clock divider (/1/2/4/8)<br>
345 
//-------------------------------------------------------<br>
346 
// When uncommented, this define will enable the<br>
347 
// ACLK clock divider<br>
348 
//-------------------------------------------------------<br>
349 
`define ACLK_DIVIDER<br>
350 
      <br>
351 
      </code></td>
352 
    </tr>
353 
  </tbody>
354 
</table>
355 
 
356 
<br>
357 
 
358 
The clock dividers instantiate a clock gate on the clock tree and are
359 
implemented as following:<br>
360 
 
361 
<br>
362 
 
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<div style="text-align: center;"><img alt="Clock Divider" src="http://opencores.org/usercontent,img,1322310000" width="50%"><br>
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</div>
365 
 
366 
<br>
367 
 
368 
<a name="2_1_4_Low_Power_Modes"></a>
369 
<h3>2.1.4 Low-Power Modes</h3>
370 
 
371 
<a name="2_1_4_1_Internal_clocks"><br>
372 
</a><span style="font-weight: bold;">2.1.4.1 Internal clocks ( MCLK /
373 
SMCLK )</span><br>
374 
 
375 
<br>
376 
 
377 
Two bit fields in the status register (R2) allow to
378 
control the system clocks:<br>
379 
 
380 
<ul>
381 
 
382 
  <ul>
383 
    <ul>
384 
      <li><span style="font-weight: bold;">CPUOFF</span> allows to
385 
switch-off <span style="font-style: italic;">MCLK</span></li>
386 
      <li><span style="font-weight: bold;">SCG1</span> allows to
387 
switch-off <span style="font-style: italic;">SMCLK</span><br>
388 
      </li>
389 
    </ul>
390 
  </ul>
391 
</ul>
392 
 
393 
These control bits are supported by the openMSP430 and can be
394 
included in the design with the following defines:<br>
395 
 
396 
<br>
397 
 
398 
<table border="0" cellpadding="0" cellspacing="4">
399 
 
400 
  <tbody>
401 
    <tr>
402 
      <td width="35"><br>
403 
      </td>
404 
      <td bgcolor="#d0d0d0" width="3"><br>
405 
      </td>
406 
      <td width="15"><br>
407 
      </td>
408 
      <td><code>//============================================================================<br>
409 
// LOW POWER MODES<br>
410 
//============================================================================<br>
411 
      <br>
412 
//-------------------------------------------------------<br>
413 
// LOW POWER MODE: CPUOFF<br>
414 
//-------------------------------------------------------<br>
415 
// When uncommented, this define will include the<br>
416 
// clock gate allowing to switch off MCLK in<br>
417 
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4<br>
418 
//-------------------------------------------------------<br>
419 
`define CPUOFF_EN<br>
420 
      <br>
421 
//-------------------------------------------------------<br>
422 
// LOW POWER MODE: SCG1<br>
423 
//-------------------------------------------------------<br>
424 
// When uncommented, this define will include the<br>
425 
// clock gate allowing to switch off SMCLK in<br>
426 
// the following low power modes: LPM2, LPM3, LPM4<br>
427 
//-------------------------------------------------------<br>
428 
`define SCG1_EN<br>
429 
      <br>
430 
      </code></td>
431 
    </tr>
432 
  </tbody>
433 
</table>
434 
 
435 
<br>
436 
 
437 
In order to keep the clock tree as flat as possible, the CPUOFF and
438 
SCG1 low power options share the same clock gate with the clock divider:<br>
439 
 
440 
<br>
441 
 
442 
<div style="text-align: center;"><img alt="Clock Divider and low power" src="http://opencores.org/usercontent,img,1322310023" width="50%"><br>
443 
</div>
444 
 
445 
<a name="2_1_4_2_Clock_oscillators"><br>
446 
</a><span style="font-weight: bold;">2.1.4.2 Clock oscillators (
447 
DCO_CLK / LFXT_CLK )</span><br>
448 
 
449 
<br>
450 
 
451 
There are two bit fields in the status register (R2) allowing to
452 
control the clock oscillators:<br>
453 
 
454 
<ul>
455 
 
456 
  <ul>
457 
    <ul>
458 
      <li><span style="font-weight: bold;">SCG0</span> allows to
459 
switch-off the DCO oscillator<span style="font-style: italic;"></span></li>
460 
      <li><span style="font-weight: bold;">OSCOFF</span> allows to
461 
switch-off the LFXT oscillator<span style="font-style: italic;"></span><br>
462 
      </li>
463 
    </ul>
464 
  </ul>
465 
</ul>
466 
 
467 
These control bits are supported by the openMSP430 and can be
468 
included in the design with the following defines:<br>
469 
 
470 
<br>
471 
 
472 
<table border="0" cellpadding="0" cellspacing="4">
473 
 
474 
  <tbody>
475 
    <tr>
476 
      <td width="35"><br>
477 
      </td>
478 
      <td bgcolor="#d0d0d0" width="3"><br>
479 
      </td>
480 
      <td width="15"><br>
481 
      </td>
482 
      <td><code>//============================================================================<br>
483 
// LOW POWER MODES<br>
484 
//============================================================================<br>
485 
      <br>
486 
//-------------------------------------------------------<br>
487 
// LOW POWER MODE: SCG0<br>
488 
//-------------------------------------------------------<br>
489 
// When uncommented, this define will enable the<br>
490 
// DCO_ENABLE/WKUP port control (always 1 when commented).<br>
491 
// This allows to switch off the DCO oscillator in the<br>
492 
// following low power modes: LPM1, LPM3, LPM4<br>
493 
//-------------------------------------------------------<br>
494 
`define SCG0_EN<br>
495 
      <br>
496 
//-------------------------------------------------------<br>
497 
// LOW POWER MODE: OSCOFF<br>
498 
//-------------------------------------------------------<br>
499 
// When uncommented, this define will include the<br>
500 
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP<br>
501 
// port control (always 1 when commented).<br>
502 
// This allows to switch off the low frequency oscillator<br>
503 
// in the following low power modes: LPM4<br>
504 
//-------------------------------------------------------<br>
505 
`define OSCOFF_EN<br>
506 
      <br>
507 
      </code></td>
508 
    </tr>
509 
  </tbody>
510 
</table>
511 
 
512 
<br>
513 
 
514 
The control logic of both DCO and LFXT oscillators is identical.<br>
515 
 
516 
<br>
517 
 
518 
When disabled, the <span style="font-weight: bold;">*_WKUP</span>
519 
signal
520 
is used to asynchronously wake up the oscillator. Once the oscillator
521 
is awake (and therefore a clock is available), the <span style="font-weight: bold;">*_ENABLE</span> signal will take over and
522 
synchronously keep the oscillator enabled until the CPU clears the SCG0
523 
or OSCOFF bit again.<br>
524 
 
525 
<br>
526 
 
527 
The following two waveforms illustrate the CPU entering the LPM1 mode,
528 
and in particular the DCO oscillator being switched-off:<br>
529 
 
530 
<ul>
531 
 
532 
  <li>Entering LPM1 through a <span style="font-weight: bold; font-style: italic; color: rgb(51, 51, 153);">BIS
533 
#N, R2</span>
534 
instruction:</li>
535 
</ul>
536 
 
537 182 olivier.gi 
<img alt="Entering LPM1 with BIS" src="http://opencores.org/usercontent,img,1322600748" width="100%"><br>
538 135 olivier.gi 
 
539 
<ul>
540 
 
541 
  <li>Entering LPM1 through a <span style="font-weight: bold; font-style: italic; color: rgb(51, 51, 153);">RETI</span>
542 
instruction:<br>
543 
  </li>
544 
</ul>
545 
 
546 
<img alt="Entering LPM1 with RETI" src="http://opencores.org/usercontent,img,1322600763" width="100%"><br>
547 
 
548 
<br>
549 
 
550 
<span style="font-weight: bold; text-decoration: underline;">Note:</span>
551 
the DCO oscillator is enabled until the BIS and RETI instruction are
552 
fully executed (i.e. until the CPU state machines reach their IDLE
553 
state).<br>
554 
 
555 
<br>
556 
 
557 
<br>
558 
 
559 
At last, this waveform shows the CPU going out of LPM1 mode and in
560 
particular the DCO oscillator wake-up sequence:<br>
561 
 
562 
<br>
563 
 
564 182 olivier.gi 
<img alt="Wakeup from LPM1" src="http://opencores.org/usercontent,img,1322602185" width="100%"><br>
565 135 olivier.gi 
 
566 
<br>
567 
 
568 
In order to wake-up the CPU from ANY low power mode, the system <span style="font-weight: bold;">MUST ALWAYS</span> go through the following
569 
chain of events (as illustrated in the previous waveform):<br>
570 
 
571 
<ul>
572 
 
573 
  <ul>
574 
    <ol>
575 
      <li style="color: red;">&nbsp;<span style="color: black;">The
576 
peripheral (for example a timer) asserts the </span><span style="font-weight: bold; font-style: italic; color: black;">WKUP</span><span style="color: black;"> input of the openMSP430 in order to
577 
asynchronously restore the clocks. At this stage, </span><span style="font-weight: bold; font-style: italic; color: black;">DCO_WKUP</span><span style="color: black;"> is activated and </span><span style="font-weight: bold; font-style: italic; color: black;">DCO_ENABLE</span><span style="color: black;"> is still cleared.</span></li>
578 
      <li style="color: red;">&nbsp;<span style="color: black;">Once
579 
MCLK is available, the peripheral generates a synchronous IRQ signal in
580 
order to re-activate the CPU state machines.</span></li>
581 
      <li style="color: red;">&nbsp;<span style="color: black;">The CPU
582 
state machines activated, </span><span style="font-weight: bold; font-style: italic; color: black;">DCO_ENABLE</span><span style="color: black;"> is synchronously set.</span><br>
583 
      </li>
584 
      <li style="color: red;">&nbsp;<span style="color: black;">When
585 
the global interrupt enable flag (GIE) is cleared, <span style="font-weight: bold; font-style: italic;">DCO_WKUP</span> is
586 
released two clock cycles later (i.e. same behavior as a reset
587 
synchronizer).<br>
588 
        <span style="font-weight: bold; text-decoration: underline;">Important
589 
note:</span> the peripheral should release the </span><span style="font-weight: bold; font-style: italic; color: black;">WKUP</span><span style="color: black;"> input when its interrupt pending flag is cleared</span><span style="font-weight: bold; font-style: italic; color: black;"></span><span style="color: black;">. Otherwise the <span style="font-weight: bold; font-style: italic;">DCO_WKUP</span> signal
590 
will be set again as soon as the GIE flag is restored by the RETI
591 
instruction... which is probably not the intended behavior :-P<br>
592 
        </span></li>
593 
      <li style="color: red;"><span style="color: black;">The DCO
594 
oscillator is now enabled until SCG0 is set again.</span><br>
595 
      </li>
596 
    </ol>
597 
  </ul>
598 
</ul>
599 
 
600 
<br>
601 
 
602 
<a name="2_2_Other_configuration_options"></a>
603 
<h2>2.2 Other configuration options</h2>
604 
 
605 
<a name="2_2_1_Fine_Grained_Clock_Gating"></a>
606 
<h3>2.2.1 Fine Grained Clock Gating</h3>
607 
 
608 
Nowadays, all synthesis tools support automatic (fine grained) clock
609 
gating insertion.<br>
610 
 
611 
However, as some design houses still prefer to have the clock gates
612 
directly instantiated in the RTL, there is the possibility to include
613 
the <span style="font-style: italic;">'manual</span>' fine grained
614 
clock gates in the design with the following define:<br>
615 
 
616 
<br>
617 
 
618 
<table border="0" cellpadding="0" cellspacing="4">
619 
 
620 
  <tbody>
621 
    <tr>
622 
      <td width="35"><br>
623 
      </td>
624 
      <td bgcolor="#d0d0d0" width="3"><br>
625 
      </td>
626 
      <td width="15"><br>
627 
      </td>
628 
      <td><code>//============================================================================<br>
629 
// FINE GRAINED CLOCK GATING<br>
630 
//============================================================================<br>
631 
      <br>
632 
//-------------------------------------------------------<br>
633 
// When uncommented, this define will enable the fine<br>
634 
// grained clock gating of all registers in the core.<br>
635 
//-------------------------------------------------------<br>
636 
`define CLOCK_GATING<br>
637 
      <br>
638 
      </code></td>
639 
    </tr>
640 
  </tbody>
641 
</table>
642 
 
643 
<br>
644 
 
645 
<br>
646 
 
647 
<a name="2_2_2_Watchdog_Clock_Mux"></a>
648 
<h3>2.2.2 Watchdog Clock Mux</h3>
649 
 
650 
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">The
651 
watchdog clock <span class="Apple-converted-space"><span style="font-style: italic;"></span></span><span style="font-style: italic;"></span><span class="Apple-converted-space"></span><span class="Apple-converted-space"></span><span style="font-style: italic;"></span><span class="Apple-converted-space"></span>mux allows to select between <span style="font-style: italic;">ACLK</span> and <span style="font-style: italic;">SMCLK</span>. It can be enabled or
652 
disabled with the <span style="font-weight: bold;">WATCHDOG_MUX</span>
653 
define.<br>
654 
</span>When excluded, the additional <span style="font-weight: bold;">WATCHDOG_NOMUX_ACLK</span>&nbsp;
655 
option allows the user to decide if the watchdog clock should be
656 
hard-wired to <span style="font-style: italic;">ACLK</span> (if
657 
uncommented) or <span style="font-style: italic;">SMCLK</span> (if
658 
commented-out)<br>
659 
 
660 
<br>
661 
 
662 
<table border="0" cellpadding="0" cellspacing="4">
663 
 
664 
  <tbody>
665 
    <tr>
666 
      <td width="35"><br>
667 
      </td>
668 
      <td bgcolor="#d0d0d0" width="3"><br>
669 
      </td>
670 
      <td width="15"><br>
671 
      </td>
672 
      <td> <code>//============================================================================<br>
673 
// CLOCK MUXES<br>
674 
//============================================================================<br>
675 
      <br>
676 
//-------------------------------------------------------<br>
677 
// WATCHDOG: Clock Mux<br>
678 
//-------------------------------------------------------<br>
679 
// When uncommented, this define will enable the<br>
680 
// Watchdog clock MUX allowing the selection between<br>
681 
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.<br>
682 
// When commented out, ACLK is selected if the<br>
683 
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is<br>
684 
// selected otherwise.<br>
685 
//-------------------------------------------------------<br>
686 
`define WATCHDOG_MUX<br>
687 
//`define WATCHDOG_NOMUX_ACLK<br>
688 
      <br>
689 
      </code></td>
690 
    </tr>
691 
  </tbody>
692 
</table>
693 
 
694 
<br>
695 
 
696 
<a name="3_DFT_Considerations"></a><br>
697 
 
698 
<h1><a name="3._DFT_Considerations"></a>3. DFT Considerations</h1>
699 
 
700 
The openMSP430 is designed to be fully scan friendly. During
701 
production, the ATE controls the core through the <span style="font-weight: bold; font-style: italic;">scan_mode</span> and <span style="font-weight: bold; font-style: italic;">scan_enable</span>
702 
signals. The <span style="font-weight: bold; font-style: italic;">scan_mode</span>
703 
port is always asserted during scan testing and is used to switch
704 
between functional and scan mode.<br>
705 
 
706 
<a name="3_1_Resets"></a><br>
707 
 
708 
<h2>3.1 Resets</h2>
709 
 
710 
When in scan mode (i.e. <span style="font-weight: bold; font-style: italic;">scan_mode</span> input
711 
port is set), <span style="font-weight: bold;">ALL</span> internal
712 
resets of the openMSP430 are connected the <span style="font-style: italic; font-weight: bold;">reset_n</span> input
713 
port.<br>
714 
 
715 
Taking the <span style="font-weight: bold; font-style: italic;">POR</span>
716 
generation as an example, it is implemented using the <span style="font-weight: bold;">omsp_scan_mux</span> module as following:<br>
717 
 
718 
<br>
719 
 
720 182 olivier.gi 
<div style="text-align: center;"><img alt="DFT Reset" src="http://opencores.org/usercontent,img,1330808995" width="50%"><br>
721 135 olivier.gi 
</div>
722 
 
723 
<a name="3_2_Clock_Gates"></a>
724 
<h2>3.2 Clock Gates<br>
725 
</h2>
726 
 
727 
When in scan mode (i.e. <span style="font-weight: bold; font-style: italic;">scan_mode</span> input
728 
port is set), <span style="font-weight: bold;">ALL</span> clock gates
729 
instantiated in the design must<span style="font-weight: bold;"> </span>be
730 
enabled during scan shifting.
731 
This is can be achieved by setting the <span style="font-weight: bold; font-style: italic;">scan_enable</span>
732 
input port during the shift phase.<br>
733 
 
734 
On the other hand, during the capture phase, the <span style="font-weight: bold; font-style: italic;">scan_enable</span> port
735 
must be cleared in order to restore the functional behavior of the
736 
clock gate.<br>
737 
 
738 
<br>
739 
 
740 
This feature is implemented in the <span style="font-weight: bold;">omsp_clock_gate</span>
741 
module as following:<br>
742 
 
743 
<br>
744 
 
745 
<div style="text-align: center;"><img alt="DFT Clock Gate" src="http://opencores.org/usercontent,img,1322775594" width="50%"><br>
746 
</div>
747 
 
748 
<a name="3_3_Clock_Muxes"></a>
749 
<h2>3.3 Clock Muxes</h2>
750 
 
751 
When in scan mode (i.e. <span style="font-weight: bold; font-style: italic;">scan_mode</span> input
752 
port is set), the <span style="font-weight: bold; font-style: italic;">MCLK</span>
753 
and <span style="font-weight: bold; font-style: italic;">SMCLK</span>
754 
clock muxes are both running on <span style="font-weight: bold; font-style: italic;">DCO_CLK</span>. The
755 
watchdog mux is running <span style="font-weight: bold; font-style: italic;">SMCLK</span> (i.e.
756 
DCO_CLK).<br>
757 
 
758 
<br>
759 
 
760 
This feature is implemented in the <span style="font-weight: bold;">omsp_clock_mux</span>
761 
module as following:<br>
762 
 
763 
<br>
764 
 
765 
<div style="text-align: center;"><img alt="DFT Clock MUX" src="http://opencores.org/usercontent,img,1322775611" width="50%"><br>
766 
</div>
767 
 
768 
<br>
769 
 
770 
<span style="font-weight: bold; text-decoration: underline;">Note:</span>
771 
if the LFXT clock domain is enabled, the <span style="font-weight: bold; font-style: italic;">LFXT_CLK</span> input
772 
port should also be connected to the scan clock when in scan mode.<br>
773 
 
774 
<a name="3_4_Coverage"></a>
775 
<h2>3.4 Coverage</h2>
776 
 
777 
After synthesizing the openMSP430 in its maximum configuration (in
778 
particular with ALL clock domains available and ALL clock muxes
779 
included), the core reaches <span style="font-weight: bold;">99.7%</span>
780 
stuck-at fault coverage:<br>
781 
 
782 
<br>
783 
 
784 
<div style="text-align: center;"><img alt="Tetramax" src="http://opencores.org/usercontent,img,1331154317" width="50%"><br>
785 
</div>
786 
 
787 
<br>
788 
 
789 
<br>
790 
 
791 
<a name="4_Sensitive_Modules"></a><br>
792 
 
793 
<h1>4. Sensitive Modules</h1>
794 
 
795 
ALL modules discussed in this section have
796 
a simple and well defined functionality but nonetheless lay on
797 
sensitive parts of the design (clock tree, wake-up path, ...).<br>
798 
 
799 
<br>
800 
 
801 
In the industry, it is common place for companies to have policies
802 
recommending designers to use textbook structures or specific
803 
standard cells when implementing circuits considered as 'sensitive'.<br>
804 
 
805 
This section will hopefully help to quickly identify these
806 
'sensitive' circuits and adapt them to your requirements if necessary.<br>
807 
 
808 
<br>
809 
 
810 
<a name="4_1_AND_Gate"></a>
811 
<h2>4.1 AND Gate (<span style="font-style: italic;"> omsp_and_gate.v</span>
812 
)<br>
813 
</h2>
814 
 
815 
This module implements a simple AND2 gate and is instantiated several
816 
times on the wake-up paths in order to ensure a glitch free generation
817 
of the wake-up signals. The idea behind this block is to prevent the
818 
synthesis tool from optimizing the combinatorial wake-up path and
819 
potentially
820 
generate a glitchy logic.<br>
821 
 
822 
<br>
823 
 
824 
There are three different ways to handle this block:<br>
825 
 
826 
<ol>
827 
 
828 
  <li>Do nothing<br>
829 
  </li>
830 
  <li>Modify the RTL by directly instantiating an AND2 cell from the
831 
target library and applying a <span style="font-weight: bold; font-style: italic;">don't touch</span> or <span style="font-weight: bold; font-style: italic;">size only</span>
832 
attribute on it before proceeding to the synthesis compile step<br>
833 
  </li>
834 
  <li>Keep
835 
the RTL unchanged and when running synthesis, first compile this module
836 
separately before going to the top down compile (don't forget the <span style="font-weight: bold; font-style: italic;">don't touch</span> or <span style="font-weight: bold; font-style: italic;">size only</span>
837 
attribute)<br>
838 
  </li>
839 
</ol>
840 
 
841 
Note that the first option is actually acceptable because in low power
842 
mode,
843 
there are no clocks available, which means no glitch... However, in
844 
active mode, the wake-up line could see a lot of glitches, which is
845 
functionally not a problem (since the core is awake anyway) but could
846 
be
847 
considered as not really elegant...<br>
848 
 
849 
<br>
850 
 
851 
<a name="4_2_Clock_Gate"></a>
852 
<h2>4.2 Clock Gate (<span style="font-style: italic;"> omsp_clock_gate.v</span>
853 
)<br>
854 
</h2>
855 
 
856 
Almost every company has a different policy
857 
for handling clock gates. Therefore, this module is probably the most
858 
likely to be modified. <br>
859 
 
860 
<br>
861 
 
862 
So here are the facts:<br>
863 
 
864 
<ul>
865 
 
866 
  <li>There
867 
are only rising edge flip-flop in the design<b><sup><font color="#ff0000">1</font></sup></b><br>
868 
    <span class="Apple-style-span" style="color: rgb(51, 51, 51); font-family: Arial,Verdana,sans-serif; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 18px; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; background-color: rgb(255, 255, 255);"><b style="margin: 0px; padding: 0px;">→</b></span>&nbsp; as a consequence
869 
clock gates can indifferently park the clock high or low without
870 
affecting functionality.<br>
871 
    <br>
872 
  </li>
873 
  <li>The enable signal of ALL clock gates in the openMSP430 are
874 
generated with the rising edge of the clock<br>
875 
    <span class="Apple-style-span" style="color: rgb(51, 51, 51); font-family: Arial,Verdana,sans-serif; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 18px; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; background-color: rgb(255, 255, 255);"><b style="margin: 0px; padding: 0px;">→</b></span>&nbsp; this leaves the
876 
door open for both LATCH and NAND2 based clock gates.<br>
877 
  </li>
878 
</ul>
879 
 
880 
<small style="font-style: italic;"><b><sup><font color="#ff0000">1</font></sup></b><span style="color: red; font-weight: bold;"></span>: beside for the
881 
DCO_ENABLE
882 
and LFXT_ENABLE signals and the clock MUXes. However, these can be
883 
safely ignored</small><br>
884 
 
885 
<br>
886 
 
887 
As a consequence, you can feel free to use:<br>
888 
 
889 
<ul>
890 
 
891 
  <li>A LATCH based clock gate. For example:<br>
892 
    <div style="text-align: center;"><img alt="Clock Gate Latch" src="http://opencores.org/usercontent,img,1328475744" width="50%"><br>
893 
    </div>
894 
  </li>
895 
  <li>Or a NAND2 based clock gate:<br>
896 
  </li>
897 
</ul>
898 
 
899 182 olivier.gi 
<div style="text-align: center;"><img alt="Clock Gate NAND2" src="http://opencores.org/usercontent,img,1328475770" width="30%"><br>
900 135 olivier.gi 
</div>
901 
 
902 
<br>
903 
 
904 
<a name="4_3_Clock_Mux"></a>
905 
<h2>4.3 Clock Mux ( <span style="font-style: italic;">omsp_clock_mux.v</span>
906 
)<br>
907 
</h2>
908 
 
909 
The clock muxes of the openMSP430 are implemented as following:<br>
910 
 
911 
<div style="text-align: center;"><img alt="Clock Mux" src="http://opencores.org/usercontent,img,1330032914" width="70%"><br>
912 
</div>
913 
 
914 
<span style="font-weight: bold; text-decoration: underline;"></span>In
915 
order to make this&nbsp; implementation 100% bullet proof, the RTL
916 
could be modified by manually instantiating the NAND2 and AND2
917 
cells directly from the target library (with the associated <span style="font-weight: bold; font-style: italic;">don't touch</span> or <span style="font-weight: bold; font-style: italic;">size only</span>
918 
attributes of course).<br>
919 
 
920 
However, if you decide to compile this module as it is, the synthesis
921 
tool should normally be smart enough and not mess it up (but PLEASE
922 
PLEASE PLEASE double check manually the resulting
923 
gate netlist).<br>
924 
 
925 
<br>
926 
 
927 
<a name="4_4_Scan_Mux"></a>
928 
<h2>4.4 Scan Mux ( <span style="font-style: italic;">omsp_scan_mux.v</span>
929 
)<br>
930 
</h2>
931 
 
932 
As illustrated in the section <a href="asic_implementation.html#3_1_Resets">3.1</a> , the scan mux cell
933 
allows <span style="font-weight: bold;">ALL</span> internal resets to
934 
be controllable with the <span style="font-style: italic; font-weight: bold;">reset_n</span> input
935 
port in scan mode.<br>
936 
 
937 
In addition, the scan mux is also used by the <span style="font-style: italic;">omsp_wakeup_cell</span> (see section <a href="asic_implementation.html#4_7_Wakeup_Cell">4.7<span style="font-style: italic;"></span></a> below).<br>
938 
 
939 
<br>
940 
 
941 
<a name="4_5_Sync_Cell"></a>
942 
<h2>4.5 Sync Cell ( <span style="font-style: italic;">omsp_sync_cell.v</span>
943 
)<br>
944 
</h2>
945 
 
946 
The following synchronization cell is instantiated on all clock domain
947 
crossing data paths:
948 
<br>
949 
 
950 
<br>
951 
 
952 
<div style="text-align: center;"><img alt="Sync Cell" src="http://opencores.org/usercontent,img,1330809519" width="40%"><br>
953 
</div>
954 
 
955 
<a name="4_6_Sync_Reset"></a>
956 
<h2>4.6 Sync Reset ( <span style="font-style: italic;">omsp_sync_reset.v</span>
957 
)<br>
958 
</h2>
959 
 
960 
Internal resets are generated using the following standard reset
961 
synchronizer:<br>
962 
 
963 
<div style="text-align: center;"><img alt="Sync Reset" src="http://opencores.org/usercontent,img,1330809533" width="40%"><br>
964 
</div>
965 
 
966 
<br>
967 
 
968 
<a name="4_7_Wakeup_Cell"></a>
969 
<h2>4.7 Wakeup Cell ( <span style="font-style: italic;">omsp_wakeup_cell.v</span>
970 
)<br>
971 
</h2>
972 
 
973 
The wakeup cell is the most unconventional module of the
974 
openMSP430 design as it contains a flip-flop whose clock and reset are
975 
both coming from a data path.<br>
976 
 
977 
In the openMSP430 core, it is instantiated a single time in the
978 
watchdog
979 
timer but can also be reused in external custom peripherals.<br>
980 
 
981 
<br>
982 
 
983 
The implementation of the block looks as following:<br>
984 
 
985 
<div style="text-align: center;"><img alt="Wakeup cell" src="http://opencores.org/usercontent,img,1331155523" width="60%"><br>
986 
</div>
987 
 
988 
<br>
989 
 
990 
The basic idea here is simply to set the WKUP_OUT signal with a
991 
rising edge on the WKUP_EVENT port, and clear it when WKUP_CLEAR is
992 
active (i.e. level sensitive clear).<br>
993 
 
994 
<br>
995 
 
996 
In order to give a better perspective from a system point of view, the
997 
following diagram shows how the wakeup cell has been used in the
998 
particular case of the watchdog timer (note that WDTIFG_CLR_REG and
999 
WDTQN_EDGE_REG are both output of a flip-flop and therefore
1000 
glitch-free):<br>
1001 
 
1002 
<br>
1003 
 
1004 
<div style="text-align: center;"><img alt="Watchdog wakeup" src="http://opencores.org/usercontent,img,1331155543" width="100%"><br>
1005 
</div>
1006 
 
1007 
<h1>
1008 
</h1>
1009 
 
1010 
<span style="font-weight: bold; text-decoration: underline;">Note:</span>
1011 
Wake-up signals can of course be generated in a
1012 
different way as long as they directly come from a flip-flop (or are
1013 
certified to be non-glitchy).<br>
1014 
 
1015 
For example a simple handshake between the WDT_CLK and MCLK clock
1016 
domains could have been used to clear the WDT_WKUP signal in a fully
1017 
synchronous
1018 
manner.<br>
1019 
 
1020 
However, it is to be noted that this handshake would introduce some
1021 
synchronization
1022 
delay, which might not be negligible if MCLK and WDT_CLK frequencies
1023 
are orders of magnitude apart (i.e. several MHz for MCLK and 32kHz
1024 
for WDT_CLK).<br>
1025 
 
1026 
As getting the oscillators back to sleep as fast as possible might
1027 
prove to be extremely important for low-power designs, this
1028 
asynchronous solution was selected for the <span style="font-style: italic; font-weight: bold;">omsp_watchdog</span>
1029 
implementation.<br>
1030 
 
1031 
<br>
1032 
 
1033 
<br>
1034 
 
1035 
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