OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [doc/] [html/] [asic_implementation.html] - Blame information for rev 135

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 olivier.gi 
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
2 
<html><head>
3 
  <title>openMSP430 ASIC Implementation</title>
4 
 
5 
 
6 
 
7 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
8 
 
9 
 
10 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
11 
 
12 
 
13 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
14 
 
15 
 
16 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
17 
 
18 
 
19 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
20 
 
21 
 
22 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
23 
 
24 
 
25 
  <meta http-equiv="content-type" content="text/html; charset=utf-8">
26 
 
27 
</head><body>
28 
<h3>Table of content</h3>
29 
 
30 
<ul>
31 
 
32 
  <li><a href="#1_Introduction">1. Introduction</a></li>
33 
  <li><a href="#2_RTL_Configuration"> 2. RTL Configuration</a>
34 
    <ul>
35 
      <li><a href="#2_1_1_Low_Frequency_Clock_Domain"> 2.1 Basic Clock
36 
Module</a></li>
37 
      <ul>
38 
        <li><a href="#2_1_1_Low_Frequency_Clock_Domain"> 2.1.1
39 
Low-frequency clock domain</a></li>
40 
      </ul>
41 
      <ul>
42 
        <li><a href="#2_1_2_Clock_Muxes"> 2.1.2 Clock muxes</a></li>
43 
      </ul>
44 
      <ul>
45 
        <li><a href="#2_1_3_Clock_Dividers"> 2.1.3 Clock dividers</a></li>
46 
      </ul>
47 
      <ul>
48 
        <li><a href="#2_1_4_Low_Power_Modes">2.1.4 Low-Power modes</a></li>
49 
        <ul>
50 
          <li><a href="#2_1_4_1_Internal_clocks">2.1.4.1 Internal
51 
clocks ( MCLK / SMCLK )</a><br>
52 
          </li>
53 
          <li><a href="#2_1_4_2_Clock_oscillators">2.1.4.2 Clock
54 
oscillators ( DCO_CLK / LFXT_CLK )</a><br>
55 
          </li>
56 
        </ul>
57 
      </ul>
58 
      <li><a href="#2_2_Other_configuration_options">2.2 Other
59 
configuration options</a><br>
60 
      </li>
61 
      <ul>
62 
        <li><a href="#2_2_1_Fine_Grained_Clock_Gating"> 2.2.1 Fine
63 
grained clock gating</a></li>
64 
      </ul>
65 
      <ul>
66 
        <li><a href="#2_2_2_Watchdog_Clock_Mux"> 2.2.2 Watchdog clock
67 
mux</a></li>
68 
      </ul>
69 
    </ul>
70 
  </li>
71 
  <li><a href="#3._DFT_Considerations"> 3. DFT&nbsp; considerations</a></li>
72 
  <ul>
73 
    <li><a href="#3_1_Resets">3.1 Resets</a></li>
74 
    <li><a href="#3_2_Clock_Gates">3.2 Clock Gates</a></li>
75 
    <li><a href="#3_3_Clock_Muxes">3.3 Clock Muxes</a></li>
76 
    <li><a href="#3_4_Coverage">3.4 Coverage</a></li>
77 
  </ul>
78 
  <li><a href="#4_Sensitive_Modules"> 4. Sensitive modules</a><br>
79 
    <ul>
80 
      <li><a href="#4_1_AND_Gate"> 4.1 AND Gate ( <span style="font-style: italic;">omsp_and_gate.v</span> )<br>
81 
        </a></li>
82 
      <li><a href="#4_2_Clock_Gate">4.2 Clock Gate ( <span style="font-style: italic;">omsp_clock_gate.v</span> )</a></li>
83 
      <li><a href="#4_3_Clock_Mux">4.3 Clock Mux ( <span style="font-style: italic;">omsp_clock_mux.v</span> )</a></li>
84 
      <li><a href="#4_4_Scan_Mux">4.4 Scan Mux ( <span style="font-style: italic;">omsp_scan_mux.v</span> )</a></li>
85 
      <li><a href="#4_5_Sync_Cell">4.5 Sync Cell ( <span style="font-style: italic;">omsp_sync_cell.v</span> )</a></li>
86 
      <li><a href="#4_6_Sync_Reset">4.6 Sync Reset ( <span style="font-style: italic;">omsp_sync_reset.v</span> )</a></li>
87 
      <li><a href="#4_7_Wakeup_Cell">4.7 Wakeup Cell
88 
( <span style="font-style: italic;">omsp_wakeup_cell.v</span> )</a></li>
89 
    </ul>
90 
  </li>
91 
</ul>
92 
 
93 
<a name="1_Introduction"></a>
94 
<h1>1. Introduction</h1>
95 
 
96 
This section covers specific points of the openMSP430 ASIC
97 
implementation, in particular:<br>
98 
 
99 
<ul>
100 
 
101 
  <ul>
102 
    <ul>
103 
      <li>The ASIC specific RTL configuration options.</li>
104 
      <li>Some DFT
105 
considerations.</li>
106 
      <li>A description of each ASIC sensitive module.<br>
107 
      </li>
108 
    </ul>
109 
  </ul>
110 
</ul>
111 
 
112 
Keep in mind that as no exotic design technique were used in the
113 
openMSP430,
114 
following a standard implementation flow from
115 
Synthesis to P&amp;R is the best way to go.<br>
116 
 
117 
&nbsp;<br>
118 
 
119 
<br>
120 
 
121 
<a name="2_RTL_Configuration"></a>
122 
<h1>2. RTL Configuration</h1>
123 
 
124 
Whenever the "<span style="font-weight: bold; font-style: italic;">`define
125 
ASIC</span>" statement of the <a style="font-style: italic;" href="http://opencores.org/project,openmsp430,core#2.1.3.3%20Expert%20System%20Configuration">Expert
126 
System Configuration</a> section is uncommented, all ASIC specific
127 
configuration options are enabled. <br>
128 
 
129 
<a name="2_1_Basic_Clock_Module"></a>
130 
<h2>2.1 Basic Clock Module</h2>
131 
 
132 
In its ASIC configuration, the Basic clock module of the openMSP430 can
133 
support <span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space">&nbsp;</span>up to all features
134 
described
135 
in the<span class="Apple-converted-space">&nbsp;</span><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's
136 
Guide</a><span class="Apple-converted-space">&nbsp;</span>(Chapter 4).<br>
137 
All these options are highlighted in the following diagram and
138 
discussed below:<br>
139 
<br>
140 
</span>
141 
<div style="text-align: center;"><img alt="Clock Module ASIC configuration" src="http://opencores.org/usercontent,img,1321995017" width="80%"><br>
142 
</div>
143 
 
144 
<a name="2_1_1_Low_Frequency_Clock_Domain"></a>
145 
<h3>2.1.1 Low-Frequency Clock Domain</h3>
146 
 
147 
The LFXT clock domain can be enabled thanks to the following
148 
configuration
149 
option:<br>
150 
 
151 
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span></span><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span></span><span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;"><span class="Apple-converted-space"> </span></span><br>
152 
 
153 
<table border="0" cellpadding="0" cellspacing="4">
154 
 
155 
  <tbody>
156 
    <tr>
157 
      <td width="35"><br>
158 
      </td>
159 
      <td bgcolor="#d0d0d0" width="3"><br>
160 
      </td>
161 
      <td width="15"><br>
162 
      </td>
163 
      <td> <code>//============================================================================<br>
164 
// LFXT CLOCK DOMAIN<br>
165 
//============================================================================<br>
166 
      <br>
167 
//-------------------------------------------------------<br>
168 
// When uncommented, this define will enable the lfxt_clk<br>
169 
// clock domain.<br>
170 
// When commented out, the whole chip is clocked with dco_clk.<br>
171 
//-------------------------------------------------------<br>
172 
`define LFXT_DOMAIN<br>
173 
      <br>
174 
      </code></td>
175 
    </tr>
176 
  </tbody>
177 
</table>
178 
 
179 
<br>
180 
 
181 
<span style="font-style: italic; font-weight: bold; text-decoration: underline;">Note
182 
1:</span> When commented-out:<br>
183 
 
184 
<ul>
185 
 
186 
  <ul>
187 
    <ul>
188 
      <li><span style="font-style: italic;">ACLK</span> is running on <span style="font-style: italic;">DCO_CLK</span></li>
189 
      <li>MCLK_MUX and SMCLK_MUX options are not supported</li>
190 
      <li>OSCOFF_EN low power mode is not supported<span style="font-style: italic;"><br>
191 
        </span></li>
192 
    </ul>
193 
  </ul>
194 
</ul>
195 
 
196 
<span style="font-weight: bold; font-style: italic; text-decoration: underline;">Note
197 
2:</span> Unlike its name suggest, there is no frequency limitation on <span style="font-style: italic;">LFXT_CLK</span>. The name was simply kept
198 
in order to be consistent with the original MSP430 documentation, where
199 
<span style="font-style: italic;">LFXT_CLK</span> is
200 
typically connected to a 32 kHz crystal oscillator.<br>
201 
 
202 
<br>
203 
 
204 
<a name="2_1_2_Clock_Muxes"></a><br>
205 
 
206 
<h3>2.1.2 Clock Muxes</h3>
207 
 
208 
The <span style="font-style: italic;">MCLK</span> and <span style="font-style: italic;">SMCLK</span> clock muxes can be enabled or
209 
disabled with the following options:<br>
210 
 
211 
<br>
212 
 
213 
<table border="0" cellpadding="0" cellspacing="4">
214 
 
215 
  <tbody>
216 
    <tr>
217 
      <td width="35"><br>
218 
      </td>
219 
      <td bgcolor="#d0d0d0" width="3"><br>
220 
      </td>
221 
      <td width="15"><br>
222 
      </td>
223 
      <td> <code>//============================================================================<br>
224 
// CLOCK MUXES<br>
225 
//============================================================================<br>
226 
      <br>
227 
//-------------------------------------------------------<br>
228 
// MCLK: Clock Mux<br>
229 
//-------------------------------------------------------<br>
230 
// When uncommented, this define will enable the<br>
231 
// MCLK clock MUX allowing the selection between<br>
232 
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.<br>
233 
// When commented, DCO_CLK is selected.<br>
234 
//-------------------------------------------------------<br>
235 
`define MCLK_MUX<br>
236 
      <br>
237 
//-------------------------------------------------------<br>
238 
// SMCLK: Clock Mux<br>
239 
//-------------------------------------------------------<br>
240 
// When uncommented, this define will enable the<br>
241 
// SMCLK clock MUX allowing the selection between<br>
242 
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.<br>
243 
// When commented, DCO_CLK is selected.<br>
244 
//-------------------------------------------------------<br>
245 
`define SMCLK_MUX<br>
246 
      <br>
247 
      </code></td>
248 
    </tr>
249 
  </tbody>
250 
</table>
251 
 
252 
<br>
253 
 
254 
<span style="font-style: italic; font-weight: bold; text-decoration: underline;">Note
255 
1:</span> When a MUX is excluded, the concerned clock (<span style="font-style: italic;">MCLK</span> and/or <span style="font-style: italic;">SMCLK) is</span> running with <span style="font-style: italic;">DCO_CLK</span>.<br>
256 
 
257 
<br>
258 
 
259 
<span style="font-weight: bold; font-style: italic; text-decoration: underline;">Note
260 
2:</span> If a MUX is included, the implementation and sign-off tools
261 
(in particular CTS and STA) must be aware
262 
that a new clock needs to be defined on the MUX output.<br>
263 
 
264 
<br>
265 
 
266 
<br>
267 
 
268 
<a name="2_1_3_Clock_Dividers"></a>
269 
<h3>2.1.3 Clock Dividers</h3>
270 
 
271 
The <span style="font-style: italic;">MCLK</span>, <span style="font-style: italic;">SMCLK</span> and ACLK clock dividers can
272 
be enabled or disabled with the following options:<br>
273 
 
274 
<br>
275 
 
276 
<table border="0" cellpadding="0" cellspacing="4">
277 
 
278 
  <tbody>
279 
    <tr>
280 
      <td width="35"><br>
281 
      </td>
282 
      <td bgcolor="#d0d0d0" width="3"><br>
283 
      </td>
284 
      <td width="15"><br>
285 
      </td>
286 
      <td> <code>//============================================================================<br>
287 
// CLOCK DIVIDERS<br>
288 
//============================================================================<br>
289 
      <br>
290 
//-------------------------------------------------------<br>
291 
// MCLK: Clock divider<br>
292 
//-------------------------------------------------------<br>
293 
// When uncommented, this define will enable the<br>
294 
// MCLK clock divider (/1/2/4/8)<br>
295 
//-------------------------------------------------------<br>
296 
`define MCLK_DIVIDER<br>
297 
      <br>
298 
//-------------------------------------------------------<br>
299 
// SMCLK: Clock divider (/1/2/4/8)<br>
300 
//-------------------------------------------------------<br>
301 
// When uncommented, this define will enable the<br>
302 
// SMCLK clock divider<br>
303 
//-------------------------------------------------------<br>
304 
`define SMCLK_DIVIDER<br>
305 
      <br>
306 
//-------------------------------------------------------<br>
307 
// ACLK: Clock divider (/1/2/4/8)<br>
308 
//-------------------------------------------------------<br>
309 
// When uncommented, this define will enable the<br>
310 
// ACLK clock divider<br>
311 
//-------------------------------------------------------<br>
312 
`define ACLK_DIVIDER<br>
313 
      <br>
314 
      </code></td>
315 
    </tr>
316 
  </tbody>
317 
</table>
318 
 
319 
<br>
320 
 
321 
The clock dividers instantiate a clock gate on the clock tree and are
322 
implemented as following:<br>
323 
 
324 
<br>
325 
 
326 
<div style="text-align: center;"><img alt="Clock Divider" src="http://opencores.org/usercontent,img,1322310000"  width="50%"><br>
327 
</div>
328 
 
329 
<br>
330 
 
331 
<a name="2_1_4_Low_Power_Modes"></a>
332 
<h3>2.1.4 Low-Power Modes</h3>
333 
 
334 
<a name="2_1_4_1_Internal_clocks"><br>
335 
</a><span style="font-weight: bold;">2.1.4.1 Internal clocks ( MCLK /
336 
SMCLK )</span><br>
337 
 
338 
<br>
339 
 
340 
Two bit fields in the status register (R2) allow to
341 
control the system clocks:<br>
342 
 
343 
<ul>
344 
 
345 
  <ul>
346 
    <ul>
347 
      <li><span style="font-weight: bold;">CPUOFF</span> allows to
348 
switch-off <span style="font-style: italic;">MCLK</span></li>
349 
      <li><span style="font-weight: bold;">SCG1</span> allows to
350 
switch-off <span style="font-style: italic;">SMCLK</span><br>
351 
      </li>
352 
    </ul>
353 
  </ul>
354 
</ul>
355 
 
356 
These control bits are supported by the openMSP430 and can be
357 
included in the design with the following defines:<br>
358 
 
359 
<br>
360 
 
361 
<table border="0" cellpadding="0" cellspacing="4">
362 
 
363 
  <tbody>
364 
    <tr>
365 
      <td width="35"><br>
366 
      </td>
367 
      <td bgcolor="#d0d0d0" width="3"><br>
368 
      </td>
369 
      <td width="15"><br>
370 
      </td>
371 
      <td><code>//============================================================================<br>
372 
// LOW POWER MODES<br>
373 
//============================================================================<br>
374 
      <br>
375 
//-------------------------------------------------------<br>
376 
// LOW POWER MODE: CPUOFF<br>
377 
//-------------------------------------------------------<br>
378 
// When uncommented, this define will include the<br>
379 
// clock gate allowing to switch off MCLK in<br>
380 
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4<br>
381 
//-------------------------------------------------------<br>
382 
`define CPUOFF_EN<br>
383 
      <br>
384 
//-------------------------------------------------------<br>
385 
// LOW POWER MODE: SCG1<br>
386 
//-------------------------------------------------------<br>
387 
// When uncommented, this define will include the<br>
388 
// clock gate allowing to switch off SMCLK in<br>
389 
// the following low power modes: LPM2, LPM3, LPM4<br>
390 
//-------------------------------------------------------<br>
391 
`define SCG1_EN<br>
392 
      <br>
393 
      </code></td>
394 
    </tr>
395 
  </tbody>
396 
</table>
397 
 
398 
<br>
399 
 
400 
In order to keep the clock tree as flat as possible, the CPUOFF and
401 
SCG1 low power options share the same clock gate with the clock divider:<br>
402 
 
403 
<br>
404 
 
405 
<div style="text-align: center;"><img alt="Clock Divider and low power" src="http://opencores.org/usercontent,img,1322310023" width="50%"><br>
406 
</div>
407 
 
408 
<a name="2_1_4_2_Clock_oscillators"><br>
409 
</a><span style="font-weight: bold;">2.1.4.2 Clock oscillators (
410 
DCO_CLK / LFXT_CLK )</span><br>
411 
 
412 
<br>
413 
 
414 
There are two bit fields in the status register (R2) allowing to
415 
control the clock oscillators:<br>
416 
 
417 
<ul>
418 
 
419 
  <ul>
420 
    <ul>
421 
      <li><span style="font-weight: bold;">SCG0</span> allows to
422 
switch-off the DCO oscillator<span style="font-style: italic;"></span></li>
423 
      <li><span style="font-weight: bold;">OSCOFF</span> allows to
424 
switch-off the LFXT oscillator<span style="font-style: italic;"></span><br>
425 
      </li>
426 
    </ul>
427 
  </ul>
428 
</ul>
429 
 
430 
These control bits are supported by the openMSP430 and can be
431 
included in the design with the following defines:<br>
432 
 
433 
<br>
434 
 
435 
<table border="0" cellpadding="0" cellspacing="4">
436 
 
437 
  <tbody>
438 
    <tr>
439 
      <td width="35"><br>
440 
      </td>
441 
      <td bgcolor="#d0d0d0" width="3"><br>
442 
      </td>
443 
      <td width="15"><br>
444 
      </td>
445 
      <td><code>//============================================================================<br>
446 
// LOW POWER MODES<br>
447 
//============================================================================<br>
448 
      <br>
449 
//-------------------------------------------------------<br>
450 
// LOW POWER MODE: SCG0<br>
451 
//-------------------------------------------------------<br>
452 
// When uncommented, this define will enable the<br>
453 
// DCO_ENABLE/WKUP port control (always 1 when commented).<br>
454 
// This allows to switch off the DCO oscillator in the<br>
455 
// following low power modes: LPM1, LPM3, LPM4<br>
456 
//-------------------------------------------------------<br>
457 
`define SCG0_EN<br>
458 
      <br>
459 
//-------------------------------------------------------<br>
460 
// LOW POWER MODE: OSCOFF<br>
461 
//-------------------------------------------------------<br>
462 
// When uncommented, this define will include the<br>
463 
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP<br>
464 
// port control (always 1 when commented).<br>
465 
// This allows to switch off the low frequency oscillator<br>
466 
// in the following low power modes: LPM4<br>
467 
//-------------------------------------------------------<br>
468 
`define OSCOFF_EN<br>
469 
      <br>
470 
      </code></td>
471 
    </tr>
472 
  </tbody>
473 
</table>
474 
 
475 
<br>
476 
 
477 
The control logic of both DCO and LFXT oscillators is identical.<br>
478 
 
479 
<br>
480 
 
481 
When disabled, the <span style="font-weight: bold;">*_WKUP</span>
482 
signal
483 
is used to asynchronously wake up the oscillator. Once the oscillator
484 
is awake (and therefore a clock is available), the <span style="font-weight: bold;">*_ENABLE</span> signal will take over and
485 
synchronously keep the oscillator enabled until the CPU clears the SCG0
486 
or OSCOFF bit again.<br>
487 
 
488 
<br>
489 
 
490 
The following two waveforms illustrate the CPU entering the LPM1 mode,
491 
and in particular the DCO oscillator being switched-off:<br>
492 
 
493 
<ul>
494 
 
495 
  <li>Entering LPM1 through a <span style="font-weight: bold; font-style: italic; color: rgb(51, 51, 153);">BIS
496 
#N, R2</span>
497 
instruction:</li>
498 
</ul>
499 
 
500 
<img alt="Entering LPM1 with BIS" src="http://opencores.org/usercontent,img,1322600748"  width="100%"><br>
501 
 
502 
<ul>
503 
 
504 
  <li>Entering LPM1 through a <span style="font-weight: bold; font-style: italic; color: rgb(51, 51, 153);">RETI</span>
505 
instruction:<br>
506 
  </li>
507 
</ul>
508 
 
509 
<img alt="Entering LPM1 with RETI" src="http://opencores.org/usercontent,img,1322600763" width="100%"><br>
510 
 
511 
<br>
512 
 
513 
<span style="font-weight: bold; text-decoration: underline;">Note:</span>
514 
the DCO oscillator is enabled until the BIS and RETI instruction are
515 
fully executed (i.e. until the CPU state machines reach their IDLE
516 
state).<br>
517 
 
518 
<br>
519 
 
520 
<br>
521 
 
522 
At last, this waveform shows the CPU going out of LPM1 mode and in
523 
particular the DCO oscillator wake-up sequence:<br>
524 
 
525 
<br>
526 
 
527 
<img alt="Wakeup from LPM1" src="http://opencores.org/usercontent,img,1322602185"  width="100%"><br>
528 
 
529 
<br>
530 
 
531 
In order to wake-up the CPU from ANY low power mode, the system <span style="font-weight: bold;">MUST ALWAYS</span> go through the following
532 
chain of events (as illustrated in the previous waveform):<br>
533 
 
534 
<ul>
535 
 
536 
  <ul>
537 
    <ol>
538 
      <li style="color: red;">&nbsp;<span style="color: black;">The
539 
peripheral (for example a timer) asserts the </span><span style="font-weight: bold; font-style: italic; color: black;">WKUP</span><span style="color: black;"> input of the openMSP430 in order to
540 
asynchronously restore the clocks. At this stage, </span><span style="font-weight: bold; font-style: italic; color: black;">DCO_WKUP</span><span style="color: black;"> is activated and </span><span style="font-weight: bold; font-style: italic; color: black;">DCO_ENABLE</span><span style="color: black;"> is still cleared.</span></li>
541 
      <li style="color: red;">&nbsp;<span style="color: black;">Once
542 
MCLK is available, the peripheral generates a synchronous IRQ signal in
543 
order to re-activate the CPU state machines.</span></li>
544 
      <li style="color: red;">&nbsp;<span style="color: black;">The CPU
545 
state machines activated, </span><span style="font-weight: bold; font-style: italic; color: black;">DCO_ENABLE</span><span style="color: black;"> is synchronously set.</span><br>
546 
      </li>
547 
      <li style="color: red;">&nbsp;<span style="color: black;">When
548 
the global interrupt enable flag (GIE) is cleared, <span style="font-weight: bold; font-style: italic;">DCO_WKUP</span> is
549 
released two clock cycles later (i.e. same behavior as a reset
550 
synchronizer).<br>
551 
        <span style="font-weight: bold; text-decoration: underline;">Important
552 
note:</span> the peripheral should release the </span><span style="font-weight: bold; font-style: italic; color: black;">WKUP</span><span style="color: black;"> input when its interrupt pending flag is cleared</span><span style="font-weight: bold; font-style: italic; color: black;"></span><span style="color: black;">. Otherwise the <span style="font-weight: bold; font-style: italic;">DCO_WKUP</span> signal
553 
will be set again as soon as the GIE flag is restored by the RETI
554 
instruction... which is probably not the intended behavior :-P<br>
555 
        </span></li>
556 
      <li style="color: red;"><span style="color: black;">The DCO
557 
oscillator is now enabled until SCG0 is set again.</span><br>
558 
      </li>
559 
    </ol>
560 
  </ul>
561 
</ul>
562 
 
563 
<br>
564 
 
565 
<a name="2_2_Other_configuration_options"></a>
566 
<h2>2.2 Other configuration options</h2>
567 
 
568 
<a name="2_2_1_Fine_Grained_Clock_Gating"></a>
569 
<h3>2.2.1 Fine Grained Clock Gating</h3>
570 
 
571 
Nowadays, all synthesis tools support automatic (fine grained) clock
572 
gating insertion.<br>
573 
 
574 
However, as some design houses still prefer to have the clock gates
575 
directly instantiated in the RTL, there is the possibility to include
576 
the <span style="font-style: italic;">'manual</span>' fine grained
577 
clock gates in the design with the following define:<br>
578 
 
579 
<br>
580 
 
581 
<table border="0" cellpadding="0" cellspacing="4">
582 
 
583 
  <tbody>
584 
    <tr>
585 
      <td width="35"><br>
586 
      </td>
587 
      <td bgcolor="#d0d0d0" width="3"><br>
588 
      </td>
589 
      <td width="15"><br>
590 
      </td>
591 
      <td><code>//============================================================================<br>
592 
// FINE GRAINED CLOCK GATING<br>
593 
//============================================================================<br>
594 
      <br>
595 
//-------------------------------------------------------<br>
596 
// When uncommented, this define will enable the fine<br>
597 
// grained clock gating of all registers in the core.<br>
598 
//-------------------------------------------------------<br>
599 
`define CLOCK_GATING<br>
600 
      <br>
601 
      </code></td>
602 
    </tr>
603 
  </tbody>
604 
</table>
605 
 
606 
<br>
607 
 
608 
<br>
609 
 
610 
<a name="2_2_2_Watchdog_Clock_Mux"></a>
611 
<h3>2.2.2 Watchdog Clock Mux</h3>
612 
 
613 
<span class="Apple-style-span" style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium;">The
614 
watchdog clock <span class="Apple-converted-space"><span style="font-style: italic;"></span></span><span style="font-style: italic;"></span><span class="Apple-converted-space"></span><span class="Apple-converted-space"></span><span style="font-style: italic;"></span><span class="Apple-converted-space"></span>mux allows to select between <span style="font-style: italic;">ACLK</span> and <span style="font-style: italic;">SMCLK</span>. It can be enabled or
615 
disabled with the <span style="font-weight: bold;">WATCHDOG_MUX</span>
616 
define.<br>
617 
</span>When excluded, the additional <span style="font-weight: bold;">WATCHDOG_NOMUX_ACLK</span>&nbsp;
618 
option allows the user to decide if the watchdog clock should be
619 
hard-wired to <span style="font-style: italic;">ACLK</span> (if
620 
uncommented) or <span style="font-style: italic;">SMCLK</span> (if
621 
commented-out)<br>
622 
 
623 
<br>
624 
 
625 
<table border="0" cellpadding="0" cellspacing="4">
626 
 
627 
  <tbody>
628 
    <tr>
629 
      <td width="35"><br>
630 
      </td>
631 
      <td bgcolor="#d0d0d0" width="3"><br>
632 
      </td>
633 
      <td width="15"><br>
634 
      </td>
635 
      <td> <code>//============================================================================<br>
636 
// CLOCK MUXES<br>
637 
//============================================================================<br>
638 
      <br>
639 
//-------------------------------------------------------<br>
640 
// WATCHDOG: Clock Mux<br>
641 
//-------------------------------------------------------<br>
642 
// When uncommented, this define will enable the<br>
643 
// Watchdog clock MUX allowing the selection between<br>
644 
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.<br>
645 
// When commented out, ACLK is selected if the<br>
646 
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is<br>
647 
// selected otherwise.<br>
648 
//-------------------------------------------------------<br>
649 
`define WATCHDOG_MUX<br>
650 
//`define WATCHDOG_NOMUX_ACLK<br>
651 
      <br>
652 
      </code></td>
653 
    </tr>
654 
  </tbody>
655 
</table>
656 
 
657 
<br>
658 
 
659 
<a name="3_DFT_Considerations"></a><br>
660 
 
661 
<h1><a name="3._DFT_Considerations"></a>3. DFT Considerations</h1>
662 
 
663 
The openMSP430 is designed to be fully scan friendly. During
664 
production, the ATE controls the core through the <span style="font-weight: bold; font-style: italic;">scan_mode</span> and <span style="font-weight: bold; font-style: italic;">scan_enable</span>
665 
signals. The <span style="font-weight: bold; font-style: italic;">scan_mode</span>
666 
port is always asserted during scan testing and is used to switch
667 
between functional and scan mode.<br>
668 
 
669 
<a name="3_1_Resets"></a><br>
670 
 
671 
<h2>3.1 Resets</h2>
672 
 
673 
When in scan mode (i.e. <span style="font-weight: bold; font-style: italic;">scan_mode</span> input
674 
port is set), <span style="font-weight: bold;">ALL</span> internal
675 
resets of the openMSP430 are connected the <span style="font-style: italic; font-weight: bold;">reset_n</span> input
676 
port.<br>
677 
 
678 
Taking the <span style="font-weight: bold; font-style: italic;">POR</span>
679 
generation as an example, it is implemented using the <span style="font-weight: bold;">omsp_scan_mux</span> module as following:<br>
680 
 
681 
<br>
682 
 
683 
<div style="text-align: center;"><img alt="DFT Reset" src="http://opencores.org/usercontent,img,1330808995"  width="50%"><br>
684 
</div>
685 
 
686 
<a name="3_2_Clock_Gates"></a>
687 
<h2>3.2 Clock Gates<br>
688 
</h2>
689 
 
690 
When in scan mode (i.e. <span style="font-weight: bold; font-style: italic;">scan_mode</span> input
691 
port is set), <span style="font-weight: bold;">ALL</span> clock gates
692 
instantiated in the design must<span style="font-weight: bold;"> </span>be
693 
enabled during scan shifting.
694 
This is can be achieved by setting the <span style="font-weight: bold; font-style: italic;">scan_enable</span>
695 
input port during the shift phase.<br>
696 
 
697 
On the other hand, during the capture phase, the <span style="font-weight: bold; font-style: italic;">scan_enable</span> port
698 
must be cleared in order to restore the functional behavior of the
699 
clock gate.<br>
700 
 
701 
<br>
702 
 
703 
This feature is implemented in the <span style="font-weight: bold;">omsp_clock_gate</span>
704 
module as following:<br>
705 
 
706 
<br>
707 
 
708 
<div style="text-align: center;"><img alt="DFT Clock Gate" src="http://opencores.org/usercontent,img,1322775594" width="50%"><br>
709 
</div>
710 
 
711 
<a name="3_3_Clock_Muxes"></a>
712 
<h2>3.3 Clock Muxes</h2>
713 
 
714 
When in scan mode (i.e. <span style="font-weight: bold; font-style: italic;">scan_mode</span> input
715 
port is set), the <span style="font-weight: bold; font-style: italic;">MCLK</span>
716 
and <span style="font-weight: bold; font-style: italic;">SMCLK</span>
717 
clock muxes are both running on <span style="font-weight: bold; font-style: italic;">DCO_CLK</span>. The
718 
watchdog mux is running <span style="font-weight: bold; font-style: italic;">SMCLK</span> (i.e.
719 
DCO_CLK).<br>
720 
 
721 
<br>
722 
 
723 
This feature is implemented in the <span style="font-weight: bold;">omsp_clock_mux</span>
724 
module as following:<br>
725 
 
726 
<br>
727 
 
728 
<div style="text-align: center;"><img alt="DFT Clock MUX" src="http://opencores.org/usercontent,img,1322775611" width="50%"><br>
729 
</div>
730 
 
731 
<br>
732 
 
733 
<span style="font-weight: bold; text-decoration: underline;">Note:</span>
734 
if the LFXT clock domain is enabled, the <span style="font-weight: bold; font-style: italic;">LFXT_CLK</span> input
735 
port should also be connected to the scan clock when in scan mode.<br>
736 
 
737 
<a name="3_4_Coverage"></a>
738 
<h2>3.4 Coverage</h2>
739 
 
740 
After synthesizing the openMSP430 in its maximum configuration (in
741 
particular with ALL clock domains available and ALL clock muxes
742 
included), the core reaches <span style="font-weight: bold;">99.7%</span>
743 
stuck-at fault coverage:<br>
744 
 
745 
<br>
746 
 
747 
<div style="text-align: center;"><img alt="Tetramax" src="http://opencores.org/usercontent,img,1331154317" width="50%"><br>
748 
</div>
749 
 
750 
<br>
751 
 
752 
<br>
753 
 
754 
<a name="4_Sensitive_Modules"></a><br>
755 
 
756 
<h1>4. Sensitive Modules</h1>
757 
 
758 
ALL modules discussed in this section have
759 
a simple and well defined functionality but nonetheless lay on
760 
sensitive parts of the design (clock tree, wake-up path, ...).<br>
761 
 
762 
<br>
763 
 
764 
In the industry, it is common place for companies to have policies
765 
recommending designers to use textbook structures or specific
766 
standard cells when implementing circuits considered as 'sensitive'.<br>
767 
 
768 
This section will hopefully help to quickly identify these
769 
'sensitive' circuits and adapt them to your requirements if necessary.<br>
770 
 
771 
<br>
772 
 
773 
<a name="4_1_AND_Gate"></a>
774 
<h2>4.1 AND Gate (<span style="font-style: italic;"> omsp_and_gate.v</span>
775 
)<br>
776 
</h2>
777 
 
778 
This module implements a simple AND2 gate and is instantiated several
779 
times on the wake-up paths in order to ensure a glitch free generation
780 
of the wake-up signals. The idea behind this block is to prevent the
781 
synthesis tool from optimizing the combinatorial wake-up path and
782 
potentially
783 
generate a glitchy logic.<br>
784 
 
785 
<br>
786 
 
787 
There are three different ways to handle this block:<br>
788 
 
789 
<ol>
790 
 
791 
  <li>Do nothing<br>
792 
  </li>
793 
  <li>Modify the RTL by directly instantiating an AND2 cell from the
794 
target library and applying a <span style="font-weight: bold; font-style: italic;">don't touch</span> or <span style="font-weight: bold; font-style: italic;">size only</span>
795 
attribute on it before proceeding to the synthesis compile step<br>
796 
  </li>
797 
  <li>Keep
798 
the RTL unchanged and when running synthesis, first compile this module
799 
separately before going to the top down compile (don't forget the <span style="font-weight: bold; font-style: italic;">don't touch</span> or <span style="font-weight: bold; font-style: italic;">size only</span>
800 
attribute)<br>
801 
  </li>
802 
</ol>
803 
 
804 
Note that the first option is actually acceptable because in low power
805 
mode,
806 
there are no clocks available, which means no glitch... However, in
807 
active mode, the wake-up line could see a lot of glitches, which is
808 
functionally not a problem (since the core is awake anyway) but could
809 
be
810 
considered as not really elegant...<br>
811 
 
812 
<br>
813 
 
814 
<a name="4_2_Clock_Gate"></a>
815 
<h2>4.2 Clock Gate (<span style="font-style: italic;"> omsp_clock_gate.v</span>
816 
)<br>
817 
</h2>
818 
 
819 
Almost every company has a different policy
820 
for handling clock gates. Therefore, this module is probably the most
821 
likely to be modified. <br>
822 
 
823 
<br>
824 
 
825 
So here are the facts:<br>
826 
 
827 
<ul>
828 
 
829 
  <li>There
830 
are only rising edge flip-flop in the design<b><sup><font color="#ff0000">1</font></sup></b><br>
831 
    <span class="Apple-style-span" style="color: rgb(51, 51, 51); font-family: Arial,Verdana,sans-serif; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 18px; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; background-color: rgb(255, 255, 255);"><b style="margin: 0px; padding: 0px;">→</b></span>&nbsp; as a consequence
832 
clock gates can indifferently park the clock high or low without
833 
affecting functionality.<br>
834 
    <br>
835 
  </li>
836 
  <li>The enable signal of ALL clock gates in the openMSP430 are
837 
generated with the rising edge of the clock<br>
838 
    <span class="Apple-style-span" style="color: rgb(51, 51, 51); font-family: Arial,Verdana,sans-serif; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 18px; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; background-color: rgb(255, 255, 255);"><b style="margin: 0px; padding: 0px;">→</b></span>&nbsp; this leaves the
839 
door open for both LATCH and NAND2 based clock gates.<br>
840 
  </li>
841 
</ul>
842 
 
843 
<small style="font-style: italic;"><b><sup><font color="#ff0000">1</font></sup></b><span style="color: red; font-weight: bold;"></span>: beside for the
844 
DCO_ENABLE
845 
and LFXT_ENABLE signals and the clock MUXes. However, these can be
846 
safely ignored</small><br>
847 
 
848 
<br>
849 
 
850 
As a consequence, you can feel free to use:<br>
851 
 
852 
<ul>
853 
 
854 
  <li>A LATCH based clock gate. For example:<br>
855 
    <div style="text-align: center;"><img alt="Clock Gate Latch" src="http://opencores.org/usercontent,img,1328475744" width="50%"><br>
856 
    </div>
857 
  </li>
858 
  <li>Or a NAND2 based clock gate:<br>
859 
  </li>
860 
</ul>
861 
 
862 
<div style="text-align: center;"><img alt="Clock Gate NAND2" src="http://opencores.org/usercontent,img,1328475770"  width="30%"><br>
863 
</div>
864 
 
865 
<br>
866 
 
867 
<a name="4_3_Clock_Mux"></a>
868 
<h2>4.3 Clock Mux ( <span style="font-style: italic;">omsp_clock_mux.v</span>
869 
)<br>
870 
</h2>
871 
 
872 
The clock muxes of the openMSP430 are implemented as following:<br>
873 
 
874 
<div style="text-align: center;"><img alt="Clock Mux" src="http://opencores.org/usercontent,img,1330032914" width="70%"><br>
875 
</div>
876 
 
877 
<span style="font-weight: bold; text-decoration: underline;"></span>In
878 
order to make this&nbsp; implementation 100% bullet proof, the RTL
879 
could be modified by manually instantiating the NAND2 and AND2
880 
cells directly from the target library (with the associated <span style="font-weight: bold; font-style: italic;">don't touch</span> or <span style="font-weight: bold; font-style: italic;">size only</span>
881 
attributes of course).<br>
882 
 
883 
However, if you decide to compile this module as it is, the synthesis
884 
tool should normally be smart enough and not mess it up (but PLEASE
885 
PLEASE PLEASE double check manually the resulting
886 
gate netlist).<br>
887 
 
888 
<br>
889 
 
890 
<a name="4_4_Scan_Mux"></a>
891 
<h2>4.4 Scan Mux ( <span style="font-style: italic;">omsp_scan_mux.v</span>
892 
)<br>
893 
</h2>
894 
 
895 
As illustrated in the section <a href="asic_implementation.html#3_1_Resets">3.1</a> , the scan mux cell
896 
allows <span style="font-weight: bold;">ALL</span> internal resets to
897 
be controllable with the <span style="font-style: italic; font-weight: bold;">reset_n</span> input
898 
port in scan mode.<br>
899 
 
900 
In addition, the scan mux is also used by the <span style="font-style: italic;">omsp_wakeup_cell</span> (see section <a href="asic_implementation.html#4_7_Wakeup_Cell">4.7<span style="font-style: italic;"></span></a> below).<br>
901 
 
902 
<br>
903 
 
904 
<a name="4_5_Sync_Cell"></a>
905 
<h2>4.5 Sync Cell ( <span style="font-style: italic;">omsp_sync_cell.v</span>
906 
)<br>
907 
</h2>
908 
 
909 
The following synchronization cell is instantiated on all clock domain
910 
crossing data paths:
911 
<br>
912 
 
913 
<br>
914 
 
915 
<div style="text-align: center;"><img alt="Sync Cell" src="http://opencores.org/usercontent,img,1330809519" width="40%"><br>
916 
</div>
917 
 
918 
<a name="4_6_Sync_Reset"></a>
919 
<h2>4.6 Sync Reset ( <span style="font-style: italic;">omsp_sync_reset.v</span>
920 
)<br>
921 
</h2>
922 
 
923 
Internal resets are generated using the following standard reset
924 
synchronizer:<br>
925 
 
926 
<div style="text-align: center;"><img alt="Sync Reset" src="http://opencores.org/usercontent,img,1330809533" width="40%"><br>
927 
</div>
928 
 
929 
<br>
930 
 
931 
<a name="4_7_Wakeup_Cell"></a>
932 
<h2>4.7 Wakeup Cell ( <span style="font-style: italic;">omsp_wakeup_cell.v</span>
933 
)<br>
934 
</h2>
935 
 
936 
The wakeup cell is the most unconventional module of the
937 
openMSP430 design as it contains a flip-flop whose clock and reset are
938 
both coming from a data path.<br>
939 
 
940 
In the openMSP430 core, it is instantiated a single time in the
941 
watchdog
942 
timer but can also be reused in external custom peripherals.<br>
943 
 
944 
<br>
945 
 
946 
The implementation of the block looks as following:<br>
947 
 
948 
<div style="text-align: center;"><img alt="Wakeup cell" src="http://opencores.org/usercontent,img,1331155523" width="60%"><br>
949 
</div>
950 
 
951 
<br>
952 
 
953 
The basic idea here is simply to set the WKUP_OUT signal with a
954 
rising edge on the WKUP_EVENT port, and clear it when WKUP_CLEAR is
955 
active (i.e. level sensitive clear).<br>
956 
 
957 
<br>
958 
 
959 
In order to give a better perspective from a system point of view, the
960 
following diagram shows how the wakeup cell has been used in the
961 
particular case of the watchdog timer (note that WDTIFG_CLR_REG and
962 
WDTQN_EDGE_REG are both output of a flip-flop and therefore
963 
glitch-free):<br>
964 
 
965 
<br>
966 
 
967 
<div style="text-align: center;"><img alt="Watchdog wakeup" src="http://opencores.org/usercontent,img,1331155543" width="100%"><br>
968 
</div>
969 
 
970 
<h1>
971 
</h1>
972 
 
973 
<span style="font-weight: bold; text-decoration: underline;">Note:</span>
974 
Wake-up signals can of course be generated in a
975 
different way as long as they directly come from a flip-flop (or are
976 
certified to be non-glitchy).<br>
977 
 
978 
For example a simple handshake between the WDT_CLK and MCLK clock
979 
domains could have been used to clear the WDT_WKUP signal in a fully
980 
synchronous
981 
manner.<br>
982 
 
983 
However, it is to be noted that this handshake would introduce some
984 
synchronization
985 
delay, which might not be negligible if MCLK and WDT_CLK frequencies
986 
are orders of magnitude apart (i.e. several MHz for MCLK and 32kHz
987 
for WDT_CLK).<br>
988 
 
989 
As getting the oscillators back to sleep as fast as possible might
990 
prove to be extremely important for low-power designs, this
991 
asynchronous solution was selected for the <span style="font-style: italic; font-weight: bold;">omsp_watchdog</span>
992 
implementation.<br>
993 
 
994 
<br>
995 
 
996 
<br>
997 
 
998 
</body></html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.