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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html>
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<head>
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<title>openMSP430 Core</title>
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</head>
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<body>
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<h3>Table of content</h3>
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<ul>
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<li><a href="#1. Introduction">1. Introduction</a></li>
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<li><a href="#2. Design"> 2. Design</a>
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<ul>
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<li><a href="#2.1 Core"> 2.1 Core</a>
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<ul>
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<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
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<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
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<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
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<ul>
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<li><a href="#2.1.3.1 Basic System Configuration"> 2.1.3.1 Basic System Configuration</a></li>
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<li><a href="#2.1.3.2 Advanced System Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
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<li><a href="#2.1.3.3 Expert System Configuration"> 2.1.3.3 Expert System Configuration</a></li>
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</ul>
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<li><a href="#2.1.4 Memory mapping"> 2.1.4 Memory mapping</a></li>
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<li><a href="#2.1.5 Pinout"> 2.1.5 Pinout</a></li>
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<li><a href="#2.1.6 Instruction Cycles and Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.7 Serial Debug Interface"> 2.1.7 Serial Debug Interface</a></li>
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</ul>
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</li>
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<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
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<ul>
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<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
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<li><a href="#2.2.2 Watchdog Timer"> 2.2.2 Watchdog Timer</a></li>
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<li><a href="#2.2.3 Digital I/O"> 2.2.3 Digital I/O</a></li>
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<li><a href="#2.2.4 Timer A"> 2.2.4 Timer A</a></li>
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<li><a href="#2.2.5 16x16 Hardware Multiplier"> 2.2.5 16x16 Hardware Multiplier</a></li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b> (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
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<br /><br />
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This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
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<br /><br />
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It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
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However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
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<br /><br />
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In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
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<br /><br />
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<a name="2. Design"></a>
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<h1>2. Design</h1>
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<a name="2.1 Core"></a>
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<h2>2.1 Core</h2>
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<a name="2.1.1 Design structure"></a>
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<h3>2.1.1 Design structure</h3>
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The following diagram shows the openMSP430 design structure:
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<br /><br />
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<img src="getimg.php?1267738921" width="100%" alt="CPU Structure" title="CPU Structure" />
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<br />
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<ul>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li>
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<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
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<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
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<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
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<li><b>16x16 Multiplier</b>: The hardware multiplier peripheral is transparently supported by the GCC compiler and is also located in the core. It can be included or excluded at will through a Verilog define.</li>
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</ul>
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<a name="2.1.2 Limitations"></a>
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<h3>2.1.2 Limitations</h3>
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The known core limitations are the following:
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<br />
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<ul>
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<li>Instructions can't be executed from the data memory.</li>
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<li>SCG0 is not implemented (turns off DCO).</li>
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<li>MCLK can't be divided and can only have DCO_CLK as source (see <a href="#2.2.1 Basic Clock Module">Basic Clock Module</a> section).</li>
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</ul>
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<a name="2.1.3 Configuration"></a>
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<h3>2.1.3 Configuration</h3>
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It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
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Three sets of parameters can be adjusted by the user in order to fully customize the core.
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<a name="2.1.3.1 Basic System Configuration"></a>
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<h4>2.1.3.1 Basic System Configuration</h4>
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The basic system can be adjusted with the following set of defines in order to match the target system requirements.
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<br /><br />
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<table border="0" cellspacing="4" cellpadding="0">
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<tr>
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<td width="35"></td>
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<td bgcolor="#d0d0d0" width="3"></td>
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<td width="15"></td>
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<td>
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<code>
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//============================================================================
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<br />//============================================================================
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<br />// BASIC SYSTEM CONFIGURATION
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<br />//============================================================================
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<br />//============================================================================
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<br />//
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<br />// Note: the sum of program, data and peripheral memory spaces must not
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<br />// exceed 64 kB
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<br />//
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<br />
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<br />// Program Memory Size:
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<br />// Uncomment the required memory size
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<br />//-------------------------------------------------------
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<br />//`define PMEM_SIZE_59_KB
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<br />//`define PMEM_SIZE_55_KB
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<br />//`define PMEM_SIZE_54_KB
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<br />//`define PMEM_SIZE_51_KB
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<br />//`define PMEM_SIZE_48_KB
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<br />//`define PMEM_SIZE_41_KB
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<br />//`define PMEM_SIZE_32_KB
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<br />//`define PMEM_SIZE_24_KB
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<br />//`define PMEM_SIZE_16_KB
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<br />//`define PMEM_SIZE_12_KB
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<br />//`define PMEM_SIZE_8_KB
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<br />//`define PMEM_SIZE_4_KB
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<br />`define PMEM_SIZE_2_KB
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<br />//`define PMEM_SIZE_1_KB
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<br />
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<br />// Data Memory Size:
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<br />// Uncomment the required memory size
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<br />//-------------------------------------------------------
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<br />//`define DMEM_SIZE_32_KB
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<br />//`define DMEM_SIZE_24_KB
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<br />//`define DMEM_SIZE_16_KB
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<br />//`define DMEM_SIZE_10_KB
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<br />//`define DMEM_SIZE_8_KB
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<br />//`define DMEM_SIZE_5_KB
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<br />//`define DMEM_SIZE_4_KB
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<br />//`define DMEM_SIZE_2p5_KB
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<br />//`define DMEM_SIZE_2_KB
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<br />//`define DMEM_SIZE_1_KB
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<br />//`define DMEM_SIZE_512_B
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<br />//`define DMEM_SIZE_256_B
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<br />`define DMEM_SIZE_128_B
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<br />
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<br />// Include/Exclude Hardware Multiplier
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<br />`define MULTIPLIER
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<br />
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<br />// Include/Exclude Serial Debug interface
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<br />`define DBG_EN
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</code>
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</td>
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</tr>
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</table>
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<br /><br />
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The only design considerations at this stage are:
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<ul>
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<li>Make sure that the program and data memories have the correct size :-P</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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<br />
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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In this section, some additional features are available in order to match the needs of more experienced users.
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<br /><br />
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<table border="0" cellspacing="4" cellpadding="0">
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<tr>
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<td width="35"></td>
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<td bgcolor="#d0d0d0" width="3"></td>
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<td width="15"></td>
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<td>
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<code>
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//============================================================================
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<br />//============================================================================
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<br />// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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<br />//============================================================================
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<br />//============================================================================
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<br />
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<br />//-------------------------------------------------------
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<br />// Peripheral Memory Space:
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<br />//-------------------------------------------------------
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<br />// The original MSP430 architecture map the peripherals
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<br />// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
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<br />// The following defines allow you to expand this space
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<br />// up to 32 kB (i.e. from 0x0000 to 0x7fff).
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<br />// As a consequence, the data memory mapping will be
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<br />// shifted up and a custom linker script will therefore
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<br />// be required by the GCC compiler.
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<br />//-------------------------------------------------------
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<br />//`define PER_SIZE_32_KB
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<br />//`define PER_SIZE_16_KB
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<br />//`define PER_SIZE_8_KB
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<br />//`define PER_SIZE_4_KB
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<br />//`define PER_SIZE_2_KB
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<br />//`define PER_SIZE_1_KB
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<br />`define PER_SIZE_512_B
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<br />
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<br />
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<br />//-------------------------------------------------------
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<br />// Defines the debugger CPU_CTL.RST_BRK_EN reset value
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<br />// (CPU break on PUC reset)
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<br />//-------------------------------------------------------
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<br />// When defined, the CPU will automatically break after
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<br />// a PUC occurrence by default. This is typically usefull
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<br />// when the program memory can only be initialized through
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<br />// the serial debug interface.
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<br />//-------------------------------------------------------
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<br />//`define DBG_RST_BRK_EN
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<br />
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<br />
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<br />//-------------------------------------------------------
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<br />// Custom user version number
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<br />//-------------------------------------------------------
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<br />// This 5 bit field can be freely used in order to allow
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<br />// custom identification of the system through the debug
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<br />// interface.
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<br />// (see CPU_ID.USER_VERSION field in the documentation)
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<br />//-------------------------------------------------------
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<br />`define USER_VERSION 5'b00000
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<br />
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</code>
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</td>
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</tr>
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</table>
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<br /><br />
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Design consideration at this stage are:
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<ul>
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<li>Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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<br />
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<a name="2.1.3.3 Expert System Configuration"></a>
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<h4>2.1.3.3 Expert System Configuration</h4>
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In this section, you will find configuration options which will be relevant for roughly 0.01% of the users (according to an highly reliable market analysis ;-) ).
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<br /><br />
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<table border="0" cellspacing="4" cellpadding="0">
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<tr>
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<td width="35"></td>
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<td bgcolor="#d0d0d0" width="3"></td>
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<td width="15"></td>
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<td>
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<code>
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//============================================================================
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<br />//============================================================================
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<br />// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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<br />//============================================================================
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<br />//============================================================================
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<br />//
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<br />// IMPORTANT NOTE: Please update following configuration options ONLY if
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<br />// you have a good reason to do so... and if you know what
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<br />// you are doing :-P
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<br />//
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<br />//============================================================================
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<br />
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<br />//-------------------------------------------------------
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<br />// Number of hardware breakpoint units (each unit contains
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<br />// two hardware address breakpoints):
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<br />// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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<br />// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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<br />// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
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<br />// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
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<br />//-------------------------------------------------------
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<br />// Please keep in mind that hardware breakpoints only
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<br />// make sense whenever the program memory is not an SRAM
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<br />// (i.e. Flash/OTP/ROM/...) or when you are interested
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<br />// in data breakpoints (btw. not supported by GDB).
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<br />//-------------------------------------------------------
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<br />//`define DBG_HWBRK_0
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<br />//`define DBG_HWBRK_1
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<br />//`define DBG_HWBRK_2
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<br />//`define DBG_HWBRK_3
|
| 281 |
|
|
<br />
|
| 282 |
|
|
<br />//-------------------------------------------------------
|
| 283 |
|
|
<br />// Enable/Disable the hardware breakpoint RANGE mode
|
| 284 |
|
|
<br />//-------------------------------------------------------
|
| 285 |
|
|
<br />// When enabled this feature allows the hardware breakpoint
|
| 286 |
|
|
<br />// units to stop the cpu whenever an instruction or data
|
| 287 |
|
|
<br />// access lays within an address range.
|
| 288 |
|
|
<br />// Note that this feature is not supported by GDB.
|
| 289 |
|
|
<br />//-------------------------------------------------------
|
| 290 |
|
|
<br />//`define DBG_HWBRK_RANGE
|
| 291 |
|
|
<br />
|
| 292 |
|
|
<br />//-------------------------------------------------------
|
| 293 |
|
|
<br />// Input synchronizers
|
| 294 |
|
|
<br />//-------------------------------------------------------
|
| 295 |
|
|
<br />// In some cases, the asynchronous input ports might
|
| 296 |
|
|
<br />// already be synchronized externally.
|
| 297 |
|
|
<br />// If an extensive CDC design review showed that this
|
| 298 |
|
|
<br />// is really the case, the individual synchronizers
|
| 299 |
|
|
<br />// can be disabled with the following defines.
|
| 300 |
|
|
<br />//
|
| 301 |
|
|
<br />// Notes:
|
| 302 |
|
|
<br />// - the dbg_en signal will reset the debug interface
|
| 303 |
|
|
<br />// when 0. Therefore make sure it is glitch free.
|
| 304 |
|
|
<br />//
|
| 305 |
|
|
<br />// - the dbg_uart_rxd synchronizer must be set to 1
|
| 306 |
|
|
<br />// when its reset is active.
|
| 307 |
|
|
<br />//-------------------------------------------------------
|
| 308 |
|
|
<br />`define SYNC_CPU_EN
|
| 309 |
|
|
<br />`define SYNC_DBG_EN
|
| 310 |
|
|
<br />`define SYNC_DBG_UART_RXD
|
| 311 |
|
|
<br />`define SYNC_NMI
|
| 312 |
|
|
<br />
|
| 313 |
69 |
olivier.gi |
</code>
|
| 314 |
|
|
</td>
|
| 315 |
|
|
</tr>
|
| 316 |
|
|
</table>
|
| 317 |
116 |
olivier.gi |
<br /><br />
|
| 318 |
|
|
Design consideration at this stage are:
|
| 319 |
|
|
<ul>
|
| 320 |
|
|
<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
|
| 321 |
|
|
</ul>
|
| 322 |
|
|
<br />
|
| 323 |
|
|
All remaining defines located in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
|
| 324 |
|
|
<br /><br />
|
| 325 |
50 |
olivier.gi |
|
| 326 |
116 |
olivier.gi |
<a name="2.1.4 Memory mapping"></a>
|
| 327 |
|
|
<h3>2.1.4 Memory mapping</h3>
|
| 328 |
50 |
olivier.gi |
|
| 329 |
116 |
olivier.gi |
As discussed in the earlier section, the openMSP430 memory mapping is fully configurable.<br />
|
| 330 |
|
|
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC4 (or any other toolchain for that matter).<br />
|
| 331 |
|
|
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section give the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.<br />
|
| 332 |
|
|
The following schematic should hopefully summarize this:<br />
|
| 333 |
|
|
<br /><br />
|
| 334 |
|
|
<img src="usercontent,img,1306066277" width="100%" alt="Memory mapping" title="Memory mapping" />
|
| 335 |
|
|
<br />
|
| 336 |
|
|
|
| 337 |
|
|
<br /><br />
|
| 338 |
|
|
<a name="2.1.5 Pinout"></a>
|
| 339 |
|
|
<h3>2.1.5 Pinout</h3>
|
| 340 |
|
|
|
| 341 |
50 |
olivier.gi |
The full pinout of the openMSP430 core is provided in the following table:
|
| 342 |
|
|
<br /><br />
|
| 343 |
|
|
<table border="1">
|
| 344 |
|
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 345 |
|
|
|
| 346 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
|
| 347 |
|
|
<tr>
|
| 348 |
116 |
olivier.gi |
<td> cpu_en </td>
|
| 349 |
|
|
<td> Input </td>
|
| 350 |
|
|
<td> 1 </td>
|
| 351 |
|
|
<td> Enable CPU code execution (asynchronous) - set to 1 if unused </td>
|
| 352 |
|
|
</tr>
|
| 353 |
|
|
<tr>
|
| 354 |
50 |
olivier.gi |
<td> dco_clk </td>
|
| 355 |
|
|
<td> Input </td>
|
| 356 |
|
|
<td> 1 </td>
|
| 357 |
|
|
<td> Fast oscillator (fast clock), CPU clock </td>
|
| 358 |
|
|
</tr>
|
| 359 |
|
|
<tr>
|
| 360 |
|
|
<td> lfxt_clk </td>
|
| 361 |
|
|
<td> Input </td>
|
| 362 |
|
|
<td> 1 </td>
|
| 363 |
|
|
<td> Low frequency oscillator (typ. 32kHz) </td>
|
| 364 |
|
|
</tr>
|
| 365 |
|
|
<tr>
|
| 366 |
|
|
<td> mclk </td>
|
| 367 |
|
|
<td> Output </td>
|
| 368 |
|
|
<td> 1 </td>
|
| 369 |
|
|
<td> Main system clock </td>
|
| 370 |
|
|
</tr>
|
| 371 |
|
|
<tr>
|
| 372 |
|
|
<td> aclk_en </td>
|
| 373 |
|
|
<td> Output </td>
|
| 374 |
|
|
<td> 1 </td>
|
| 375 |
|
|
<td> ACLK enable </td>
|
| 376 |
|
|
</tr>
|
| 377 |
|
|
<tr>
|
| 378 |
|
|
<td> smclk_en </td>
|
| 379 |
|
|
<td> Output </td>
|
| 380 |
|
|
<td> 1 </td>
|
| 381 |
|
|
<td> SMCLK enable </td>
|
| 382 |
|
|
</tr>
|
| 383 |
|
|
|
| 384 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
|
| 385 |
|
|
<tr>
|
| 386 |
116 |
olivier.gi |
<td> puc_rst </td>
|
| 387 |
50 |
olivier.gi |
<td> Output </td>
|
| 388 |
|
|
<td> 1 </td>
|
| 389 |
|
|
<td> Main system reset </td>
|
| 390 |
|
|
</tr>
|
| 391 |
|
|
<tr>
|
| 392 |
|
|
<td> reset_n </td>
|
| 393 |
|
|
<td> Input </td>
|
| 394 |
|
|
<td> 1 </td>
|
| 395 |
116 |
olivier.gi |
<td> Reset Pin (active low, asynchronous) </td>
|
| 396 |
50 |
olivier.gi |
</tr>
|
| 397 |
|
|
|
| 398 |
|
|
|
| 399 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
| 400 |
|
|
<tr>
|
| 401 |
|
|
<td> pmem_addr </td>
|
| 402 |
|
|
<td> Output </td>
|
| 403 |
116 |
olivier.gi |
<td> `PMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b> </td>
|
| 404 |
50 |
olivier.gi |
<td> Program Memory address </td>
|
| 405 |
|
|
</tr>
|
| 406 |
|
|
<tr>
|
| 407 |
|
|
<td> pmem_cen </td>
|
| 408 |
|
|
<td> Output </td>
|
| 409 |
|
|
<td> 1 </td>
|
| 410 |
|
|
<td> Program Memory chip enable (low active) </td>
|
| 411 |
|
|
</tr>
|
| 412 |
|
|
<tr>
|
| 413 |
|
|
<td> pmem_din </td>
|
| 414 |
|
|
<td> Output </td>
|
| 415 |
|
|
<td> 16 </td>
|
| 416 |
116 |
olivier.gi |
<td> Program Memory data input (optional <b><sup><font color="#FF0000">2</font></sup></b>)</td>
|
| 417 |
50 |
olivier.gi |
</tr>
|
| 418 |
|
|
<tr>
|
| 419 |
|
|
<td> pmem_dout </td>
|
| 420 |
|
|
<td> Input </td>
|
| 421 |
|
|
<td> 16 </td>
|
| 422 |
|
|
<td> Program Memory data output </td>
|
| 423 |
|
|
</tr>
|
| 424 |
|
|
<tr>
|
| 425 |
|
|
<td> pmem_wen </td>
|
| 426 |
|
|
<td> Output </td>
|
| 427 |
|
|
<td> 2 </td>
|
| 428 |
116 |
olivier.gi |
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#FF0000">2</font></sup></b>) </td>
|
| 429 |
50 |
olivier.gi |
</tr>
|
| 430 |
|
|
|
| 431 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
| 432 |
|
|
<tr>
|
| 433 |
|
|
<td> dmem_addr </td>
|
| 434 |
|
|
<td> Output </td>
|
| 435 |
116 |
olivier.gi |
<td> `DMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b></td>
|
| 436 |
50 |
olivier.gi |
<td> Data Memory address </td>
|
| 437 |
|
|
</tr>
|
| 438 |
|
|
<tr>
|
| 439 |
|
|
<td> dmem_cen </td>
|
| 440 |
|
|
<td> Output </td>
|
| 441 |
|
|
<td> 1 </td>
|
| 442 |
|
|
<td> Data Memory chip enable (low active) </td>
|
| 443 |
|
|
</tr>
|
| 444 |
|
|
<tr>
|
| 445 |
|
|
<td> dmem_din </td>
|
| 446 |
|
|
<td> Output </td>
|
| 447 |
|
|
<td> 16 </td>
|
| 448 |
|
|
<td> Data Memory data input </td>
|
| 449 |
|
|
</tr>
|
| 450 |
|
|
<tr>
|
| 451 |
|
|
<td> dmem_dout </td>
|
| 452 |
|
|
<td> Input </td>
|
| 453 |
|
|
<td> 16 </td>
|
| 454 |
|
|
<td> Data Memory data output </td>
|
| 455 |
|
|
</tr>
|
| 456 |
|
|
<tr>
|
| 457 |
|
|
<td> dmem_wen </td>
|
| 458 |
|
|
<td> Output </td>
|
| 459 |
|
|
<td> 2 </td>
|
| 460 |
116 |
olivier.gi |
<td> Data Memory write byte enable (low active) </td>
|
| 461 |
50 |
olivier.gi |
</tr>
|
| 462 |
|
|
|
| 463 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 464 |
|
|
<tr>
|
| 465 |
|
|
<td> per_addr </td>
|
| 466 |
|
|
<td> Output </td>
|
| 467 |
116 |
olivier.gi |
<td> 14 </td>
|
| 468 |
50 |
olivier.gi |
<td> Peripheral address </td>
|
| 469 |
|
|
</tr>
|
| 470 |
|
|
<tr>
|
| 471 |
|
|
<td> per_din </td>
|
| 472 |
|
|
<td> Output </td>
|
| 473 |
|
|
<td> 16 </td>
|
| 474 |
|
|
<td> Peripheral data input </td>
|
| 475 |
|
|
</tr>
|
| 476 |
|
|
<tr>
|
| 477 |
|
|
<td> per_dout </td>
|
| 478 |
|
|
<td> Input </td>
|
| 479 |
|
|
<td> 16 </td>
|
| 480 |
|
|
<td> Peripheral data output </td>
|
| 481 |
|
|
</tr>
|
| 482 |
|
|
<tr>
|
| 483 |
|
|
<td> per_en </td>
|
| 484 |
|
|
<td> Output </td>
|
| 485 |
|
|
<td> 1 </td>
|
| 486 |
|
|
<td> Peripheral enable (high active) </td>
|
| 487 |
|
|
</tr>
|
| 488 |
|
|
<tr>
|
| 489 |
116 |
olivier.gi |
<td> per_we </td>
|
| 490 |
50 |
olivier.gi |
<td> Output </td>
|
| 491 |
|
|
<td> 2 </td>
|
| 492 |
|
|
<td> Peripheral write enable (high active) </td>
|
| 493 |
|
|
</tr>
|
| 494 |
|
|
|
| 495 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 496 |
|
|
<tr>
|
| 497 |
|
|
<td> irq </td>
|
| 498 |
|
|
<td> Input </td>
|
| 499 |
|
|
<td> 14 </td>
|
| 500 |
|
|
<td> Maskable interrupts (one-hot signal) </td>
|
| 501 |
|
|
</tr>
|
| 502 |
|
|
<tr>
|
| 503 |
|
|
<td> nmi </td>
|
| 504 |
|
|
<td> Input </td>
|
| 505 |
|
|
<td> 1 </td>
|
| 506 |
|
|
<td> Non-maskable interrupt (asynchronous) </td>
|
| 507 |
|
|
</tr>
|
| 508 |
|
|
<tr>
|
| 509 |
|
|
<td> irq_acc </td>
|
| 510 |
|
|
<td> Output </td>
|
| 511 |
|
|
<td> 14 </td>
|
| 512 |
|
|
<td> Interrupt request accepted (one-hot signal) </td>
|
| 513 |
|
|
</tr>
|
| 514 |
|
|
|
| 515 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
| 516 |
|
|
<tr>
|
| 517 |
116 |
olivier.gi |
<td> dbg_en </td>
|
| 518 |
|
|
<td> Input </td>
|
| 519 |
|
|
<td> 1 </td>
|
| 520 |
|
|
<td> Debug interface enable (asynchronous) <b><sup><font color="#FF0000">3</font></sup></b> </td>
|
| 521 |
|
|
</tr>
|
| 522 |
|
|
<tr>
|
| 523 |
50 |
olivier.gi |
<td> dbg_freeze </td>
|
| 524 |
|
|
<td> Output </td>
|
| 525 |
|
|
<td> 1 </td>
|
| 526 |
|
|
<td> Freeze peripherals </td>
|
| 527 |
|
|
</tr>
|
| 528 |
|
|
<tr>
|
| 529 |
|
|
<td> dbg_uart_txd </td>
|
| 530 |
|
|
<td> Output </td>
|
| 531 |
|
|
<td> 1 </td>
|
| 532 |
|
|
<td> Debug interface: UART TXD </td>
|
| 533 |
|
|
</tr>
|
| 534 |
|
|
<tr>
|
| 535 |
|
|
<td> dbg_uart_rxd </td>
|
| 536 |
|
|
<td> Input </td>
|
| 537 |
|
|
<td> 1 </td>
|
| 538 |
116 |
olivier.gi |
<td> Debug interface: UART RXD (asynchronous) </td>
|
| 539 |
50 |
olivier.gi |
</tr>
|
| 540 |
|
|
</table>
|
| 541 |
|
|
<br />
|
| 542 |
116 |
olivier.gi |
<b><sup><font color="#FF0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
|
| 543 |
|
|
<b><sup><font color="#FF0000">2</font></sup></b>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.<br />
|
| 544 |
|
|
<b><sup><font color="#FF0000">3</font></sup></b>: When disabled, the debug interface is hold into reset. As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br />
|
| 545 |
|
|
<br />
|
| 546 |
50 |
olivier.gi |
|
| 547 |
116 |
olivier.gi |
<a name="2.1.6 Instruction Cycles and Lengths"></a>
|
| 548 |
|
|
<h3>2.1.6 Instruction Cycles and Lengths</h3>
|
| 549 |
50 |
olivier.gi |
|
| 550 |
116 |
olivier.gi |
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br /><br />
|
| 551 |
|
|
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.<br />
|
| 552 |
|
|
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
| 553 |
50 |
olivier.gi |
Differences with the original MSP430 are highlighted in green (the original value being red).
|
| 554 |
|
|
<ul>
|
| 555 |
|
|
<li><b>Interrupt and Reset Cycles</b></li>
|
| 556 |
|
|
</ul>
|
| 557 |
|
|
<table border="1">
|
| 558 |
|
|
<tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
|
| 559 |
|
|
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
|
| 560 |
|
|
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
|
| 561 |
|
|
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
| 562 |
|
|
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
| 563 |
|
|
</table>
|
| 564 |
|
|
|
| 565 |
|
|
<ul>
|
| 566 |
|
|
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
|
| 567 |
|
|
</ul>
|
| 568 |
|
|
<table border="1">
|
| 569 |
|
|
<tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
| 570 |
|
|
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
|
| 571 |
|
|
|
| 572 |
|
|
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 573 |
|
|
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
|
| 574 |
|
|
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 575 |
|
|
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 576 |
|
|
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 577 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 578 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 579 |
|
|
</table>
|
| 580 |
|
|
|
| 581 |
|
|
<ul>
|
| 582 |
|
|
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
|
| 583 |
|
|
</ul>
|
| 584 |
|
|
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
|
| 585 |
|
|
|
| 586 |
|
|
<ul>
|
| 587 |
|
|
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
|
| 588 |
|
|
</ul>
|
| 589 |
|
|
<table border="1">
|
| 590 |
|
|
<tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
| 591 |
|
|
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
|
| 592 |
|
|
|
| 593 |
|
|
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
|
| 594 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 595 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 596 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 597 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 598 |
|
|
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 599 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 600 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 601 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 602 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 603 |
|
|
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 604 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
|
| 605 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 606 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 607 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 608 |
|
|
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
|
| 609 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 610 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 611 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 612 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 613 |
|
|
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 614 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
| 615 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 616 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 617 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 618 |
|
|
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 619 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
| 620 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 621 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 622 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 623 |
|
|
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 624 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 625 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 626 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 627 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 628 |
|
|
</table>
|
| 629 |
|
|
|
| 630 |
116 |
olivier.gi |
<a name="2.1.7 Serial Debug Interface"></a>
|
| 631 |
|
|
<h3>2.1.7 Serial Debug Interface</h3>
|
| 632 |
50 |
olivier.gi |
|
| 633 |
|
|
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
|
| 634 |
|
|
<a name="2.2 Peripherals"></a>
|
| 635 |
|
|
<h2>2.2 Peripherals</h2>
|
| 636 |
|
|
|
| 637 |
|
|
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
|
| 638 |
|
|
|
| 639 |
|
|
<a name="2.2.1 Basic Clock Module"></a>
|
| 640 |
|
|
<h3>2.2.1 Basic Clock Module</h3>
|
| 641 |
|
|
|
| 642 |
|
|
In order to make an FPGA implementation as simple as possible (ideally, a non-designer should be able to do it), clock gates are not used in the design and neither are clock muxes.
|
| 643 |
|
|
<br />
|
| 644 |
|
|
With these constrains, the Basic Clock Module is implemented as following:
|
| 645 |
|
|
<br /><br />
|
| 646 |
|
|
<img src="getimg.php?1249244393" alt="Clock structure diagram" title="Clock structure diagram" />
|
| 647 |
|
|
<br />
|
| 648 |
|
|
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.
|
| 649 |
|
|
<br /><br />
|
| 650 |
|
|
|
| 651 |
|
|
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
|
| 652 |
|
|
<br /><br />
|
| 653 |
|
|
<img src="getimg.php?1246434793" alt="Clock implementation example" title="Clock implementation example" />
|
| 654 |
|
|
<br /><br />
|
| 655 |
|
|
The following Verilog code would implement a counter clocked with SMCLK:
|
| 656 |
|
|
<br />
|
| 657 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 658 |
|
|
<tr>
|
| 659 |
|
|
<td width="35"></td>
|
| 660 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 661 |
|
|
<td width="15"></td>
|
| 662 |
|
|
<td>
|
| 663 |
|
|
<code>
|
| 664 |
|
|
reg [7:0] test_cnt;
|
| 665 |
|
|
<br />
|
| 666 |
116 |
olivier.gi |
<br />always @ (posedge mclk or posedge puc_rst)
|
| 667 |
|
|
<br /> if (puc_rst) test_cnt <= 8'h00;
|
| 668 |
50 |
olivier.gi |
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
| 669 |
|
|
</code>
|
| 670 |
|
|
</td>
|
| 671 |
|
|
</tr>
|
| 672 |
|
|
</table>
|
| 673 |
|
|
<br /><br />
|
| 674 |
|
|
<b>Register Description</b>
|
| 675 |
|
|
<ul>
|
| 676 |
|
|
<li>DCOCTL: Not implemented</li>
|
| 677 |
|
|
<li>BCSCTL1:
|
| 678 |
|
|
<ul>
|
| 679 |
|
|
<li>BCSCTL1[7:6]: Unused</li>
|
| 680 |
|
|
<li>BCSCTL1[5:4]: DIVAx</li>
|
| 681 |
|
|
<li>BCSCTL1[4:0]: Unused</li>
|
| 682 |
|
|
</ul>
|
| 683 |
|
|
</li>
|
| 684 |
|
|
<li>BCSCTL2:
|
| 685 |
|
|
<ul>
|
| 686 |
|
|
<li>BCSCTL2[7:4]: Unused</li>
|
| 687 |
|
|
<li>BCSCTL2[3] : SELS</li>
|
| 688 |
|
|
<li>BCSCTL2[2:1]: DIVSx</li>
|
| 689 |
|
|
<li>BCSCTL2[0] : Unused</li>
|
| 690 |
|
|
</ul>
|
| 691 |
|
|
</li>
|
| 692 |
|
|
</ul>
|
| 693 |
|
|
|
| 694 |
|
|
<a name="2.2.2 Watchdog Timer"></a>
|
| 695 |
|
|
<h3>2.2.2 Watchdog Timer</h3>
|
| 696 |
|
|
|
| 697 |
69 |
olivier.gi |
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.
|
| 698 |
50 |
olivier.gi |
|
| 699 |
|
|
<a name="2.2.3 Digital I/O"></a>
|
| 700 |
|
|
<h3>2.2.3 Digital I/O</h3>
|
| 701 |
|
|
|
| 702 |
69 |
olivier.gi |
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
|
| 703 |
50 |
olivier.gi |
<br /><br />
|
| 704 |
|
|
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
|
| 705 |
|
|
<br /><br />
|
| 706 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 707 |
|
|
<tr>
|
| 708 |
|
|
<td width="35"></td>
|
| 709 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 710 |
|
|
<td width="15"></td>
|
| 711 |
|
|
<td>
|
| 712 |
|
|
<code>
|
| 713 |
|
|
parameter P1_EN = 1'b1; // Enable Port 1
|
| 714 |
|
|
<br />parameter P2_EN = 1'b1; // Enable Port 2
|
| 715 |
|
|
<br />parameter P3_EN = 1'b0; // Enable Port 3
|
| 716 |
|
|
<br />parameter P4_EN = 1'b0; // Enable Port 4
|
| 717 |
|
|
<br />parameter P5_EN = 1'b0; // Enable Port 5
|
| 718 |
|
|
<br />parameter P6_EN = 1'b0; // Enable Port 6
|
| 719 |
|
|
</code>
|
| 720 |
|
|
</td>
|
| 721 |
|
|
</tr>
|
| 722 |
|
|
</table>
|
| 723 |
|
|
<br />
|
| 724 |
|
|
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
|
| 725 |
|
|
<br /><br />
|
| 726 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 727 |
|
|
<tr>
|
| 728 |
|
|
<td width="35"></td>
|
| 729 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 730 |
|
|
<td width="15"></td>
|
| 731 |
|
|
<td>
|
| 732 |
|
|
<code>
|
| 733 |
|
|
gpio #(.P1_EN(1),
|
| 734 |
|
|
<br /> .P2_EN(1),
|
| 735 |
|
|
<br /> .P3_EN(1),
|
| 736 |
|
|
<br /> .P4_EN(0),
|
| 737 |
|
|
<br /> .P5_EN(0),
|
| 738 |
|
|
<br /> .P6_EN(0)) gpio_0 (
|
| 739 |
|
|
</code>
|
| 740 |
|
|
</td>
|
| 741 |
|
|
</tr>
|
| 742 |
|
|
</table>
|
| 743 |
|
|
<br />
|
| 744 |
|
|
The full pinout of the GPIO module is provided in the following table:
|
| 745 |
|
|
<br /><br />
|
| 746 |
|
|
<table border="1">
|
| 747 |
|
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 748 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
| 749 |
|
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 750 |
116 |
olivier.gi |
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 751 |
50 |
olivier.gi |
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 752 |
|
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
| 753 |
|
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
| 754 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 755 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 756 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 757 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 758 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 759 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 760 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
|
| 761 |
|
|
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
|
| 762 |
|
|
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
|
| 763 |
|
|
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
|
| 764 |
|
|
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
|
| 765 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
|
| 766 |
|
|
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
|
| 767 |
|
|
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
|
| 768 |
|
|
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
|
| 769 |
|
|
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
|
| 770 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
|
| 771 |
|
|
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
|
| 772 |
|
|
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
|
| 773 |
|
|
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
|
| 774 |
|
|
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
|
| 775 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
|
| 776 |
|
|
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
|
| 777 |
|
|
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
|
| 778 |
|
|
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
|
| 779 |
|
|
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
|
| 780 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
|
| 781 |
|
|
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
|
| 782 |
|
|
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
|
| 783 |
|
|
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
|
| 784 |
|
|
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
|
| 785 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
|
| 786 |
|
|
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
|
| 787 |
|
|
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
|
| 788 |
|
|
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
|
| 789 |
|
|
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
|
| 790 |
|
|
</table>
|
| 791 |
|
|
|
| 792 |
|
|
<a name="2.2.4 Timer A"></a>
|
| 793 |
|
|
<h3>2.2.4 Timer A</h3>
|
| 794 |
|
|
|
| 795 |
69 |
olivier.gi |
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
|
| 796 |
50 |
olivier.gi |
<br /><br />
|
| 797 |
|
|
The full pinout of the Timer A module is provided in the following table:
|
| 798 |
|
|
<br /><br />
|
| 799 |
|
|
<table border="1">
|
| 800 |
|
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 801 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
|
| 802 |
|
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 803 |
|
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
| 804 |
|
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
| 805 |
|
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
| 806 |
|
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
| 807 |
116 |
olivier.gi |
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 808 |
50 |
olivier.gi |
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
|
| 809 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 810 |
|
|
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
|
| 811 |
|
|
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
|
| 812 |
|
|
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
|
| 813 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 814 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 815 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 816 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 817 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 818 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 819 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
|
| 820 |
|
|
<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
|
| 821 |
|
|
<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
|
| 822 |
|
|
<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
|
| 823 |
|
|
<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
|
| 824 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
|
| 825 |
|
|
<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
|
| 826 |
|
|
<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
|
| 827 |
|
|
<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
|
| 828 |
|
|
<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
|
| 829 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
|
| 830 |
|
|
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
|
| 831 |
|
|
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
|
| 832 |
|
|
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
|
| 833 |
|
|
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
|
| 834 |
|
|
</table>
|
| 835 |
|
|
<br />
|
| 836 |
|
|
<b>Note</b>: for the same reason as with the Basic Clock Module, the two additional clock inputs (TACLK and INCLK) are internally synchronized with the MCLK domain.
|
| 837 |
|
|
As a consequence, TACLK and INCLK should be at least 2 times slowlier than MCLK, and if these clock are used toghether with the Timer A output unit, some jitter might be observed on the generated output.
|
| 838 |
|
|
If this jitter is critical for the application, ACLK and INCLK should idealy be derivated from DCO_CLK.
|
| 839 |
69 |
olivier.gi |
<br /><br />
|
| 840 |
|
|
<a name="2.2.5 16x16 Hardware Multiplier"></a>
|
| 841 |
|
|
<h3>2.2.5 16x16 Hardware Multiplier</h3>
|
| 842 |
50 |
olivier.gi |
|
| 843 |
69 |
olivier.gi |
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
|
| 844 |
|
|
<br /><br />
|
| 845 |
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not.
|
| 846 |
|
|
<br /><br />
|
| 847 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 848 |
|
|
<tr>
|
| 849 |
|
|
<td width="35"></td>
|
| 850 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 851 |
|
|
<td width="15"></td>
|
| 852 |
|
|
<td>
|
| 853 |
|
|
<code>
|
| 854 |
|
|
// Include/Exclude Hardware Multiplier
|
| 855 |
|
|
<br />`define MULTIPLIER
|
| 856 |
|
|
</code>
|
| 857 |
|
|
</td>
|
| 858 |
|
|
</tr>
|
| 859 |
|
|
</table>
|
| 860 |
|
|
<br /><br />
|
| 861 |
|
|
|
| 862 |
|
|
<br /><br />
|
| 863 |
50 |
olivier.gi |
</body>
|
| 864 |
|
|
</html>
|
