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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 Core</title></head><body>
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<h3>Table of content</h3>
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<ul>
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<li><a href="#1.%20Introduction">1. Introduction</a></li>
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<li><a href="#2.%20Design"> 2. Design</a>
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<ul>
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<li><a href="#2.1%20Core"> 2.1 Core</a>
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<ul>
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<li><a href="#2.1.1%20Design%20structure"> 2.1.1 Design structure</a></li>
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<li><a href="#2.1.2%20Limitations"> 2.1.2 Limitations</a></li>
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<li><a href="#2.1.3%20Configuration"> 2.1.3 Configuration</a></li>
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<ul>
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<li><a href="#2.1.3.1%20Basic%20System%20Configuration"> 2.1.3.1 Basic System Configuration</a></li>
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<li><a href="#2.1.3.2%20Advanced%20System%20Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
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<li><a href="#2.1.3.3%20Expert%20System%20Configuration"> 2.1.3.3 Expert System Configuration</a></li>
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</ul>
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<li><a href="#2.1.4%20Memory%20mapping"> 2.1.4 Memory mapping</a></li>
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<li><a href="#2.1.5%20Pinout"> 2.1.5 Pinout</a></li>
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<li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.7%20Serial%20Debug%20Interface"> 2.1.7 Serial Debug Interface</a></li>
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</ul>
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</li>
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<li><a href="#2.2_System_Peripherals"> 2.2 System Peripherals</a>
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<ul>
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<li><a href="#2.2.1%20Basic%20Clock%20Module"> 2.2.1 Basic Clock Module: FPGA</a></li>
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<li><a href="#2.2.2_Basic_Clock_Module_ASIC"> 2.2.2 Basic Clock Module: ASIC</a></li>
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<li><a href="#2.2.3_SFR">2.2.3 SFR</a><br>
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</li>
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<li><a href="#2.2.2%20Watchdog%20Timer"> 2.2.4 Watchdog Timer</a></li>
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<li><a href="core.html#2.2.5%2016x16%20Hardware%20Multiplier"> 2.2.5 16x16 Hardware Multiplier</a></li>
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</ul>
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</li>
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<li><a href="#2.3_Peripherals"> 2.3 External Peripherals</a></li>
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<ul>
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<li><a href="core.html#2.2.3%20Digital%20I/O">2.3.1 Digital I/O (FPGA ONLY)</a></li>
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<li><a href="core.html#2.2.4%20Timer%20A"> 2.3.2 Timer A (FPGA ONLY)</a></li>
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</ul>
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</ul></li>
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</ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b>
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(note that the extended version of the architecture, the MSP430X, isn't
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supported by this IP). It is based on a Von Neumann architecture, with
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a single address space for instructions and data.
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<br><br>Depending on the selected configuration, this design can either be:<br>
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<ul>
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<ul>
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<ul>
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<li> <span style="font-weight: bold;">FPGA friendly</span>: the core doesn't contain any clock gate and has only a single clock
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domain. As a consequence, in this mode, the <span style="font-style: italic;">Basic Clock Module</span> peripheral has a few
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limitations.<br>
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<br>
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</li>
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<li> <span style="font-weight: bold;">ASIC friendly</span>: the core contains up to all clock management
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options (clock muxes & low-power modes, fine grained clock
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gating, ...) and is also ready for scan insertion. In this mode, the <span style="font-style: italic;">Basic Clock Module</span> offers all features listed in the official <a href="http://www.ti.com/litv/pdf/slau049f">documentation</a>.<br>
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</li>
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</ul>
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</ul>
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</ul>
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<br>It is to be noted that this IP doesn't contain the instruction and
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data memory blocks internally (these are technology dependent hard
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macros which are connected to the IP during chip integration).
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However the core is fully configurable in regard to the supported RAM
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and/or ROM sizes.
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<br><br>In addition to the CPU core itself, several peripherals are
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also provided and can be easily connected to the core during
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integration.
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<br><br>
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<a name="2. Design"></a>
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<h1>2. Design</h1>
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<a name="2.1 Core"></a>
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<h2>2.1 Core</h2>
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<a name="2.1.1 Design structure"></a>
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<h3>2.1.1 Design structure</h3>
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The following diagram shows the openMSP430 design structure:
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<br><br>
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<img src="usercontent,img,1267738921" alt="CPU Structure" title="CPU Structure" width="80%">
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<br>
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<ul>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Execution unit</b>:
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Containing the ALU and the register file, this module executes the
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current decoded instruction according to the execution state.</li>
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<li><b>Serial Debug Interface</b>:
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Contains all the required logic for a Nexus class 3 debugging unit
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(without trace). Communication with the host is done with a standard
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two-wire 8N1 serial interface.</li>
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<li><b>Memory backbone</b>: This block
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performs a simple arbitration between the frontend and execution-unit
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for program, data and peripheral memory access.</li>
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<li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>Watchdog</b>:
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Although it is a peripheral, the watchdog is directly included in
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the core because of its tight links with the NMI interrupts and PUC
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reset generation.</li>
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<li><b>16x16 Multiplier</b>: The hardware
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multiplier peripheral is transparently supported by the GCC compiler
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and is therefore located in the core. It can be included or excluded at will
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through a Verilog define.</li>
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</ul>
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<a name="2.1.2 Limitations"></a>
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<h3>2.1.2 Limitations</h3>
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The known core limitations are the following:
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<br>
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<ul>
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<li>Instructions can't be executed from the data memory.</li>
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</ul>
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<a name="2.1.3 Configuration"></a>
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<h3>2.1.3 Configuration</h3>
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It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br>In
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this section, three sets of adjustabe user parameters are discussed in
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order to customize the core. A fourth set is available for ASIC
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specific options and will be discussed in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
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section. <a name="2.1.3.1 Basic System Configuration"></a>
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<h4>2.1.3.1 Basic System Configuration</h4>
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The basic system can be adjusted with the following set of defines in order to match the target system requirements.
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<br><br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br>
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</td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td>
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<code>
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//============================================================================<br>
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//============================================================================<br>
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// BASIC SYSTEM CONFIGURATION<br>
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//============================================================================<br>
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//============================================================================<br>
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//<br>
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// Note: the sum of program, data and peripheral memory spaces must not<br>
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// exceed 64 kB<br>
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//<br>
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<br>
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// Program Memory Size:<br>
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//
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Uncomment the required memory size<br>
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//-------------------------------------------------------<br>
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//`define PMEM_SIZE_59_KB<br>
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//`define PMEM_SIZE_55_KB<br>
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//`define PMEM_SIZE_54_KB<br>
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//`define PMEM_SIZE_51_KB<br>
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//`define PMEM_SIZE_48_KB<br>
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//`define PMEM_SIZE_41_KB<br>
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//`define PMEM_SIZE_32_KB<br>
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//`define PMEM_SIZE_24_KB<br>
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//`define PMEM_SIZE_16_KB<br>
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//`define PMEM_SIZE_12_KB<br>
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//`define PMEM_SIZE_8_KB<br>
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//`define PMEM_SIZE_4_KB<br>
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`define PMEM_SIZE_2_KB<br>
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//`define PMEM_SIZE_1_KB<br>
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<br>
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<br>
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// Data Memory Size:<br>
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//
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Uncomment the required memory size<br>
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//-------------------------------------------------------<br>
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//`define DMEM_SIZE_32_KB<br>
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//`define DMEM_SIZE_24_KB<br>
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//`define DMEM_SIZE_16_KB<br>
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//`define DMEM_SIZE_10_KB<br>
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//`define DMEM_SIZE_8_KB<br>
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//`define DMEM_SIZE_5_KB<br>
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//`define DMEM_SIZE_4_KB<br>
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//`define DMEM_SIZE_2p5_KB<br>
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//`define DMEM_SIZE_2_KB<br>
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//`define DMEM_SIZE_1_KB<br>
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//`define DMEM_SIZE_512_B<br>
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//`define DMEM_SIZE_256_B<br>
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`define DMEM_SIZE_128_B<br>
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<br>
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<br>
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// Include/Exclude Hardware Multiplier<br>
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`define MULTIPLIER<br>
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<br>
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<br>
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// Include/Exclude Serial Debug interface<br>
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`define DBG_EN<br>
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</code></td></tr></tbody></table><br><br>
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The only design considerations at this stage are:
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<ul>
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<li>Make sure that the program and data memories have the correct size :-P</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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<br>
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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In this section, some additional features are available in order to match the needs of more experienced users.
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<br><br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br>
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</td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td><code>//============================================================================<br>
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//============================================================================<br>
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// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)<br>
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//============================================================================<br>
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//============================================================================<br>
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<br>
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//-------------------------------------------------------<br>
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// Custom user version number<br>
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//-------------------------------------------------------<br>
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// This 5 bit field can be freely used in order to allow<br>
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// custom identification of the system through the debug<br>
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// interface.<br>
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// (see CPU_ID.USER_VERSION field in the documentation)<br>
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//-------------------------------------------------------<br>
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`define USER_VERSION 5'b00000<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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// Include/Exclude Watchdog timer<br>
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//-------------------------------------------------------<br>
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// When excluded, the following functionality will be<br>
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// lost:<br>
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// - Watchog (both interval and watchdog modes)<br>
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// - NMI interrupt edge selection<br>
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// - Possibility to generate a software PUC reset<br>
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//-------------------------------------------------------<br>
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`define WATCHDOG<br>
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<br>
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<br>
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///-------------------------------------------------------<br>
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// Include/Exclude Non-Maskable-Interrupt support<br>
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//-------------------------------------------------------<br>
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`define NMI<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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// Input synchronizers<br>
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//-------------------------------------------------------<br>
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// In some cases, the asynchronous input ports might<br>
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// already be synchronized externally.<br>
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// If an extensive CDC design review showed that this<br>
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// is really the case, the individual synchronizers<br>
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// can be disabled with the following defines.<br>
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//<br>
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// Notes:<br>
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// - all three signals are all sampled in the MCLK domain<br>
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//<br>
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// - the dbg_en signal reset the debug interface<br>
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// when 0. Therefore make sure it is glitch free.<br>
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//<br>
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//-------------------------------------------------------<br>
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`define SYNC_NMI<br>
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//`define SYNC_CPU_EN<br>
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//`define SYNC_DBG_EN<br>
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</code><code><br>
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<br>
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</code><code>//-------------------------------------------------------<br>
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// Peripheral Memory Space:<br>
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//-------------------------------------------------------<br>
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// The original MSP430 architecture map the peripherals<br>
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// from 0x0000 to 0x01FF (i.e. 512B of the memory space).<br>
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// The following defines allow you to expand this space<br>
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
|
| 287 |
|
|
// As a consequence, the data memory mapping will be<br>
|
| 288 |
|
|
// shifted up and a custom linker script will therefore<br>
|
| 289 |
|
|
// be required by the GCC compiler.<br>
|
| 290 |
|
|
//-------------------------------------------------------<br>
|
| 291 |
|
|
//`define PER_SIZE_32_KB<br>
|
| 292 |
|
|
//`define PER_SIZE_16_KB<br>
|
| 293 |
|
|
//`define PER_SIZE_8_KB<br>
|
| 294 |
|
|
//`define PER_SIZE_4_KB<br>
|
| 295 |
|
|
//`define PER_SIZE_2_KB<br>
|
| 296 |
|
|
//`define PER_SIZE_1_KB<br>
|
| 297 |
|
|
`define PER_SIZE_512_B<br>
|
| 298 |
|
|
<br>
|
| 299 |
|
|
<br></code><code>//-------------------------------------------------------<br>
|
| 300 |
|
|
// Defines the debugger CPU_CTL.RST_BRK_EN reset value<br>
|
| 301 |
|
|
// (CPU break on PUC reset)<br>
|
| 302 |
|
|
//-------------------------------------------------------<br>
|
| 303 |
|
|
// When defined, the CPU will automatically break after<br>
|
| 304 |
|
|
// a PUC occurrence by default. This is typically useful<br>
|
| 305 |
|
|
// when the program memory can only be initialized through<br>
|
| 306 |
|
|
// the serial debug interface.<br>
|
| 307 |
|
|
//-------------------------------------------------------<br>
|
| 308 |
|
|
`define DBG_RST_BRK_EN</code><br>
|
| 309 |
|
|
</td></tr></tbody></table><br><br>
|
| 310 |
116 |
olivier.gi |
Design consideration at this stage are:
|
| 311 |
|
|
<ul>
|
| 312 |
135 |
olivier.gi |
<li>Setting a peripheral memory space to something else than 512B
|
| 313 |
|
|
will shift the data memory mapping up, which in turn will require the
|
| 314 |
|
|
use of a custom linker script. If you don't know what a linker script
|
| 315 |
|
|
is and if you don't want to know what it is, you should probably not
|
| 316 |
|
|
modify this section.</li>
|
| 317 |
116 |
olivier.gi |
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
|
| 318 |
|
|
</ul>
|
| 319 |
135 |
olivier.gi |
<br>
|
| 320 |
116 |
olivier.gi |
<a name="2.1.3.3 Expert System Configuration"></a>
|
| 321 |
|
|
<h4>2.1.3.3 Expert System Configuration</h4>
|
| 322 |
135 |
olivier.gi |
In this section, you will find configuration options which are
|
| 323 |
|
|
relevant for roughly 0.1% of the users (according to a highly
|
| 324 |
|
|
reliable market analysis ;-) ).
|
| 325 |
|
|
<br><br>
|
| 326 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 327 |
|
|
<tbody><tr>
|
| 328 |
|
|
<td width="35"><br>
|
| 329 |
|
|
</td>
|
| 330 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 331 |
|
|
</td>
|
| 332 |
|
|
<td width="15"><br>
|
| 333 |
|
|
</td>
|
| 334 |
69 |
olivier.gi |
<td>
|
| 335 |
135 |
olivier.gi |
<code> //============================================================================<br>
|
| 336 |
|
|
//============================================================================<br>
|
| 337 |
|
|
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )<br>
|
| 338 |
|
|
//============================================================================<br>
|
| 339 |
|
|
//============================================================================<br>
|
| 340 |
|
|
//<br>
|
| 341 |
|
|
// IMPORTANT NOTE: Please update following configuration options ONLY if<br>
|
| 342 |
|
|
//
|
| 343 |
|
|
you have a good reason to do so... and if you know what<br>
|
| 344 |
|
|
// you are doing :-P<br>
|
| 345 |
|
|
//<br>
|
| 346 |
|
|
//============================================================================<br>
|
| 347 |
|
|
<br>
|
| 348 |
|
|
//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
|
| 349 |
|
|
// (each unit contains two hardware addresses available<br>
|
| 350 |
|
|
// for breakpoints or watchpoints):<br>
|
| 351 |
|
|
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0<br>
|
| 352 |
|
|
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1<br>
|
| 353 |
|
|
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2<br>
|
| 354 |
|
|
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3<br>
|
| 355 |
|
|
//-------------------------------------------------------<br>
|
| 356 |
|
|
// Please keep in mind that hardware breakpoints only<br>
|
| 357 |
|
|
// make sense whenever the program memory is not an SRAM<br>
|
| 358 |
|
|
// (i.e. Flash/OTP/ROM/...) or when you are interested<br>
|
| 359 |
|
|
// in data breakpoints.<br>
|
| 360 |
|
|
//-------------------------------------------------------<br>
|
| 361 |
|
|
//`define DBG_HWBRK_0<br>
|
| 362 |
|
|
//`define DBG_HWBRK_1<br>
|
| 363 |
|
|
//`define DBG_HWBRK_2<br>
|
| 364 |
|
|
//`define DBG_HWBRK_3<br>
|
| 365 |
|
|
<br>
|
| 366 |
|
|
<br>
|
| 367 |
|
|
//-------------------------------------------------------<br>
|
| 368 |
|
|
// Enable/Disable the hardware breakpoint RANGE mode<br>
|
| 369 |
|
|
//-------------------------------------------------------<br>
|
| 370 |
|
|
// When enabled this feature allows the hardware breakpoint<br>
|
| 371 |
|
|
// units to stop the cpu whenever an instruction or data<br>
|
| 372 |
|
|
// access lays within an address range.<br>
|
| 373 |
|
|
// Note that this feature is not supported by GDB.<br>
|
| 374 |
|
|
//-------------------------------------------------------<br>
|
| 375 |
|
|
//`define DBG_HWBRK_RANGE<br>
|
| 376 |
|
|
<br>
|
| 377 |
|
|
<br>
|
| 378 |
|
|
//-------------------------------------------------------<br>
|
| 379 |
|
|
// ASIC version<br>
|
| 380 |
|
|
//-------------------------------------------------------<br>
|
| 381 |
|
|
// When uncommented, this define will enable the<br>
|
| 382 |
|
|
// ASIC system configuration section (see below) and<br>
|
| 383 |
|
|
// will activate scan support for production test.<br>
|
| 384 |
|
|
//<br>
|
| 385 |
|
|
// WARNING: if you target an FPGA, leave this define<br>
|
| 386 |
|
|
// commented.<br>
|
| 387 |
|
|
//-------------------------------------------------------<br>
|
| 388 |
|
|
//`define ASIC<br></code></td></tr></tbody></table><br><br>
|
| 389 |
116 |
olivier.gi |
Design consideration at this stage are:
|
| 390 |
|
|
<ul>
|
| 391 |
|
|
<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
|
| 392 |
|
|
</ul>
|
| 393 |
135 |
olivier.gi |
<br>
|
| 394 |
|
|
All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
|
| 395 |
|
|
<br><br>
|
| 396 |
50 |
olivier.gi |
|
| 397 |
116 |
olivier.gi |
<a name="2.1.4 Memory mapping"></a>
|
| 398 |
|
|
<h3>2.1.4 Memory mapping</h3>
|
| 399 |
50 |
olivier.gi |
|
| 400 |
135 |
olivier.gi |
As discussed earlier, the openMSP430 memory mapping is fully configurable.<br>The
|
| 401 |
|
|
basic system configuration section allows to adjust program and data
|
| 402 |
|
|
memory sizes while keeping 100% compatibility with the pre-existing
|
| 403 |
|
|
linker scripts provided by MSPGCC (or any other toolchain for that
|
| 404 |
|
|
matter).<br>
|
| 405 |
|
|
However, an increasing number of users saw the 512B space available for
|
| 406 |
|
|
peripherals in the standard MSP430 architecture as a limitation.
|
| 407 |
|
|
Therefore, the advanced system configuration section gives the
|
| 408 |
|
|
possibility to up-scale the reserved peripheral address space anywhere
|
| 409 |
|
|
between 512B and 32kB. As a consequence, the data memory space will be
|
| 410 |
|
|
shifted up, which means that the linker script of your favorite
|
| 411 |
|
|
toolchain will have to be modified accordingly.<br>
|
| 412 |
|
|
The following schematic should hopefully illustrate this:<br>
|
| 413 |
|
|
<br><br>
|
| 414 |
|
|
<img src="usercontent,img,1306066277" alt="Memory mapping" title="Memory mapping" width="80%">
|
| 415 |
|
|
<br>
|
| 416 |
116 |
olivier.gi |
|
| 417 |
135 |
olivier.gi |
<br><br>
|
| 418 |
116 |
olivier.gi |
<a name="2.1.5 Pinout"></a>
|
| 419 |
|
|
<h3>2.1.5 Pinout</h3>
|
| 420 |
|
|
|
| 421 |
50 |
olivier.gi |
The full pinout of the openMSP430 core is provided in the following table:
|
| 422 |
135 |
olivier.gi |
<br><br>
|
| 423 |
50 |
olivier.gi |
<table border="1">
|
| 424 |
135 |
olivier.gi |
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td style="vertical-align: top; text-align: center;"><span style="font-weight: bold;">Clock</span><br style="font-weight: bold;">
|
| 425 |
|
|
<span style="font-weight: bold;">Domain</span><br>
|
| 426 |
|
|
</td>
|
| 427 |
|
|
<td align="center"><b>Description</b></td> </tr>
|
| 428 |
50 |
olivier.gi |
|
| 429 |
135 |
olivier.gi |
<tr> <td colspan="5" align="center"> <b><i>Clocks & Power-Managment</i></b> </td></tr>
|
| 430 |
50 |
olivier.gi |
<tr>
|
| 431 |
116 |
olivier.gi |
<td> cpu_en </td>
|
| 432 |
|
|
<td> Input </td>
|
| 433 |
|
|
<td> 1 </td>
|
| 434 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 435 |
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
| 436 |
|
|
<td> Enable CPU code execution (asynchronous and non-glitchy).<br>
|
| 437 |
|
|
Set to 1 if unused. </td>
|
| 438 |
116 |
olivier.gi |
</tr>
|
| 439 |
|
|
<tr>
|
| 440 |
50 |
olivier.gi |
<td> dco_clk </td>
|
| 441 |
|
|
<td> Input </td>
|
| 442 |
|
|
<td> 1 </td>
|
| 443 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">-<br>
|
| 444 |
|
|
</td>
|
| 445 |
|
|
<td> Fast oscillator (fast clock) </td>
|
| 446 |
50 |
olivier.gi |
</tr>
|
| 447 |
|
|
<tr>
|
| 448 |
135 |
olivier.gi |
<td style="vertical-align: top;"> lfxt_clk</td>
|
| 449 |
|
|
<td style="vertical-align: top;">Input<br>
|
| 450 |
|
|
</td>
|
| 451 |
|
|
<td style="vertical-align: top;">1<br>
|
| 452 |
|
|
</td>
|
| 453 |
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
| 454 |
|
|
</td>
|
| 455 |
|
|
<td style="vertical-align: top;"> Low frequency oscillator (typ. 32kHz)<br>
|
| 456 |
|
|
Set to 0 if unused.<br>
|
| 457 |
|
|
</td>
|
| 458 |
|
|
</tr>
|
| 459 |
|
|
<tr>
|
| 460 |
|
|
<td style="vertical-align: top;"> mclk</td>
|
| 461 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 462 |
|
|
</td>
|
| 463 |
|
|
<td style="vertical-align: top;">1<br>
|
| 464 |
|
|
</td>
|
| 465 |
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
| 466 |
|
|
</td>
|
| 467 |
|
|
<td style="vertical-align: top;"> Main system clock</td>
|
| 468 |
|
|
</tr>
|
| 469 |
|
|
<tr>
|
| 470 |
|
|
<td style="vertical-align: top;"> aclk_en</td>
|
| 471 |
|
|
<td style="vertical-align: top;">Output</td>
|
| 472 |
|
|
<td style="vertical-align: top;">1<br>
|
| 473 |
|
|
</td>
|
| 474 |
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 475 |
|
|
</td>
|
| 476 |
|
|
<td style="vertical-align: top;">FPGA ONLY: ACLK enable</td>
|
| 477 |
|
|
</tr>
|
| 478 |
|
|
<tr>
|
| 479 |
|
|
<td style="vertical-align: top;">smclk_en</td>
|
| 480 |
|
|
<td style="vertical-align: top;">Output</td>
|
| 481 |
|
|
<td style="vertical-align: top;">1<br>
|
| 482 |
|
|
</td>
|
| 483 |
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 484 |
|
|
</td>
|
| 485 |
|
|
<td style="vertical-align: top;">FPGA ONLY: SMCLK enable</td>
|
| 486 |
|
|
</tr>
|
| 487 |
|
|
<tr>
|
| 488 |
|
|
<td style="vertical-align: top;">dco_enable<br>
|
| 489 |
|
|
</td>
|
| 490 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 491 |
|
|
</td>
|
| 492 |
|
|
<td style="vertical-align: top;">1<br>
|
| 493 |
|
|
</td>
|
| 494 |
|
|
<td style="vertical-align: top; text-align: center;">dco_clk<br>
|
| 495 |
|
|
</td>
|
| 496 |
|
|
<td style="vertical-align: top;">ASIC ONLY: Fast oscillator enable<br>
|
| 497 |
|
|
</td>
|
| 498 |
|
|
</tr>
|
| 499 |
|
|
<tr>
|
| 500 |
|
|
<td style="vertical-align: top;">dco_wkup<br>
|
| 501 |
|
|
</td>
|
| 502 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 503 |
|
|
</td>
|
| 504 |
|
|
<td style="vertical-align: top;">1<br>
|
| 505 |
|
|
</td>
|
| 506 |
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 507 |
|
|
</td>
|
| 508 |
|
|
<td style="vertical-align: top;">ASIC ONLY: Fast oscillator wakeup (asynchronous)<br>
|
| 509 |
|
|
</td>
|
| 510 |
|
|
</tr>
|
| 511 |
|
|
|
| 512 |
50 |
olivier.gi |
<tr>
|
| 513 |
135 |
olivier.gi |
<td style="vertical-align: top;">lfxt_enable<br>
|
| 514 |
|
|
</td>
|
| 515 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 516 |
|
|
</td>
|
| 517 |
|
|
<td style="vertical-align: top;">1<br>
|
| 518 |
|
|
</td>
|
| 519 |
|
|
<td style="vertical-align: top; text-align: center;">lfxt_clk<br>
|
| 520 |
|
|
</td>
|
| 521 |
|
|
<td style="vertical-align: top;">ASIC ONLY: Low frequency oscillator enable<br>
|
| 522 |
|
|
</td>
|
| 523 |
|
|
</tr>
|
| 524 |
|
|
<tr>
|
| 525 |
|
|
<td style="vertical-align: top;">lfxt_wkup<br>
|
| 526 |
|
|
</td>
|
| 527 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 528 |
|
|
</td>
|
| 529 |
|
|
<td style="vertical-align: top;">1<br>
|
| 530 |
|
|
</td>
|
| 531 |
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 532 |
|
|
</td>
|
| 533 |
|
|
<td style="vertical-align: top;">ASIC ONLY: Low frequency oscillator wakeup (asynchronous)<br>
|
| 534 |
|
|
</td>
|
| 535 |
|
|
</tr>
|
| 536 |
|
|
|
| 537 |
50 |
olivier.gi |
<tr>
|
| 538 |
135 |
olivier.gi |
<td style="vertical-align: top;">aclk<br>
|
| 539 |
|
|
</td>
|
| 540 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 541 |
|
|
</td>
|
| 542 |
|
|
<td style="vertical-align: top;">1<br>
|
| 543 |
|
|
</td>
|
| 544 |
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
| 545 |
|
|
</td>
|
| 546 |
|
|
<td style="vertical-align: top;">ASIC ONLY: ACLK<br>
|
| 547 |
|
|
</td>
|
| 548 |
|
|
</tr>
|
| 549 |
|
|
|
| 550 |
50 |
olivier.gi |
<tr>
|
| 551 |
135 |
olivier.gi |
<td style="vertical-align: top;">smclk<br>
|
| 552 |
|
|
</td>
|
| 553 |
|
|
<td style="vertical-align: top;">Output<br>
|
| 554 |
|
|
</td>
|
| 555 |
|
|
<td style="vertical-align: top;">1<br>
|
| 556 |
|
|
</td>
|
| 557 |
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
| 558 |
|
|
</td>
|
| 559 |
|
|
<td style="vertical-align: top;">ASIC ONLY: SMCLK<br>
|
| 560 |
|
|
</td>
|
| 561 |
|
|
</tr>
|
| 562 |
50 |
olivier.gi |
|
| 563 |
135 |
olivier.gi |
|
| 564 |
50 |
olivier.gi |
<tr>
|
| 565 |
135 |
olivier.gi |
<td style="vertical-align: top;">wkup<br>
|
| 566 |
|
|
</td>
|
| 567 |
|
|
<td style="vertical-align: top;">Input<br>
|
| 568 |
|
|
</td>
|
| 569 |
|
|
<td style="vertical-align: top;">1<br>
|
| 570 |
|
|
</td>
|
| 571 |
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 572 |
|
|
</td>
|
| 573 |
|
|
<td style="vertical-align: top;">ASIC ONLY: System Wake-up (asynchronous and non-glitchy)<br>
|
| 574 |
|
|
Set to 0 if unused.<br>
|
| 575 |
|
|
</td>
|
| 576 |
|
|
</tr>
|
| 577 |
|
|
<tr> <td colspan="5" align="center"> <b><i>Resets</i></b> </td></tr>
|
| 578 |
|
|
<tr>
|
| 579 |
116 |
olivier.gi |
<td> puc_rst </td>
|
| 580 |
50 |
olivier.gi |
<td> Output </td>
|
| 581 |
|
|
<td> 1 </td>
|
| 582 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 583 |
|
|
</td>
|
| 584 |
|
|
<td> Main system reset </td>
|
| 585 |
50 |
olivier.gi |
</tr>
|
| 586 |
|
|
<tr>
|
| 587 |
|
|
<td> reset_n </td>
|
| 588 |
|
|
<td> Input </td>
|
| 589 |
|
|
<td> 1 </td>
|
| 590 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 591 |
|
|
</td>
|
| 592 |
|
|
<td> Reset Pin (active low, asynchronous and non-glitchy) </td>
|
| 593 |
50 |
olivier.gi |
</tr>
|
| 594 |
|
|
|
| 595 |
|
|
|
| 596 |
135 |
olivier.gi |
<tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
| 597 |
50 |
olivier.gi |
<tr>
|
| 598 |
|
|
<td> pmem_addr </td>
|
| 599 |
|
|
<td> Output </td>
|
| 600 |
135 |
olivier.gi |
<td><small> `PMEM_AWIDTH</small> <b><sup><font color="#ff0000">1</font></sup></b> </td>
|
| 601 |
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 602 |
|
|
</td>
|
| 603 |
|
|
<td> Program Memory address </td>
|
| 604 |
50 |
olivier.gi |
</tr>
|
| 605 |
|
|
<tr>
|
| 606 |
|
|
<td> pmem_cen </td>
|
| 607 |
|
|
<td> Output </td>
|
| 608 |
|
|
<td> 1 </td>
|
| 609 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 610 |
|
|
</td>
|
| 611 |
|
|
<td> Program Memory chip enable (low active) </td>
|
| 612 |
50 |
olivier.gi |
</tr>
|
| 613 |
|
|
<tr>
|
| 614 |
|
|
<td> pmem_din </td>
|
| 615 |
|
|
<td> Output </td>
|
| 616 |
|
|
<td> 16 </td>
|
| 617 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 618 |
|
|
</td>
|
| 619 |
|
|
<td> Program Memory data input (optional <b><sup><font color="#ff0000">2</font></sup></b>)</td>
|
| 620 |
50 |
olivier.gi |
</tr>
|
| 621 |
|
|
<tr>
|
| 622 |
|
|
<td> pmem_dout </td>
|
| 623 |
|
|
<td> Input </td>
|
| 624 |
|
|
<td> 16 </td>
|
| 625 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 626 |
|
|
</td>
|
| 627 |
|
|
<td> Program Memory data output </td>
|
| 628 |
50 |
olivier.gi |
</tr>
|
| 629 |
|
|
<tr>
|
| 630 |
|
|
<td> pmem_wen </td>
|
| 631 |
|
|
<td> Output </td>
|
| 632 |
|
|
<td> 2 </td>
|
| 633 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 634 |
|
|
</td>
|
| 635 |
|
|
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#ff0000">2</font></sup></b>) </td>
|
| 636 |
50 |
olivier.gi |
</tr>
|
| 637 |
|
|
|
| 638 |
135 |
olivier.gi |
<tr> <td colspan="5" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
| 639 |
50 |
olivier.gi |
<tr>
|
| 640 |
|
|
<td> dmem_addr </td>
|
| 641 |
|
|
<td> Output </td>
|
| 642 |
135 |
olivier.gi |
<td><small> `DMEM_AWIDTH</small> <b><sup><font color="#ff0000">1</font></sup></b></td>
|
| 643 |
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 644 |
|
|
</td>
|
| 645 |
|
|
<td> Data Memory address </td>
|
| 646 |
50 |
olivier.gi |
</tr>
|
| 647 |
|
|
<tr>
|
| 648 |
|
|
<td> dmem_cen </td>
|
| 649 |
|
|
<td> Output </td>
|
| 650 |
|
|
<td> 1 </td>
|
| 651 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 652 |
|
|
</td>
|
| 653 |
|
|
<td> Data Memory chip enable (low active) </td>
|
| 654 |
50 |
olivier.gi |
</tr>
|
| 655 |
|
|
<tr>
|
| 656 |
|
|
<td> dmem_din </td>
|
| 657 |
|
|
<td> Output </td>
|
| 658 |
|
|
<td> 16 </td>
|
| 659 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 660 |
|
|
</td>
|
| 661 |
|
|
<td> Data Memory data input </td>
|
| 662 |
50 |
olivier.gi |
</tr>
|
| 663 |
|
|
<tr>
|
| 664 |
|
|
<td> dmem_dout </td>
|
| 665 |
|
|
<td> Input </td>
|
| 666 |
|
|
<td> 16 </td>
|
| 667 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 668 |
|
|
</td>
|
| 669 |
|
|
<td> Data Memory data output </td>
|
| 670 |
50 |
olivier.gi |
</tr>
|
| 671 |
|
|
<tr>
|
| 672 |
|
|
<td> dmem_wen </td>
|
| 673 |
|
|
<td> Output </td>
|
| 674 |
|
|
<td> 2 </td>
|
| 675 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 676 |
|
|
</td>
|
| 677 |
|
|
<td> Data Memory write byte enable (low active) </td>
|
| 678 |
50 |
olivier.gi |
</tr>
|
| 679 |
|
|
|
| 680 |
135 |
olivier.gi |
<tr> <td colspan="5" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 681 |
50 |
olivier.gi |
<tr>
|
| 682 |
|
|
<td> per_addr </td>
|
| 683 |
|
|
<td> Output </td>
|
| 684 |
116 |
olivier.gi |
<td> 14 </td>
|
| 685 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 686 |
|
|
</td>
|
| 687 |
|
|
<td> Peripheral address </td>
|
| 688 |
50 |
olivier.gi |
</tr>
|
| 689 |
|
|
<tr>
|
| 690 |
|
|
<td> per_din </td>
|
| 691 |
|
|
<td> Output </td>
|
| 692 |
|
|
<td> 16 </td>
|
| 693 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 694 |
|
|
</td>
|
| 695 |
|
|
<td> Peripheral data input </td>
|
| 696 |
50 |
olivier.gi |
</tr>
|
| 697 |
|
|
<tr>
|
| 698 |
|
|
<td> per_dout </td>
|
| 699 |
|
|
<td> Input </td>
|
| 700 |
|
|
<td> 16 </td>
|
| 701 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 702 |
|
|
</td>
|
| 703 |
|
|
<td> Peripheral data output </td>
|
| 704 |
50 |
olivier.gi |
</tr>
|
| 705 |
|
|
<tr>
|
| 706 |
|
|
<td> per_en </td>
|
| 707 |
|
|
<td> Output </td>
|
| 708 |
|
|
<td> 1 </td>
|
| 709 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 710 |
|
|
</td>
|
| 711 |
|
|
<td> Peripheral enable (high active) </td>
|
| 712 |
50 |
olivier.gi |
</tr>
|
| 713 |
|
|
<tr>
|
| 714 |
116 |
olivier.gi |
<td> per_we </td>
|
| 715 |
50 |
olivier.gi |
<td> Output </td>
|
| 716 |
|
|
<td> 2 </td>
|
| 717 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 718 |
|
|
</td>
|
| 719 |
|
|
<td> Peripheral write enable (high active) </td>
|
| 720 |
50 |
olivier.gi |
</tr>
|
| 721 |
|
|
|
| 722 |
135 |
olivier.gi |
<tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 723 |
50 |
olivier.gi |
<tr>
|
| 724 |
|
|
<td> irq </td>
|
| 725 |
|
|
<td> Input </td>
|
| 726 |
|
|
<td> 14 </td>
|
| 727 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 728 |
|
|
</td>
|
| 729 |
|
|
<td> Maskable interrupts (one-hot signal) </td>
|
| 730 |
50 |
olivier.gi |
</tr>
|
| 731 |
|
|
<tr>
|
| 732 |
|
|
<td> nmi </td>
|
| 733 |
|
|
<td> Input </td>
|
| 734 |
|
|
<td> 1 </td>
|
| 735 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 736 |
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
| 737 |
|
|
<td> Non-maskable interrupt (asynchronous and non-glitchy)<br>
|
| 738 |
|
|
Set to 0 if unused.<br>
|
| 739 |
|
|
</td>
|
| 740 |
50 |
olivier.gi |
</tr>
|
| 741 |
|
|
<tr>
|
| 742 |
|
|
<td> irq_acc </td>
|
| 743 |
|
|
<td> Output </td>
|
| 744 |
|
|
<td> 14 </td>
|
| 745 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 746 |
|
|
</td>
|
| 747 |
|
|
<td> Interrupt request accepted (one-hot signal) </td>
|
| 748 |
50 |
olivier.gi |
</tr>
|
| 749 |
|
|
|
| 750 |
135 |
olivier.gi |
<tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
| 751 |
50 |
olivier.gi |
<tr>
|
| 752 |
116 |
olivier.gi |
<td> dbg_en </td>
|
| 753 |
|
|
<td> Input </td>
|
| 754 |
|
|
<td> 1 </td>
|
| 755 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 756 |
|
|
|
| 757 |
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
| 758 |
|
|
<td> Debug interface enable (asynchronous) <b><sup><font color="#ff0000">3</font></sup></b> </td>
|
| 759 |
116 |
olivier.gi |
</tr>
|
| 760 |
|
|
<tr>
|
| 761 |
50 |
olivier.gi |
<td> dbg_freeze </td>
|
| 762 |
|
|
<td> Output </td>
|
| 763 |
|
|
<td> 1 </td>
|
| 764 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 765 |
|
|
</td>
|
| 766 |
|
|
<td> Freeze peripherals </td>
|
| 767 |
50 |
olivier.gi |
</tr>
|
| 768 |
|
|
<tr>
|
| 769 |
|
|
<td> dbg_uart_txd </td>
|
| 770 |
|
|
<td> Output </td>
|
| 771 |
|
|
<td> 1 </td>
|
| 772 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;">mclk<br>
|
| 773 |
|
|
</td>
|
| 774 |
|
|
<td> Debug interface: UART TXD </td>
|
| 775 |
50 |
olivier.gi |
</tr>
|
| 776 |
|
|
<tr>
|
| 777 |
|
|
<td> dbg_uart_rxd </td>
|
| 778 |
|
|
<td> Input </td>
|
| 779 |
|
|
<td> 1 </td>
|
| 780 |
135 |
olivier.gi |
<td style="vertical-align: top; text-align: center;"><async><br>
|
| 781 |
|
|
</td>
|
| 782 |
|
|
<td> Debug interface: UART RXD (asynchronous) </td>
|
| 783 |
|
|
</tr><tr align="center">
|
| 784 |
|
|
<td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
|
| 785 |
|
|
</tr>
|
| 786 |
|
|
<tr>
|
| 787 |
|
|
<td style="vertical-align: top;">scan_enable<br>
|
| 788 |
|
|
</td>
|
| 789 |
|
|
<td style="vertical-align: top;">Input<br>
|
| 790 |
|
|
</td>
|
| 791 |
|
|
<td style="vertical-align: top;">1<br>
|
| 792 |
|
|
</td>
|
| 793 |
|
|
<td style="vertical-align: top; text-align: center;">dco_clk<br>
|
| 794 |
|
|
</td>
|
| 795 |
|
|
<td style="vertical-align: top;">ASIC ONLY: Scan enable (active during scan shifting)<br>
|
| 796 |
|
|
</td>
|
| 797 |
|
|
</tr>
|
| 798 |
|
|
<tr>
|
| 799 |
|
|
<td style="vertical-align: top;">scan_mode<br>
|
| 800 |
|
|
</td>
|
| 801 |
|
|
<td style="vertical-align: top;">Input<br>
|
| 802 |
|
|
</td>
|
| 803 |
|
|
<td style="vertical-align: top;">1<br>
|
| 804 |
|
|
</td>
|
| 805 |
|
|
<td style="vertical-align: top; text-align: center;"><stable><br>
|
| 806 |
|
|
</td>
|
| 807 |
|
|
<td style="vertical-align: top;">ASIC ONLY: Scan mode<br>
|
| 808 |
|
|
</td>
|
| 809 |
|
|
</tr>
|
| 810 |
50 |
olivier.gi |
|
| 811 |
135 |
olivier.gi |
</tbody></table>
|
| 812 |
|
|
<br>
|
| 813 |
|
|
<b><sup><font color="#ff0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br>
|
| 814 |
|
|
<b><sup><font color="#ff0000">2</font></sup></b>: These two optional
|
| 815 |
|
|
ports can be connected whenever the program memory is a RAM. This will
|
| 816 |
|
|
allow the user to load a program through the serial debug interface and
|
| 817 |
|
|
to use software breakpoints.<br>
|
| 818 |
|
|
<b><sup><font color="#ff0000">3</font></sup></b>: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br>
|
| 819 |
|
|
<b><sup><font color="#ff0000">4</font></sup></b>: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).<br>
|
| 820 |
|
|
<br>
|
| 821 |
|
|
<span style="text-decoration: underline; font-weight: bold;">Note:</span> in the FPGA configuration, the <span style="font-style: italic;">ASIC ONLY</span> signals must be left unconnected (for the outputs) and tied low (for the inputs).<br>
|
| 822 |
|
|
|
| 823 |
116 |
olivier.gi |
<a name="2.1.6 Instruction Cycles and Lengths"></a>
|
| 824 |
|
|
<h3>2.1.6 Instruction Cycles and Lengths</h3>
|
| 825 |
50 |
olivier.gi |
|
| 826 |
135 |
olivier.gi |
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br><br>
|
| 827 |
|
|
The number of CPU clock cycles required for an instruction depends on
|
| 828 |
|
|
the instruction format and the addressing modes used, not the
|
| 829 |
|
|
instruction itself.<br>
|
| 830 |
116 |
olivier.gi |
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
| 831 |
50 |
olivier.gi |
Differences with the original MSP430 are highlighted in green (the original value being red).
|
| 832 |
|
|
<ul>
|
| 833 |
|
|
<li><b>Interrupt and Reset Cycles</b></li>
|
| 834 |
|
|
</ul>
|
| 835 |
|
|
<table border="1">
|
| 836 |
135 |
olivier.gi |
<tbody><tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
|
| 837 |
50 |
olivier.gi |
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
|
| 838 |
|
|
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
|
| 839 |
|
|
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
| 840 |
|
|
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
| 841 |
135 |
olivier.gi |
</tbody></table>
|
| 842 |
50 |
olivier.gi |
|
| 843 |
|
|
<ul>
|
| 844 |
|
|
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
|
| 845 |
|
|
</ul>
|
| 846 |
|
|
<table border="1">
|
| 847 |
135 |
olivier.gi |
<tbody><tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
| 848 |
50 |
olivier.gi |
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
|
| 849 |
|
|
|
| 850 |
|
|
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 851 |
|
|
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
|
| 852 |
|
|
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 853 |
|
|
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 854 |
|
|
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 855 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 856 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 857 |
|
|
</tbody></table>
|
| 858 |
50 |
olivier.gi |
|
| 859 |
|
|
<ul>
|
| 860 |
|
|
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
|
| 861 |
|
|
</ul>
|
| 862 |
|
|
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
|
| 863 |
|
|
|
| 864 |
|
|
<ul>
|
| 865 |
|
|
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
|
| 866 |
|
|
</ul>
|
| 867 |
|
|
<table border="1">
|
| 868 |
135 |
olivier.gi |
<tbody><tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
| 869 |
50 |
olivier.gi |
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
|
| 870 |
|
|
|
| 871 |
|
|
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
|
| 872 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 873 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 874 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 875 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 876 |
50 |
olivier.gi |
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 877 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 878 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 879 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 880 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 881 |
50 |
olivier.gi |
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 882 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
|
| 883 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 884 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 885 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 886 |
50 |
olivier.gi |
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
|
| 887 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 888 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 889 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 890 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 891 |
50 |
olivier.gi |
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 892 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
| 893 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 894 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 895 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 896 |
50 |
olivier.gi |
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 897 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
| 898 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 899 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 900 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 901 |
|
|
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 902 |
50 |
olivier.gi |
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 903 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 904 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 905 |
135 |
olivier.gi |
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 906 |
|
|
</tbody></table>
|
| 907 |
50 |
olivier.gi |
|
| 908 |
116 |
olivier.gi |
<a name="2.1.7 Serial Debug Interface"></a>
|
| 909 |
|
|
<h3>2.1.7 Serial Debug Interface</h3>
|
| 910 |
50 |
olivier.gi |
|
| 911 |
135 |
olivier.gi |
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
|
| 912 |
|
|
<br>
|
| 913 |
|
|
<a name="2.2_System_Peripherals"></a>
|
| 914 |
|
|
<h2>2.2 System Peripherals</h2>
|
| 915 |
|
|
In addition to the CPU core itself, several peripherals are also
|
| 916 |
|
|
provided and can be easily connected to the core during integration.
|
| 917 |
|
|
The followings are directly integrated within the core because of their
|
| 918 |
|
|
tight links with the CPU.<br>
|
| 919 |
|
|
It is to be noted that <span style="font-weight: bold;">ALL</span> system peripherals support both ASIC and FPGA versions.<br>
|
| 920 |
50 |
olivier.gi |
<a name="2.2.1 Basic Clock Module"></a>
|
| 921 |
135 |
olivier.gi |
<h3>2.2.1 Basic Clock Module: FPGA<br>
|
| 922 |
|
|
</h3>In order to make an FPGA
|
| 923 |
|
|
implementation as simple as possible (ideally, a non-professional designer should be
|
| 924 |
|
|
able to do it), clock gates are not used in this design configuration and neither are
|
| 925 |
|
|
clock muxes.
|
| 926 |
|
|
<br>
|
| 927 |
50 |
olivier.gi |
With these constrains, the Basic Clock Module is implemented as following:
|
| 928 |
135 |
olivier.gi |
<br><br>
|
| 929 |
|
|
<img src="usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="80%">
|
| 930 |
|
|
<br>
|
| 931 |
|
|
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the
|
| 932 |
|
|
CPU state machines in an IDLE state while MCLK will still be running.
|
| 933 |
|
|
<br><br>
|
| 934 |
50 |
olivier.gi |
|
| 935 |
|
|
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
|
| 936 |
135 |
olivier.gi |
<br><br>
|
| 937 |
|
|
<img src="usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example">
|
| 938 |
|
|
<br><br>For example, the following Verilog code would implement a counter clocked with SMCLK:
|
| 939 |
|
|
<br>
|
| 940 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 941 |
|
|
<tbody><tr>
|
| 942 |
|
|
<td width="35"><br>
|
| 943 |
|
|
</td>
|
| 944 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 945 |
|
|
</td>
|
| 946 |
|
|
<td width="15"><br>
|
| 947 |
|
|
</td>
|
| 948 |
50 |
olivier.gi |
<td>
|
| 949 |
|
|
<code>
|
| 950 |
|
|
reg [7:0] test_cnt;
|
| 951 |
135 |
olivier.gi |
<br>
|
| 952 |
|
|
<br>always @ (posedge mclk or posedge puc_rst)
|
| 953 |
|
|
<br> if (puc_rst) test_cnt <= 8'h00;
|
| 954 |
|
|
<br> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
| 955 |
50 |
olivier.gi |
</code>
|
| 956 |
|
|
</td>
|
| 957 |
|
|
</tr>
|
| 958 |
135 |
olivier.gi |
</tbody></table>
|
| 959 |
|
|
<br><br>
|
| 960 |
50 |
olivier.gi |
<b>Register Description</b>
|
| 961 |
|
|
<ul>
|
| 962 |
|
|
<li>DCOCTL: Not implemented</li>
|
| 963 |
|
|
<li>BCSCTL1:
|
| 964 |
|
|
<ul>
|
| 965 |
|
|
<li>BCSCTL1[7:6]: Unused</li>
|
| 966 |
|
|
<li>BCSCTL1[5:4]: DIVAx</li>
|
| 967 |
|
|
<li>BCSCTL1[4:0]: Unused</li>
|
| 968 |
|
|
</ul>
|
| 969 |
|
|
</li>
|
| 970 |
|
|
<li>BCSCTL2:
|
| 971 |
|
|
<ul>
|
| 972 |
|
|
<li>BCSCTL2[7:4]: Unused</li>
|
| 973 |
|
|
<li>BCSCTL2[3] : SELS</li>
|
| 974 |
|
|
<li>BCSCTL2[2:1]: DIVSx</li>
|
| 975 |
|
|
<li>BCSCTL2[0] : Unused</li>
|
| 976 |
135 |
olivier.gi |
</ul></li>
|
| 977 |
|
|
</ul><a name="2.2.2_Basic_Clock_Module_ASIC"></a>
|
| 978 |
|
|
<h3>2.2.2 Basic Clock Module: ASIC<br>
|
| 979 |
|
|
</h3>
|
| 980 |
|
|
When targeting an ASIC, up to all clock management
|
| 981 |
|
|
options available in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 4) can be included:<br><br>
|
| 982 |
50 |
olivier.gi |
|
| 983 |
135 |
olivier.gi |
<img src="usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="80%"><br>
|
| 984 |
|
|
Additional info can be found in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
|
| 985 |
|
|
section.<br>
|
| 986 |
|
|
<br>
|
| 987 |
|
|
<a name="2.2.3_SFR"></a>
|
| 988 |
|
|
<h3>2.2.3 SFR</h3>Following the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a>, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:<br>
|
| 989 |
|
|
<br>
|
| 990 |
|
|
<table border="1">
|
| 991 |
|
|
|
| 992 |
|
|
|
| 993 |
|
|
<tbody><tr align="center">
|
| 994 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 995 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 996 |
|
|
<td colspan="8" rowspan="1" style="vertical-align: top;"><small style="font-weight: bold;">Bit Fields</small><br>
|
| 997 |
|
|
</td>
|
| 998 |
|
|
|
| 999 |
|
|
</tr>
|
| 1000 |
|
|
<tr align="center">
|
| 1001 |
|
|
|
| 1002 |
|
|
|
| 1003 |
|
|
|
| 1004 |
|
|
|
| 1005 |
|
|
|
| 1006 |
|
|
|
| 1007 |
|
|
<td style="vertical-align: top;"><small>7<br>
|
| 1008 |
|
|
</small></td>
|
| 1009 |
|
|
<td style="vertical-align: top;"><small>6<br>
|
| 1010 |
|
|
</small></td>
|
| 1011 |
|
|
<td style="vertical-align: top;"><small>5<br>
|
| 1012 |
|
|
</small></td>
|
| 1013 |
|
|
<td style="vertical-align: top;"><small>4<br>
|
| 1014 |
|
|
</small></td>
|
| 1015 |
|
|
<td style="vertical-align: top;"><small>3<br>
|
| 1016 |
|
|
</small></td>
|
| 1017 |
|
|
<td style="vertical-align: top;"><small>2<br>
|
| 1018 |
|
|
</small></td>
|
| 1019 |
|
|
<td style="vertical-align: top;"><small>1<br>
|
| 1020 |
|
|
</small></td>
|
| 1021 |
|
|
<td style="vertical-align: top;"><small>0<br>
|
| 1022 |
|
|
</small></td>
|
| 1023 |
|
|
|
| 1024 |
|
|
|
| 1025 |
|
|
</tr>
|
| 1026 |
|
|
<tr align="center">
|
| 1027 |
|
|
<td>IE1<br>
|
| 1028 |
|
|
</td>
|
| 1029 |
|
|
<td><small>0x0000</small></td>
|
| 1030 |
|
|
|
| 1031 |
|
|
|
| 1032 |
|
|
|
| 1033 |
|
|
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><small> Reserved <br>
|
| 1034 |
|
|
</small></td>
|
| 1035 |
|
|
|
| 1036 |
|
|
|
| 1037 |
|
|
<td style="vertical-align: top;">NMIIE <b><sup><font color="#ff0000">1</font></sup></b></td>
|
| 1038 |
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><small> Reserved </small>
|
| 1039 |
|
|
</td>
|
| 1040 |
|
|
|
| 1041 |
|
|
|
| 1042 |
|
|
<td style="vertical-align: top;">WDTIE <b><sup><font color="#ff0000">2</font></sup></b></td>
|
| 1043 |
|
|
|
| 1044 |
|
|
</tr>
|
| 1045 |
|
|
<tr align="center">
|
| 1046 |
|
|
<td>IFG1<br>
|
| 1047 |
|
|
</td>
|
| 1048 |
|
|
<td><small>0x0002</small></td>
|
| 1049 |
|
|
|
| 1050 |
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small><br>
|
| 1051 |
|
|
|
| 1052 |
|
|
</td>
|
| 1053 |
|
|
|
| 1054 |
|
|
|
| 1055 |
|
|
<td style="vertical-align: top;">NMIIFG <b><sup><font color="#ff0000">1</font></sup></b></td>
|
| 1056 |
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small></td>
|
| 1057 |
|
|
|
| 1058 |
|
|
|
| 1059 |
|
|
<td style="vertical-align: top;">WDTIFG <b><sup><font color="#ff0000">2</font></sup></b></td>
|
| 1060 |
|
|
|
| 1061 |
|
|
|
| 1062 |
|
|
</tr>
|
| 1063 |
|
|
</tbody>
|
| 1064 |
|
|
</table>
|
| 1065 |
|
|
<br>
|
| 1066 |
|
|
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
|
| 1067 |
|
|
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
|
| 1068 |
|
|
<br>
|
| 1069 |
|
|
In addition, two 16-bit read-only registers have been added in order
|
| 1070 |
|
|
to let the software know with which version of the openMSP430 it is
|
| 1071 |
|
|
running:<br>
|
| 1072 |
|
|
<br>
|
| 1073 |
|
|
<table border="1">
|
| 1074 |
|
|
|
| 1075 |
|
|
<tbody><tr align="center">
|
| 1076 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 1077 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 1078 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 1079 |
|
|
</tr>
|
| 1080 |
|
|
<tr align="center">
|
| 1081 |
|
|
<td><small>15</small></td><td><small>14</small></td>
|
| 1082 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 1083 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 1084 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 1085 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 1086 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 1087 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 1088 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 1089 |
|
|
</tr>
|
| 1090 |
|
|
<tr align="center">
|
| 1091 |
|
|
<td><small>CPU_ID_LO</small></td>
|
| 1092 |
|
|
<td><small>0x0004</small></td>
|
| 1093 |
|
|
<td colspan="7"><font size="-5">PER_SPACE</font></td>
|
| 1094 |
|
|
<td colspan="5"><font size="-5">USER_VERSION</font></td>
|
| 1095 |
|
|
<td colspan="1"><font size="-5">ASIC</font></td>
|
| 1096 |
|
|
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
|
| 1097 |
|
|
</tr>
|
| 1098 |
|
|
<tr align="center">
|
| 1099 |
|
|
<td><small>CPU_ID_HI</small></td>
|
| 1100 |
|
|
<td><small>0x0006</small></td>
|
| 1101 |
|
|
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
|
| 1102 |
|
|
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
|
| 1103 |
|
|
<td colspan="1"><font size="-5">MPY</font></td>
|
| 1104 |
|
|
</tr>
|
| 1105 |
|
|
</tbody>
|
| 1106 |
|
|
</table>
|
| 1107 |
|
|
<br>
|
| 1108 |
|
|
<table border="0">
|
| 1109 |
|
|
|
| 1110 |
|
|
<tbody><tr>
|
| 1111 |
|
|
<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td>
|
| 1112 |
|
|
<td>: Current CPU version<br>
|
| 1113 |
|
|
</td>
|
| 1114 |
|
|
</tr>
|
| 1115 |
|
|
<tr>
|
| 1116 |
|
|
<td> </td><td valign="top"><li><b>ASIC</b></li></td>
|
| 1117 |
|
|
<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
|
| 1118 |
|
|
</tr>
|
| 1119 |
|
|
<tr>
|
| 1120 |
|
|
<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td>
|
| 1121 |
|
|
<td>: Reflects the value defined in the <b style="font-style: italic;">openMSP430_defines.v</b> file.</td>
|
| 1122 |
|
|
</tr>
|
| 1123 |
|
|
<tr>
|
| 1124 |
|
|
<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td>
|
| 1125 |
|
|
<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
|
| 1126 |
|
|
</tr>
|
| 1127 |
|
|
<tr>
|
| 1128 |
|
|
<td> </td><td valign="top"><li><b>MPY</b></li></td>
|
| 1129 |
|
|
<td>: This bit is set if the hardware multiplier is included in the current implementation</td>
|
| 1130 |
|
|
</tr>
|
| 1131 |
|
|
<tr>
|
| 1132 |
|
|
<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
|
| 1133 |
|
|
<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
|
| 1134 |
|
|
</tr>
|
| 1135 |
|
|
<tr>
|
| 1136 |
|
|
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
|
| 1137 |
|
|
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
|
| 1138 |
|
|
</tr>
|
| 1139 |
|
|
</tbody>
|
| 1140 |
|
|
</table>
|
| 1141 |
|
|
<br>
|
| 1142 |
|
|
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span> and <span style="font-style: italic;">CPU_ID_HI</span> are identical to the Serial Debug Interface register counterparts.<br>
|
| 1143 |
50 |
olivier.gi |
<a name="2.2.2 Watchdog Timer"></a>
|
| 1144 |
135 |
olivier.gi |
<h3>2.2.4 Watchdog Timer</h3>
|
| 1145 |
50 |
olivier.gi |
|
| 1146 |
|
|
|
| 1147 |
135 |
olivier.gi |
|
| 1148 |
|
|
|
| 1149 |
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.<br>
|
| 1150 |
|
|
|
| 1151 |
|
|
<br>
|
| 1152 |
|
|
|
| 1153 |
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the watchdog timer should be included or not:<br>
|
| 1154 |
|
|
<br>
|
| 1155 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 1156 |
|
|
|
| 1157 |
|
|
<tbody><tr>
|
| 1158 |
|
|
<td width="35"><br>
|
| 1159 |
|
|
</td>
|
| 1160 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 1161 |
|
|
</td>
|
| 1162 |
|
|
<td width="15"><br>
|
| 1163 |
|
|
</td>
|
| 1164 |
|
|
<td>
|
| 1165 |
|
|
<code>//-------------------------------------------------------<br>
|
| 1166 |
|
|
// Include/Exclude Watchdog timer<br>
|
| 1167 |
|
|
//-------------------------------------------------------<br>
|
| 1168 |
|
|
// When excluded, the following functionality will be<br>
|
| 1169 |
|
|
// lost:<br>
|
| 1170 |
|
|
// - Watchog (both interval and watchdog modes)<br>
|
| 1171 |
|
|
// - NMI interrupt edge selection<br>
|
| 1172 |
|
|
// - Possibility to generate a software PUC reset<br>
|
| 1173 |
|
|
//-------------------------------------------------------<br>
|
| 1174 |
|
|
`define WATCHDOG</code></td></tr></tbody>
|
| 1175 |
|
|
</table>
|
| 1176 |
|
|
<br>
|
| 1177 |
|
|
<a name="2.2.5 16x16 Hardware Multiplier"></a>
|
| 1178 |
|
|
<h3>2.2.5 16x16 Hardware Multiplier</h3>
|
| 1179 |
|
|
|
| 1180 |
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
|
| 1181 |
|
|
<br><br>
|
| 1182 |
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not:<br><br>
|
| 1183 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 1184 |
|
|
<tbody><tr>
|
| 1185 |
|
|
<td width="35"><br>
|
| 1186 |
|
|
</td>
|
| 1187 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 1188 |
|
|
</td>
|
| 1189 |
|
|
<td width="15"><br>
|
| 1190 |
|
|
</td>
|
| 1191 |
|
|
<td>
|
| 1192 |
|
|
<code>
|
| 1193 |
|
|
// Include/Exclude Hardware Multiplier
|
| 1194 |
|
|
<br>`define MULTIPLIER
|
| 1195 |
|
|
</code>
|
| 1196 |
|
|
</td>
|
| 1197 |
|
|
</tr>
|
| 1198 |
|
|
</tbody></table>
|
| 1199 |
|
|
<a name="2.3_Peripherals"></a>
|
| 1200 |
|
|
<h2>2.3 External Peripherals</h2>
|
| 1201 |
|
|
The external peripherals labeld with the "FPGA ONLY" tag do not contain
|
| 1202 |
|
|
any clock gate nor clock muxes and are clocked with MCLK only. This
|
| 1203 |
|
|
mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.<br>
|
| 1204 |
|
|
<br>
|
| 1205 |
50 |
olivier.gi |
<a name="2.2.3 Digital I/O"></a>
|
| 1206 |
135 |
olivier.gi |
<h3>2.3.1 Digital I/O (FPGA ONLY)<br>
|
| 1207 |
|
|
</h3>
|
| 1208 |
50 |
olivier.gi |
|
| 1209 |
135 |
olivier.gi |
|
| 1210 |
69 |
olivier.gi |
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
|
| 1211 |
135 |
olivier.gi |
<br>
|
| 1212 |
|
|
<br>
|
| 1213 |
|
|
|
| 1214 |
50 |
olivier.gi |
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
|
| 1215 |
135 |
olivier.gi |
<br>
|
| 1216 |
|
|
<br>
|
| 1217 |
|
|
|
| 1218 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 1219 |
|
|
|
| 1220 |
|
|
<tbody><tr>
|
| 1221 |
|
|
<td width="35"><br>
|
| 1222 |
|
|
</td>
|
| 1223 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 1224 |
|
|
</td>
|
| 1225 |
|
|
<td width="15"><br>
|
| 1226 |
|
|
</td>
|
| 1227 |
50 |
olivier.gi |
<td>
|
| 1228 |
|
|
<code>
|
| 1229 |
|
|
parameter P1_EN = 1'b1; // Enable Port 1
|
| 1230 |
135 |
olivier.gi |
<br>parameter P2_EN = 1'b1; // Enable Port 2
|
| 1231 |
|
|
<br>parameter P3_EN = 1'b0; // Enable Port 3
|
| 1232 |
|
|
<br>parameter P4_EN = 1'b0; // Enable Port 4
|
| 1233 |
|
|
<br>parameter P5_EN = 1'b0; // Enable Port 5
|
| 1234 |
|
|
<br>parameter P6_EN = 1'b0; // Enable Port 6
|
| 1235 |
50 |
olivier.gi |
</code>
|
| 1236 |
|
|
</td>
|
| 1237 |
|
|
</tr>
|
| 1238 |
135 |
olivier.gi |
</tbody>
|
| 1239 |
50 |
olivier.gi |
</table>
|
| 1240 |
135 |
olivier.gi |
|
| 1241 |
|
|
<br>
|
| 1242 |
|
|
|
| 1243 |
50 |
olivier.gi |
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
|
| 1244 |
135 |
olivier.gi |
<br>
|
| 1245 |
|
|
<br>
|
| 1246 |
|
|
|
| 1247 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 1248 |
|
|
|
| 1249 |
|
|
<tbody><tr>
|
| 1250 |
|
|
<td width="35"><br>
|
| 1251 |
|
|
</td>
|
| 1252 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 1253 |
|
|
</td>
|
| 1254 |
|
|
<td width="15"><br>
|
| 1255 |
|
|
</td>
|
| 1256 |
50 |
olivier.gi |
<td>
|
| 1257 |
|
|
<code>
|
| 1258 |
|
|
gpio #(.P1_EN(1),
|
| 1259 |
135 |
olivier.gi |
<br> .P2_EN(1),
|
| 1260 |
|
|
<br> .P3_EN(1),
|
| 1261 |
|
|
<br> .P4_EN(0),
|
| 1262 |
|
|
<br> .P5_EN(0),
|
| 1263 |
|
|
<br> .P6_EN(0)) gpio_0 (
|
| 1264 |
50 |
olivier.gi |
</code>
|
| 1265 |
|
|
</td>
|
| 1266 |
|
|
</tr>
|
| 1267 |
135 |
olivier.gi |
</tbody>
|
| 1268 |
50 |
olivier.gi |
</table>
|
| 1269 |
135 |
olivier.gi |
|
| 1270 |
|
|
<br>
|
| 1271 |
|
|
|
| 1272 |
50 |
olivier.gi |
The full pinout of the GPIO module is provided in the following table:
|
| 1273 |
135 |
olivier.gi |
<br>
|
| 1274 |
|
|
<br>
|
| 1275 |
|
|
|
| 1276 |
50 |
olivier.gi |
<table border="1">
|
| 1277 |
135 |
olivier.gi |
|
| 1278 |
|
|
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 1279 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
| 1280 |
50 |
olivier.gi |
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 1281 |
116 |
olivier.gi |
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 1282 |
50 |
olivier.gi |
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 1283 |
|
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
| 1284 |
|
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
| 1285 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 1286 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 1287 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 1288 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 1289 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 1290 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 1291 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
|
| 1292 |
|
|
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
|
| 1293 |
|
|
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
|
| 1294 |
|
|
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
|
| 1295 |
|
|
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
|
| 1296 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
|
| 1297 |
|
|
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
|
| 1298 |
|
|
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
|
| 1299 |
|
|
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
|
| 1300 |
|
|
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
|
| 1301 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
|
| 1302 |
|
|
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
|
| 1303 |
|
|
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
|
| 1304 |
|
|
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
|
| 1305 |
|
|
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
|
| 1306 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
|
| 1307 |
|
|
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
|
| 1308 |
|
|
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
|
| 1309 |
|
|
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
|
| 1310 |
|
|
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
|
| 1311 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
|
| 1312 |
|
|
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
|
| 1313 |
|
|
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
|
| 1314 |
|
|
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
|
| 1315 |
|
|
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
|
| 1316 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
|
| 1317 |
|
|
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
|
| 1318 |
|
|
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
|
| 1319 |
|
|
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
|
| 1320 |
|
|
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
|
| 1321 |
135 |
olivier.gi |
</tbody>
|
| 1322 |
|
|
</table>
|
| 1323 |
|
|
|
| 1324 |
50 |
olivier.gi |
|
| 1325 |
|
|
<a name="2.2.4 Timer A"></a>
|
| 1326 |
135 |
olivier.gi |
<h3>2.3.2 Timer A (FPGA ONLY)</h3>
|
| 1327 |
50 |
olivier.gi |
|
| 1328 |
135 |
olivier.gi |
|
| 1329 |
|
|
|
| 1330 |
69 |
olivier.gi |
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
|
| 1331 |
135 |
olivier.gi |
<br>
|
| 1332 |
|
|
<br>
|
| 1333 |
|
|
|
| 1334 |
50 |
olivier.gi |
The full pinout of the Timer A module is provided in the following table:
|
| 1335 |
135 |
olivier.gi |
<br>
|
| 1336 |
|
|
<br>
|
| 1337 |
|
|
|
| 1338 |
50 |
olivier.gi |
<table border="1">
|
| 1339 |
135 |
olivier.gi |
|
| 1340 |
|
|
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 1341 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
|
| 1342 |
50 |
olivier.gi |
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 1343 |
|
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
| 1344 |
|
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
| 1345 |
|
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
| 1346 |
|
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
| 1347 |
116 |
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<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 1348 |
50 |
olivier.gi |
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
|
| 1349 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 1350 |
|
|
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
|
| 1351 |
|
|
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
|
| 1352 |
|
|
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
|
| 1353 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 1354 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 1355 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 1356 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 1357 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 1358 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 1359 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
|
| 1360 |
|
|
<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
|
| 1361 |
|
|
<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
|
| 1362 |
|
|
<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
|
| 1363 |
|
|
<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
|
| 1364 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
|
| 1365 |
|
|
<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
|
| 1366 |
|
|
<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
|
| 1367 |
|
|
<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
|
| 1368 |
|
|
<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
|
| 1369 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
|
| 1370 |
|
|
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
|
| 1371 |
|
|
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
|
| 1372 |
|
|
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
|
| 1373 |
|
|
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
|
| 1374 |
135 |
olivier.gi |
</tbody>
|
| 1375 |
69 |
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</table>
|
| 1376 |
135 |
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|
| 1377 |
|
|
<br>
|
| 1378 |
69 |
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|
| 1379 |
135 |
olivier.gi |
<b>Note</b>: for the same reason as with the Basic Clock Module FPGA version, the
|
| 1380 |
|
|
two additional clock inputs (TACLK and INCLK) are internally
|
| 1381 |
|
|
synchronized with the MCLK domain.
|
| 1382 |
|
|
As a consequence, TACLK and INCLK should be at least 2 times slowlier
|
| 1383 |
|
|
than MCLK, and if these clock are used toghether with the Timer A
|
| 1384 |
|
|
output unit, some jitter might be observed on the generated output.
|
| 1385 |
|
|
If this jitter is critical for the application, ACLK and INCLK should
|
| 1386 |
|
|
idealy be derivated from DCO_CLK.
|
| 1387 |
|
|
<br>
|
| 1388 |
|
|
<br>
|
| 1389 |
|
|
<br>
|
| 1390 |
|
|
|
| 1391 |
|
|
<br><br>
|
| 1392 |
|
|
</body></html>
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