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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 Core</title></head>
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<body>
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<h3>Table of content</h3>
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<ul>
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        <li><a href="#1.%20Introduction">1. Introduction</a></li>
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        <li><a href="#2.%20Design">      2. Design</a>
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        <ul>
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      <li><a href="#2.1%20Core">        2.1 Core</a>
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                <ul>
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           <li><a href="#2.1.1%20Design%20structure">              2.1.1 Design structure</a></li>
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           <li><a href="#2.1.2%20Limitations">                   2.1.2 Limitations</a></li>
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           <li><a href="#2.1.3%20Configuration">                 2.1.3 Configuration</a></li>
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           <ul>
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                <li><a href="#2.1.3.1%20Basic%20System%20Configuration">          2.1.3.1 Basic System Configuration</a></li>
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                <li><a href="#2.1.3.2%20Advanced%20System%20Configuration">       2.1.3.2 Advanced System Configuration</a></li>
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                <li><a href="#2.1.3.3%20Expert%20System%20Configuration">         2.1.3.3 Expert System Configuration</a></li>
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                <li><a href="#2.1.3.4%20Parameters%20For%20Multi-Core%20Systems"> 2.1.3.4 Parameters For Multi-Core Systems</a></li>
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           </ul>
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           <li><a href="#2.1.4%20Memory%20mapping">                2.1.4 Memory mapping</a></li>
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           <li><a href="#2.1.5%20Pinout">                        2.1.5 Pinout</a></li>
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           <li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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           <li><a href="#2.1.7%20Serial%20Debug%20Interface">        2.1.7 Serial Debug Interface</a></li>
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           <li><a href="#2.1.8%20Benchmark%20results"> 2.1.8 Benchmark results</a></li>
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           <ul>
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                <li><a href="#2.1.8.1%20Dhrystone">2.1.8.1 Dhrystone</a></li>
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                <li><a href="#2.1.8.2%20CoreMark">2.1.8.2 CoreMark</a></li>
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           </ul>
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                </ul>
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           </li>
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      <li><a href="#2.2_System_Peripherals">        2.2 System Peripherals</a>
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33 
        <ul>
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35 
           <li><a href="#2.2.1%20Basic%20Clock%20Module">            2.2.1 Basic Clock Module: FPGA</a></li>
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          <li><a href="#2.2.2_Basic_Clock_Module_ASIC">            2.2.2 Basic Clock Module: ASIC</a></li>
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          <li><a href="#2.2.3_SFR">2.2.3 SFR</a><br>
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          </li>
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           <li><a href="#2.2.2%20Watchdog%20Timer">                2.2.4 Watchdog Timer</a></li>
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          <li><a href="core.html#2.2.5%2016x16%20Hardware%20Multiplier">     2.2.5 16x16 Hardware Multiplier</a></li>
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        </ul>
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</li>
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      <li><a href="#2.3_Peripherals">        2.3 External Peripherals</a></li>
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      <ul>
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        <li><a href="core.html#2.2.3%20Digital%20I/O">2.3.1 Digital I/O (FPGA ONLY)</a></li>
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        <li><a href="core.html#2.2.4%20Timer%20A">                       2.3.2 Timer A (FPGA ONLY)</a></li>
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      </ul>
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</ul></li>
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</ul>
52 
 
53 
<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b>
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(note that the extended version of the architecture, the MSP430X, isn't
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supported by this IP). It is based on a Von Neumann architecture, with
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a single address space for instructions and data.
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<br><br>Depending on the selected configuration, this design can either be:<br>
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<ul>
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  <ul>
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    <ul>
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      <li>&nbsp;<span style="font-weight: bold;">FPGA friendly</span>: the core doesn't contain any clock gate and has only a single clock
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domain. As a consequence, in this mode, the <span style="font-style: italic;">Basic Clock Module</span> peripheral has a few
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limitations.<br>
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        <br>
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      </li>
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      <li>&nbsp;<span style="font-weight: bold;">ASIC friendly</span>: the core contains up to all clock management
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options (clock muxes &amp; low-power modes, fine grained clock
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gating, ...) and is also ready for scan insertion. In this mode, the <span style="font-style: italic;">Basic Clock Module</span> offers all features listed in the official <a href="http://www.ti.com/litv/pdf/slau049f">documentation</a>.<br>
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      </li>
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    </ul>
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  </ul>
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</ul>
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<br>It is to be noted that this IP doesn't contain the instruction and
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data memory blocks internally (these are technology dependent hard
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macros which are connected to the IP during chip integration).
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However the core is fully configurable in regard to the supported RAM
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and/or ROM sizes.
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<br><br>In addition to the CPU core itself, several peripherals are
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also provided and can be easily connected to the core during
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integration.
85 
<br><br>
86 
 
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<a name="2. Design"></a>
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<h1>2. Design</h1>
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90 
<a name="2.1 Core"></a>
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<h2>2.1 Core</h2>
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93 
<a name="2.1.1 Design structure"></a>
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<h3>2.1.1 Design structure</h3>
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The following diagram shows the openMSP430 design structure:
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<br><br>
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<img src="http://opencores.org/usercontent,img,1354053264" alt="CPU Structure" title="CPU Structure" width="80%">
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<br>
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<ul>
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        <li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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        <li><b>Execution unit</b>:
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Containing the ALU and the register file, this module executes the
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current decoded instruction according to the execution state.</li>
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        <li><b>Serial Debug Interface</b>:
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Contains all the required logic for a Nexus class 3 debugging unit
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(without trace). Communication with the host is performed with a standard
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two-wire interface following either the UART 8N1 or I<sup>2</sup>C serial protocol.</li>
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   <li><b>Memory backbone</b>: This block
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performs a simple arbitration between the frontend and execution-unit
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for program, data and peripheral memory access.</li>
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   <li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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   <li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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   <li><b>Watchdog</b>:
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Although it is a peripheral, the watchdog is directly included in
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the core because of its tight links with the NMI interrupts and PUC
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reset generation.</li>
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   <li><b>16x16 Multiplier</b>: The hardware
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multiplier peripheral is transparently supported by the GCC compiler
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and is therefore located in the core. It can be included or excluded at will
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through a Verilog define.</li>
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</ul>
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124 
<a name="2.1.2 Limitations"></a>
125 
<h3>2.1.2 Limitations</h3>
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The known core limitations are the following:
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<br>
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<ul>
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        <li>Instructions can't be executed from the data memory.</li>
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        </ul>
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133 
<a name="2.1.3 Configuration"></a>
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<h3>2.1.3 Configuration</h3>
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It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br>In
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this section, three sets of adjustabe user parameters are discussed in
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order to customize the core. A fourth set is available for ASIC
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specific options and will be discussed in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
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section. <a name="2.1.3.1 Basic System Configuration"></a>
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<h4>2.1.3.1 Basic System Configuration</h4>
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The basic system can be adjusted with the following set of defines in order to match the target system requirements.
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<br><br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br>
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</td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td>
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        <code>
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             //============================================================================<br>
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//============================================================================<br>
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// BASIC SYSTEM CONFIGURATION<br>
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//============================================================================<br>
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//============================================================================<br>
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//<br>
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// Note: the sum of program, data and peripheral memory spaces must not<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; exceed 64 kB<br>
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//<br>
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      <br>
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// Program Memory Size:<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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Uncomment the required memory size<br>
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//-------------------------------------------------------<br>
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//`define PMEM_SIZE_CUSTOM<br>
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//`define PMEM_SIZE_59_KB<br>
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//`define PMEM_SIZE_55_KB<br>
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//`define PMEM_SIZE_54_KB<br>
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//`define PMEM_SIZE_51_KB<br>
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//`define PMEM_SIZE_48_KB<br>
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//`define PMEM_SIZE_41_KB<br>
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//`define PMEM_SIZE_32_KB<br>
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//`define PMEM_SIZE_24_KB<br>
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//`define PMEM_SIZE_16_KB<br>
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//`define PMEM_SIZE_12_KB<br>
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//`define PMEM_SIZE_8_KB<br>
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//`define PMEM_SIZE_4_KB<br>
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`define PMEM_SIZE_2_KB<br>
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//`define PMEM_SIZE_1_KB<br>
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      <br>
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      <br>
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// Data Memory Size:<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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Uncomment the required memory size<br>
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//-------------------------------------------------------<br>
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//`define DMEM_SIZE_CUSTOM<br>
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//`define DMEM_SIZE_32_KB<br>
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//`define DMEM_SIZE_24_KB<br>
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//`define DMEM_SIZE_16_KB<br>
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//`define DMEM_SIZE_10_KB<br>
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//`define DMEM_SIZE_8_KB<br>
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//`define DMEM_SIZE_5_KB<br>
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//`define DMEM_SIZE_4_KB<br>
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//`define DMEM_SIZE_2p5_KB<br>
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//`define DMEM_SIZE_2_KB<br>
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//`define DMEM_SIZE_1_KB<br>
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//`define DMEM_SIZE_512_B<br>
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//`define DMEM_SIZE_256_B<br>
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`define DMEM_SIZE_128_B<br>
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      <br>
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      <br>
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// Include/Exclude Hardware Multiplier<br>
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`define MULTIPLIER<br>
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      <br>
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      <br>
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// Include/Exclude Serial Debug interface<br>
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`define DBG_EN<br>
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      </code></td></tr></tbody></table><br><br>
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The only design considerations at this stage are:
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<ul>
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        <li>Make sure that the program and data memories have the correct size :-P</li>
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        <li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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<br>
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<b><u>Note:</u></b> when selected, custom memory sizes can be specified in the "Expert System Configuration" section.
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<br>
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<br>
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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In this section, some additional features are available in order to match the needs of more experienced users.
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<br><br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br>
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</td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td><code>//============================================================================<br>
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//============================================================================<br>
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// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)<br>
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//============================================================================<br>
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//============================================================================<br>
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      <br>
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//-------------------------------------------------------<br>
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// Custom user version number<br>
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//-------------------------------------------------------<br>
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// This 5 bit field can be freely used in order to allow<br>
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// custom identification of the system through the debug<br>
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// interface.<br>
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// (see CPU_ID.USER_VERSION field in the documentation)<br>
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//-------------------------------------------------------<br>
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`define USER_VERSION 5'b00000<br>
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      <br>
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      <br>
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//-------------------------------------------------------<br>
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// Include/Exclude Watchdog timer<br>
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//-------------------------------------------------------<br>
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// When excluded, the following functionality will be<br>
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// lost:<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - Watchog (both interval and watchdog modes)<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - NMI interrupt edge selection<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - Possibility to generate a software PUC reset<br>
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//-------------------------------------------------------<br>
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`define WATCHDOG<br>
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      <br>
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      <br>
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///-------------------------------------------------------<br>
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// Include/Exclude Non-Maskable-Interrupt support<br>
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//-------------------------------------------------------<br>
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`define NMI<br>
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      <br>
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      <br>
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//-------------------------------------------------------<br>
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// Input synchronizers<br>
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//-------------------------------------------------------<br>
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// In some cases, the asynchronous input ports might<br>
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// already be synchronized externally.<br>
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// If an extensive CDC design review showed that this<br>
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// is really the case,&nbsp; the individual synchronizers<br>
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// can be disabled with the following defines.<br>
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//<br>
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// Notes:<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - all three signals are all sampled in the MCLK domain<br>
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//<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - the dbg_en signal reset the debug interface<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; when 0. Therefore make sure it is glitch free.<br>
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//<br>
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//-------------------------------------------------------<br>
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`define SYNC_NMI<br>
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//`define SYNC_CPU_EN<br>
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//`define SYNC_DBG_EN<br>
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</code><code><br>
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      <br>
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</code><code>//-------------------------------------------------------<br>
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// Peripheral Memory Space:<br>
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//-------------------------------------------------------<br>
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// The original MSP430 architecture map the peripherals<br>
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// from 0x0000 to 0x01FF (i.e. 512B of the memory space).<br>
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// The following defines allow you to expand this space<br>
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
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// As a consequence, the data memory mapping will be<br>
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// shifted up and a custom linker script will therefore<br>
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// be required by the GCC compiler.<br>
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//-------------------------------------------------------<br>
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//`define PER_SIZE_CUSTOM<br>
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//`define PER_SIZE_32_KB<br>
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//`define PER_SIZE_16_KB<br>
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//`define PER_SIZE_8_KB<br>
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//`define PER_SIZE_4_KB<br>
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//`define PER_SIZE_2_KB<br>
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//`define PER_SIZE_1_KB<br>
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`define PER_SIZE_512_B<br>
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      <br>
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      <br></code><code>//-------------------------------------------------------<br>
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// Defines the debugger CPU_CTL.RST_BRK_EN reset value<br>
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// (CPU break on PUC reset)<br>
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//-------------------------------------------------------<br>
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// When defined, the CPU will automatically break after<br>
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// a PUC occurrence by default. This is typically useful<br>
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// when the program memory can only be initialized through<br>
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// the serial debug interface.<br>
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//-------------------------------------------------------<br>
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`define DBG_RST_BRK_EN</code><br>
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</td></tr></tbody></table><br><br>
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Design consideration at this stage are:
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<ul>
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        <li>Setting a peripheral memory space to something else than 512B
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will shift the data memory mapping up, which in turn will require the
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use of a custom linker script. If you don't know what a linker script
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is and if you don't want to know what it is, you should probably not
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modify this section.</li>
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        <li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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<br>
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<b><u>Note:</u></b> when selected, custom peripheral memory space can be specified in the "Expert System Configuration" section.
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<br>
335 
<br>
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<a name="2.1.3.3 Expert System Configuration"></a>
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<h4>2.1.3.3 Expert System Configuration</h4>
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In this section, you will find configuration options which are
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relevant for roughly 0.1% of the users (according to a highly
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reliable market analysis ;-) ).
341 
<br><br>
342 
<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br>
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</td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td>
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        <code> //============================================================================<br>
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//============================================================================<br>
353 
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )<br>
354 
//============================================================================<br>
355 
//============================================================================<br>
356 
//<br>
357 
// IMPORTANT NOTE:&nbsp; Please update following configuration options ONLY if<br>
358 
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
359 
you have a good reason to do so... and if you know what<br>
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//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; you are doing :-P<br>
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//<br>
362 
//============================================================================<br>
363 
      <br>
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//-------------------------------------------------------<br>
365 
// Select serial debug interface protocol<br>
366 
//-------------------------------------------------------<br>
367 
//&nbsp;&nbsp;&nbsp; DBG_UART -&gt; Enable UART (8N1) debug interface<br>
368 
//&nbsp;&nbsp;&nbsp; DBG_I2C&nbsp; -&gt; Enable I2C debug interface<br>
369 
//-------------------------------------------------------<br>
370 
`define DBG_UART<br>
371 
//`define DBG_I2C<br>
372 
      <br>
373 
      <br>
374 
//-------------------------------------------------------<br>
375 
// Enable the I2C broadcast address<br>
376 
//-------------------------------------------------------<br>
377 
// For multicore systems, a common I2C broadcast address<br>
378 
// can be given to all oMSP cores in order to<br>
379 
// synchronously RESET, START, STOP, or STEP all CPUs<br>
380 
// at once with a single I2C command.<br>
381 
// If you have a single openMSP430 in your system,<br>
382 
// this option can stay commented-out.<br>
383 
//-------------------------------------------------------<br>
384 
//`define DBG_I2C_BROADCAST<br>
385 
      <br>
386 
<br>
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//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
388 
// (each unit contains two hardware addresses available<br>
389 
// for breakpoints or watchpoints):<br>
390 
//&nbsp;&nbsp; - DBG_HWBRK_0 -&gt; Include hardware breakpoints unit 0<br>
391 
//&nbsp;&nbsp; - DBG_HWBRK_1 -&gt; Include hardware breakpoints unit 1<br>
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//&nbsp;&nbsp; - DBG_HWBRK_2 -&gt; Include hardware breakpoints unit 2<br>
393 
//&nbsp;&nbsp; - DBG_HWBRK_3 -&gt; Include hardware breakpoints unit 3<br>
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//-------------------------------------------------------<br>
395 
// Please keep in mind that hardware breakpoints only<br>
396 
// make sense whenever the program memory is not an SRAM<br>
397 
// (i.e. Flash/OTP/ROM/...) or when you are interested<br>
398 
// in data breakpoints.<br>
399 
//-------------------------------------------------------<br>
400 
//`define&nbsp; DBG_HWBRK_0<br>
401 
//`define&nbsp; DBG_HWBRK_1<br>
402 
//`define&nbsp; DBG_HWBRK_2<br>
403 
//`define&nbsp; DBG_HWBRK_3<br>
404 
      <br>
405 
      <br>
406 
//-------------------------------------------------------<br>
407 
// Enable/Disable the hardware breakpoint RANGE mode<br>
408 
//-------------------------------------------------------<br>
409 
// When enabled this feature allows the hardware breakpoint<br>
410 
// units to stop the cpu whenever an instruction or data<br>
411 
// access lays within an address range.<br>
412 
// Note that this feature is not supported by GDB.<br>
413 
//-------------------------------------------------------<br>
414 
//`define DBG_HWBRK_RANGE<br>
415 
      <br>
416 
      <br>
417 
//-------------------------------------------------------<br>
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// Custom Program/Data and Peripheral Memory Spaces<br>
419 
//-------------------------------------------------------<br>
420 
// The following values are valid only if the<br>
421 
// corresponding *_SIZE_CUSTOM defines are uncommented:<br>
422 
//<br>
423 
//  - *_SIZE   : size of the section in bytes.<br>
424 
//  - *_AWIDTH : address port width, this value must allow<br>
425 
//               to address all WORDS of the section<br>
426 
//               (i.e. the *_SIZE divided by 2)<br>
427 
//-------------------------------------------------------<br>
428 
<br>
429 
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)<br>
430 
`define PMEM_CUSTOM_AWIDTH      10<br>
431 
`define PMEM_CUSTOM_SIZE      2048<br>
432 
<br>
433 
// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)<br>
434 
`define DMEM_CUSTOM_AWIDTH       6<br>
435 
`define DMEM_CUSTOM_SIZE       128<br>
436 
<br>
437 
// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)<br>
438 
`define PER_CUSTOM_AWIDTH        8<br>
439 
`define PER_CUSTOM_SIZE        512<br>
440 
<br>
441 
<br>
442 
//-------------------------------------------------------<br>
443 135 olivier.gi 
// ASIC version<br>
444 
//-------------------------------------------------------<br>
445 
// When uncommented, this define will enable the<br>
446 
// ASIC system configuration section (see below) and<br>
447 
// will activate scan support for production test.<br>
448 
//<br>
449 
// WARNING: if you target an FPGA, leave this define<br>
450 
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; commented.<br>
451 
//-------------------------------------------------------<br>
452 
//`define ASIC<br></code></td></tr></tbody></table><br><br>
453 116 olivier.gi 
Design consideration at this stage are:
454 
<ul>
455 
        <li>This is the expert section... so you know what your are doing anyway right ;-)</li>
456 
</ul>
457 135 olivier.gi 
<br>
458 
All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
459 166 olivier.gi 
<br>
460 
<br>
461 
<a name="2.1.3.4 Parameters For Multi-Core Systems"></a>
462 
<h4>2.1.3.4 Parameters For Multi-Core Systems</h4>
463 
 
464 
In addition to the define file, two Verilog parameters are available to facilitate software development on multi-core systems.<br>
465 
For example, in a dual-core openMSP430 system, the cores can be instantiated as following:
466 
<br>
467 
<br>
468 
<table border="0" cellpadding="0" cellspacing="4">
469 
<tbody><tr>
470 
<td width="35"><br></td>
471 
<td bgcolor="#d0d0d0" width="3"><br></td>
472 
<td width="15"><br></td>
473 
<td>
474 
        <code>
475 
                          openMSP430 #(.INST_NR (<strong>0</strong>), .TOTAL_NR(<strong>1</strong>)) openMSP430_core_0 (
476 
                      <br>...
477 
                      <br>);
478 
                      <br>
479 
                      <br>openMSP430 #(.INST_NR (<strong>1</strong>), .TOTAL_NR(<strong>1</strong>)) openMSP430_core_1 (
480 
                      <br>...
481 
                      <br>);
482 
        </code>
483 
</td>
484 
</tr>
485 
</tbody>
486 
</table>
487 
<br>
488 
The values of these parameters are then directly accessible through the CPU_NR register of the SFR peripheral.<br>
489 
For example, if both cores share the same program memory, the software can take advantage of this information as following:
490 135 olivier.gi 
<br><br>
491 166 olivier.gi 
<table border="0" cellpadding="0" cellspacing="4">
492 
<tbody><tr>
493 
<td width="35"><br></td>
494 
<td bgcolor="#d0d0d0" width="3"><br></td>
495 
<td width="15"><br></td>
496 
<td>
497 
        <code>
498 
                           "...
499 
                      <br>int main(void) {
500 
                      <br>&nbsp;&nbsp;if (CPU_NR==<strong>0x0100</strong>) {
501 
                      <br>&nbsp;&nbsp;&nbsp;&nbsp;main_core_0();&nbsp;// Main routine call for core 0
502 
                      <br>&nbsp;&nbsp;}
503 
                      <br>&nbsp;&nbsp;if (CPU_NR==<strong>0x0101</strong>) {
504 
                      <br>&nbsp;&nbsp;&nbsp;&nbsp;main_core_1();&nbsp;// Main routine call for core 1
505 
                      <br>&nbsp;&nbsp;}
506 
                      <br>}
507 
                      <br>..."
508 
        </code>
509 
</td>
510 
</tr>
511 
</tbody>
512 
</table>
513 
<br><br>
514 50 olivier.gi 
 
515 116 olivier.gi 
<a name="2.1.4 Memory mapping"></a>
516 
<h3>2.1.4 Memory mapping</h3>
517 50 olivier.gi 
 
518 135 olivier.gi 
As discussed earlier, the openMSP430 memory mapping is fully configurable.<br>The
519 
basic system configuration section allows to adjust program and data
520 
memory sizes while keeping 100% compatibility with the pre-existing
521 
linker scripts provided by MSPGCC (or any other toolchain for that
522 
matter).<br>
523 
However, an increasing number of users saw the 512B space available for
524 
peripherals in the standard MSP430 architecture as a limitation.
525 
Therefore, the advanced system configuration section gives the
526 
possibility to up-scale the reserved peripheral address space anywhere
527 
between 512B and 32kB. As a consequence, the data memory space will be
528 
shifted up, which means that the linker script of your favorite
529 
toolchain will have to be modified accordingly.<br>
530 
The following schematic should hopefully illustrate this:<br>
531 
<br><br>
532 
<img src="usercontent,img,1306066277" alt="Memory mapping" title="Memory mapping" width="80%">
533 
<br>
534 116 olivier.gi 
 
535 135 olivier.gi 
<br><br>
536 116 olivier.gi 
<a name="2.1.5 Pinout"></a>
537 
<h3>2.1.5 Pinout</h3>
538 
 
539 50 olivier.gi 
The full pinout of the openMSP430 core is provided in the following table:
540 135 olivier.gi 
<br><br>
541 50 olivier.gi 
<table border="1">
542 135 olivier.gi 
        <tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b>    </td> <td style="vertical-align: top; text-align: center;"><span style="font-weight: bold;">Clock</span><br style="font-weight: bold;">
543 
      <span style="font-weight: bold;">Domain</span><br>
544 
      </td>
545 
<td align="center"><b>Description</b></td> </tr>
546 50 olivier.gi 
 
547 135 olivier.gi 
        <tr> <td colspan="5" align="center"> <b><i>Clocks &amp; Power-Managment</i></b>                         </td></tr>
548 50 olivier.gi 
        <tr>
549 116 olivier.gi 
             <td> cpu_en                                                           </td>
550 
             <td> Input                                                            </td>
551 
             <td> 1                                                                </td>
552 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
553 
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
554 
<td> Enable CPU code execution (asynchronous and non-glitchy).<br>
555 
 Set to 1 if unused.    </td>
556 116 olivier.gi 
        </tr>
557 
        <tr>
558 50 olivier.gi 
             <td> dco_clk                                                          </td>
559 
             <td> Input                                                            </td>
560 
             <td> 1                                                                </td>
561 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">-<br>
562 
      </td>
563 
<td> Fast oscillator (fast clock)                          </td>
564 50 olivier.gi 
        </tr>
565 
        <tr>
566 135 olivier.gi 
      <td style="vertical-align: top;"> lfxt_clk</td>
567 
      <td style="vertical-align: top;">Input<br>
568 
      </td>
569 
      <td style="vertical-align: top;">1<br>
570 
      </td>
571 
      <td style="vertical-align: top; text-align: center;">-<br>
572 
      </td>
573 
<td style="vertical-align: top;"> Low frequency oscillator (typ. 32kHz)<br>
574 
Set to 0 if unused.<br>
575 
      </td>
576 
    </tr>
577 
    <tr>
578 
      <td style="vertical-align: top;"> mclk</td>
579 
      <td style="vertical-align: top;">Output<br>
580 
      </td>
581 
      <td style="vertical-align: top;">1<br>
582 
      </td>
583 
      <td style="vertical-align: top; text-align: center;">-<br>
584 
      </td>
585 
<td style="vertical-align: top;"> Main system clock</td>
586 
    </tr>
587 
    <tr>
588 
      <td style="vertical-align: top;"> aclk_en</td>
589 
      <td style="vertical-align: top;">Output</td>
590 
      <td style="vertical-align: top;">1<br>
591 
      </td>
592 
      <td style="vertical-align: top; text-align: center;">mclk<br>
593 
      </td>
594 
<td style="vertical-align: top;">FPGA ONLY: ACLK enable</td>
595 
    </tr>
596 
    <tr>
597 
      <td style="vertical-align: top;">smclk_en</td>
598 
      <td style="vertical-align: top;">Output</td>
599 
      <td style="vertical-align: top;">1<br>
600 
      </td>
601 
      <td style="vertical-align: top; text-align: center;">mclk<br>
602 
      </td>
603 
<td style="vertical-align: top;">FPGA ONLY: SMCLK enable</td>
604 
    </tr>
605 
    <tr>
606 
      <td style="vertical-align: top;">dco_enable<br>
607 
      </td>
608 
      <td style="vertical-align: top;">Output<br>
609 
      </td>
610 
      <td style="vertical-align: top;">1<br>
611 
      </td>
612 
      <td style="vertical-align: top; text-align: center;">dco_clk<br>
613 
      </td>
614 
<td style="vertical-align: top;">ASIC ONLY: Fast oscillator enable<br>
615 
      </td>
616 
    </tr>
617 
    <tr>
618 
      <td style="vertical-align: top;">dco_wkup<br>
619 
      </td>
620 
      <td style="vertical-align: top;">Output<br>
621 
      </td>
622 
      <td style="vertical-align: top;">1<br>
623 
      </td>
624 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
625 
      </td>
626 
<td style="vertical-align: top;">ASIC ONLY: Fast oscillator wakeup (asynchronous)<br>
627 
      </td>
628 
    </tr>
629 
 
630 50 olivier.gi 
        <tr>
631 135 olivier.gi 
      <td style="vertical-align: top;">lfxt_enable<br>
632 
      </td>
633 
      <td style="vertical-align: top;">Output<br>
634 
      </td>
635 
      <td style="vertical-align: top;">1<br>
636 
      </td>
637 
      <td style="vertical-align: top; text-align: center;">lfxt_clk<br>
638 
      </td>
639 
<td style="vertical-align: top;">ASIC ONLY: Low frequency oscillator enable<br>
640 
      </td>
641 
    </tr>
642 
    <tr>
643 
      <td style="vertical-align: top;">lfxt_wkup<br>
644 
      </td>
645 
      <td style="vertical-align: top;">Output<br>
646 
      </td>
647 
      <td style="vertical-align: top;">1<br>
648 
      </td>
649 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
650 
      </td>
651 
<td style="vertical-align: top;">ASIC ONLY: Low frequency oscillator wakeup (asynchronous)<br>
652 
      </td>
653 
    </tr>
654 
 
655 50 olivier.gi 
        <tr>
656 135 olivier.gi 
      <td style="vertical-align: top;">aclk<br>
657 
      </td>
658 
      <td style="vertical-align: top;">Output<br>
659 
      </td>
660 
      <td style="vertical-align: top;">1<br>
661 
      </td>
662 
      <td style="vertical-align: top; text-align: center;">-<br>
663 
      </td>
664 
<td style="vertical-align: top;">ASIC ONLY: ACLK<br>
665 
      </td>
666 
    </tr>
667 
 
668 50 olivier.gi 
        <tr>
669 135 olivier.gi 
      <td style="vertical-align: top;">smclk<br>
670 
      </td>
671 
      <td style="vertical-align: top;">Output<br>
672 
      </td>
673 
      <td style="vertical-align: top;">1<br>
674 
      </td>
675 
      <td style="vertical-align: top; text-align: center;">-<br>
676 
      </td>
677 
<td style="vertical-align: top;">ASIC ONLY: SMCLK<br>
678 
      </td>
679 
    </tr>
680 50 olivier.gi 
 
681 135 olivier.gi 
 
682 50 olivier.gi 
        <tr>
683 135 olivier.gi 
      <td style="vertical-align: top;">wkup<br>
684 
      </td>
685 
      <td style="vertical-align: top;">Input<br>
686 
      </td>
687 
      <td style="vertical-align: top;">1<br>
688 
      </td>
689 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
690 
      </td>
691 
<td style="vertical-align: top;">ASIC ONLY: System Wake-up (asynchronous and non-glitchy)<br>
692 
Set to 0 if unused.<br>
693 
      </td>
694 
    </tr>
695 
<tr> <td colspan="5" align="center"> <b><i>Resets</i></b>                         </td></tr>
696 
        <tr>
697 116 olivier.gi 
             <td> puc_rst                                                          </td>
698 50 olivier.gi 
             <td> Output                                                           </td>
699 
             <td> 1                                                                </td>
700 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
701 
      </td>
702 
<td> Main system reset                                                </td>
703 50 olivier.gi 
   </tr>
704 
        <tr>
705 
             <td> reset_n                                                          </td>
706 
             <td> Input                                                            </td>
707 
             <td> 1                                                                </td>
708 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
709 
      </td>
710 
<td> Reset Pin (active low, asynchronous and non-glitchy)                             </td>
711 50 olivier.gi 
        </tr>
712 
 
713 
 
714 135 olivier.gi 
        <tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b>       </td></tr>
715 50 olivier.gi 
        <tr>
716 
             <td> pmem_addr                                                        </td>
717 
             <td> Output                                                           </td>
718 135 olivier.gi 
             <td><small> `PMEM_AWIDTH</small> <b><sup><font color="#ff0000">1</font></sup></b> </td>
719 
             <td style="vertical-align: top; text-align: center;">mclk<br>
720 
      </td>
721 
<td> Program Memory address                                           </td>
722 50 olivier.gi 
        </tr>
723 
        <tr>
724 
             <td> pmem_cen                                                         </td>
725 
             <td> Output                                                           </td>
726 
             <td> 1                                                                </td>
727 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
728 
      </td>
729 
<td> Program Memory chip enable (low active)                          </td>
730 50 olivier.gi 
        </tr>
731 
        <tr>
732 
             <td> pmem_din                                                         </td>
733 
             <td> Output                                                           </td>
734 
             <td> 16                                                               </td>
735 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
736 
      </td>
737 
<td> Program Memory data input (optional <b><sup><font color="#ff0000">2</font></sup></b>)</td>
738 50 olivier.gi 
        </tr>
739 
        <tr>
740 
             <td> pmem_dout                                                        </td>
741 
             <td> Input                                                            </td>
742 
             <td> 16                                                               </td>
743 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
744 
      </td>
745 
<td> Program Memory data output                                       </td>
746 50 olivier.gi 
        </tr>
747 
        <tr>
748 
             <td> pmem_wen                                                         </td>
749 
             <td> Output                                                           </td>
750 
             <td> 2                                                                </td>
751 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
752 
      </td>
753 
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#ff0000">2</font></sup></b>) </td>
754 50 olivier.gi 
        </tr>
755 
 
756 135 olivier.gi 
        <tr> <td colspan="5" align="center"> <b><i>Data Memory interface</i></b>          </td></tr>
757 50 olivier.gi 
        <tr>
758 
             <td> dmem_addr                                                        </td>
759 
             <td> Output                                                           </td>
760 135 olivier.gi 
             <td><small> `DMEM_AWIDTH</small> <b><sup><font color="#ff0000">1</font></sup></b></td>
761 
             <td style="vertical-align: top; text-align: center;">mclk<br>
762 
      </td>
763 
<td> Data Memory address                                              </td>
764 50 olivier.gi 
        </tr>
765 
        <tr>
766 
             <td> dmem_cen                                                         </td>
767 
             <td> Output                                                           </td>
768 
             <td> 1                                                                </td>
769 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
770 
      </td>
771 
<td> Data Memory chip enable (low active)                             </td>
772 50 olivier.gi 
        </tr>
773 
        <tr>
774 
             <td> dmem_din                                                         </td>
775 
             <td> Output                                                           </td>
776 
             <td> 16                                                               </td>
777 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
778 
      </td>
779 
<td> Data Memory data input                                           </td>
780 50 olivier.gi 
        </tr>
781 
        <tr>
782 
             <td> dmem_dout                                                        </td>
783 
             <td> Input                                                            </td>
784 
             <td> 16                                                               </td>
785 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
786 
      </td>
787 
<td> Data Memory data output                                          </td>
788 50 olivier.gi 
        </tr>
789 
        <tr>
790 
             <td> dmem_wen                                                         </td>
791 
             <td> Output                                                           </td>
792 
             <td> 2                                                                </td>
793 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
794 
      </td>
795 
<td> Data Memory write byte enable (low active)                       </td>
796 50 olivier.gi 
        </tr>
797 
 
798 135 olivier.gi 
        <tr> <td colspan="5" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
799 50 olivier.gi 
        <tr>
800 
             <td> per_addr                                                         </td>
801 
             <td> Output                                                           </td>
802 116 olivier.gi 
             <td> 14                                                                </td>
803 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
804 
      </td>
805 
<td> Peripheral address                                               </td>
806 50 olivier.gi 
        </tr>
807 
        <tr>
808 
             <td> per_din                                                          </td>
809 
             <td> Output                                                           </td>
810 
             <td> 16                                                               </td>
811 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
812 
      </td>
813 
<td> Peripheral data input                                            </td>
814 50 olivier.gi 
   </tr>
815 
        <tr>
816 
             <td> per_dout                                                         </td>
817 
             <td> Input                                                            </td>
818 
             <td> 16                                                               </td>
819 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
820 
      </td>
821 
<td> Peripheral data output                                           </td>
822 50 olivier.gi 
        </tr>
823 
        <tr>
824 
             <td> per_en                                                           </td>
825 
             <td> Output                                                           </td>
826 
             <td> 1                                                                </td>
827 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
828 
      </td>
829 
<td> Peripheral enable (high active)                                  </td>
830 50 olivier.gi 
        </tr>
831 
        <tr>
832 116 olivier.gi 
             <td> per_we                                                           </td>
833 50 olivier.gi 
             <td> Output                                                           </td>
834 
             <td> 2                                                                </td>
835 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
836 
      </td>
837 
<td> Peripheral write enable (high active)                            </td>
838 50 olivier.gi 
        </tr>
839 
 
840 135 olivier.gi 
        <tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b>                     </td></tr>
841 50 olivier.gi 
        <tr>
842 
                  <td> irq                                                              </td>
843 
                  <td> Input                                                            </td>
844 
                  <td> 14                                                               </td>
845 135 olivier.gi 
                  <td style="vertical-align: top; text-align: center;">mclk<br>
846 
      </td>
847 
<td> Maskable interrupts (one-hot signal)                             </td>
848 50 olivier.gi 
   </tr>
849 
        <tr>
850 
             <td> nmi                                                              </td>
851 
             <td> Input                                                            </td>
852 
             <td> 1                                                                </td>
853 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
854 
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
855 
<td> Non-maskable interrupt (asynchronous and non-glitchy)<br>
856 
Set to 0 if unused.<br>
857 
                            </td>
858 50 olivier.gi 
        </tr>
859 
        <tr>
860 
             <td> irq_acc                                                          </td>
861 
             <td> Output                                                           </td>
862 
             <td> 14                                                               </td>
863 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
864 
      </td>
865 
<td> Interrupt request accepted (one-hot signal)                      </td>
866 50 olivier.gi 
        </tr>
867 
 
868 135 olivier.gi 
        <tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b>         </td></tr>
869 50 olivier.gi 
        <tr>
870 116 olivier.gi 
             <td> dbg_en                                                           </td>
871 
             <td> Input                                                            </td>
872 
             <td> 1                                                                </td>
873 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
874 
 
875 
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
876 
<td> Debug interface enable (asynchronous) <b><sup><font color="#ff0000">3</font></sup></b> </td>
877 116 olivier.gi 
        </tr>
878 
        <tr>
879 50 olivier.gi 
             <td> dbg_freeze                                                       </td>
880 
             <td> Output                                                           </td>
881 
             <td> 1                                                                </td>
882 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
883 
      </td>
884 
<td> Freeze peripherals                                               </td>
885 50 olivier.gi 
        </tr>
886 
        <tr>
887 
             <td> dbg_uart_txd                                                     </td>
888 
             <td> Output                                                           </td>
889 
             <td> 1                                                                </td>
890 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">mclk<br>
891 
      </td>
892 
<td> Debug interface: UART TXD                                        </td>
893 50 olivier.gi 
        </tr>
894 
        <tr>
895 
             <td> dbg_uart_rxd                                                     </td>
896 
             <td> Input                                                            </td>
897 
             <td> 1                                                                </td>
898 135 olivier.gi 
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
899 
      </td>
900 
<td> Debug interface: UART RXD (asynchronous)                         </td>
901 166 olivier.gi 
        </tr><tr>
902 
      <td style="vertical-align: top;">dbg_i2c_addr<br>
903 
      </td>
904 
      <td style="vertical-align: top;"> Input</td>
905 
      <td style="vertical-align: top;"> 7</td>
906 
      <td style="vertical-align: top; text-align: center;">mclk</td>
907 
      <td style="vertical-align: top;">Debug interface: I2C Address<br>
908 
      </td>
909 
    </tr>
910 
    <tr>
911 
      <td style="vertical-align: top;">dbg_i2c_broadcast<br>
912 
      </td>
913 
      <td style="vertical-align: top;"> Input</td>
914 
      <td style="vertical-align: top;"> 7</td>
915 
      <td style="vertical-align: top; text-align: center;">mclk</td>
916 
      <td style="vertical-align: top;">Debug interface: I2C Broadcast Address (for multicore systems)<br>
917 
      </td>
918 
    </tr>
919 
    <tr>
920 
      <td style="vertical-align: top;">dbg_i2c_scl<br>
921 
      </td>
922 
      <td style="vertical-align: top;"> Input</td>
923 
      <td style="vertical-align: top;"> 1</td>
924 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;</td>
925 
      <td style="vertical-align: top;">Debug interface: I2C SCL (asynchronous)</td>
926 
    </tr>
927 
    <tr>
928 
      <td style="vertical-align: top;">dbg_i2c_sda_in<br>
929 
      </td>
930 
      <td style="vertical-align: top;"> Input</td>
931 
      <td style="vertical-align: top;"> 1</td>
932 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;</td>
933 
      <td style="vertical-align: top;">Debug interface: I2C SDA IN (asynchronous)</td>
934 
    </tr>
935 
    <tr>
936 
      <td style="vertical-align: top;">dbg_i2c_sda_out<br>
937 
      </td>
938 
      <td style="vertical-align: top;"> Output</td>
939 
      <td style="vertical-align: top;"> 1</td>
940 
      <td style="vertical-align: top; text-align: center;">mclk</td>
941 
      <td style="vertical-align: top;">Debug interface: I2C SDA OUT<br>
942 
      </td>
943 
    </tr>
944 
<tr align="center">
945 135 olivier.gi 
      <td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
946 
    </tr>
947 
    <tr>
948 
      <td style="vertical-align: top;">scan_enable<br>
949 
      </td>
950 
      <td style="vertical-align: top;">Input<br>
951 
      </td>
952 
      <td style="vertical-align: top;">1<br>
953 
      </td>
954 
      <td style="vertical-align: top; text-align: center;">dco_clk<br>
955 
      </td>
956 
<td style="vertical-align: top;">ASIC ONLY: Scan enable (active during scan shifting)<br>
957 
      </td>
958 
    </tr>
959 
    <tr>
960 
      <td style="vertical-align: top;">scan_mode<br>
961 
      </td>
962 
      <td style="vertical-align: top;">Input<br>
963 
      </td>
964 
      <td style="vertical-align: top;">1<br>
965 
      </td>
966 
      <td style="vertical-align: top; text-align: center;">&lt;stable&gt;<br>
967 
      </td>
968 
<td style="vertical-align: top;">ASIC ONLY: Scan mode<br>
969 
      </td>
970 
    </tr>
971 50 olivier.gi 
 
972 135 olivier.gi 
</tbody></table>
973 
<br>
974 
<b><sup><font color="#ff0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br>
975 
<b><sup><font color="#ff0000">2</font></sup></b>: These two optional
976 
ports can be connected whenever the program memory is a RAM. This will
977 
allow the user to load a program through the serial debug interface and
978 
to use software breakpoints.<br>
979 
<b><sup><font color="#ff0000">3</font></sup></b>: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br>
980 
<b><sup><font color="#ff0000">4</font></sup></b>: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).<br>
981 
<br>
982 
<span style="text-decoration: underline; font-weight: bold;">Note:</span> in the FPGA configuration, the <span style="font-style: italic;">ASIC ONLY</span> signals must be left unconnected (for the outputs) and tied low (for the inputs).<br>
983 
 
984 116 olivier.gi 
<a name="2.1.6 Instruction Cycles and Lengths"></a>
985 
<h3>2.1.6 Instruction Cycles and Lengths</h3>
986 50 olivier.gi 
 
987 135 olivier.gi 
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br><br>
988 
The number of CPU clock cycles required for an instruction depends on
989 
the instruction format and the addressing modes used, not the
990 
instruction itself.<br>
991 116 olivier.gi 
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
992 50 olivier.gi 
Differences with the original MSP430 are highlighted in green (the original value being red).
993 
<ul>
994 
        <li><b>Interrupt and Reset Cycles</b></li>
995 
</ul>
996 
<table border="1">
997 135 olivier.gi 
        <tbody><tr> <td align="center"><b>Action</b>  </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
998 50 olivier.gi 
        <tr> <td> Return from interrupt (RETI) </td> <td align="center">       5            </td> <td align="center">           1                </td> </tr>
999 
        <tr> <td> Interrupt accepted           </td> <td align="center">       6            </td> <td align="center">           -                </td> </tr>
1000 
        <tr> <td> WDT reset                    </td> <td align="center">       4            </td> <td align="center">           -                </td> </tr>
1001 
        <tr> <td> Reset (!RST/NMI)             </td> <td align="center">       4            </td> <td align="center">           -                </td> </tr>
1002 135 olivier.gi 
</tbody></table>
1003 50 olivier.gi 
 
1004 
<ul>
1005 
        <li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
1006 
</ul>
1007 
<table border="1">
1008 135 olivier.gi 
        <tbody><tr> <td rowspan="2" align="center"><b>Addressing Mode</b>  </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
1009 50 olivier.gi 
        <tr>                                                              <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
1010 
 
1011 
        <tr> <td align="center"> Rn    </td> <td align="center"> 1   </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
1012 
        <tr> <td align="center"> @Rn   </td> <td align="center"> 3   </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
1013 
        <tr> <td align="center"> @Rn+  </td> <td align="center"> 3   </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
1014 
        <tr> <td align="center"> #N    </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1015 
        <tr> <td align="center"> X(Rn) </td> <td align="center"> 4   </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1016 
        <tr> <td align="center"> EDE   </td> <td align="center"> 4   </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1017 135 olivier.gi 
        <tr> <td align="center"> &amp;EDE  </td> <td align="center"> 4   </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1018 
</tbody></table>
1019 50 olivier.gi 
 
1020 
<ul>
1021 
        <li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
1022 
</ul>
1023 
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
1024 
 
1025 
<ul>
1026 
        <li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
1027 
</ul>
1028 
<table border="1">
1029 135 olivier.gi 
        <tbody><tr> <td colspan="2" align="center"><b>Addressing Mode</b>  </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
1030 50 olivier.gi 
        <tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
1031 
 
1032 
        <tr> <td rowspan="5" align="center"> Rn    </td> <td align="center"> Rm    </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
1033 
        <tr>                                             <td align="center"> PC    </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
1034 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
1035 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
1036 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
1037 50 olivier.gi 
        <tr> <td rowspan="5" align="center"> @Rn   </td> <td align="center"> Rm    </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
1038 
        <tr>                                             <td align="center"> PC    </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
1039 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1040 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1041 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1042 50 olivier.gi 
        <tr> <td rowspan="5" align="center"> @Rn+  </td> <td align="center"> Rm    </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
1043 
        <tr>                                             <td align="center"> PC    </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
1044 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1045 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1046 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
1047 50 olivier.gi 
        <tr> <td rowspan="5" align="center"> #N    </td> <td align="center"> Rm    </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
1048 
        <tr>                                             <td align="center"> PC    </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
1049 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
1050 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
1051 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
1052 50 olivier.gi 
        <tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm    </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
1053 
        <tr>                                             <td align="center"> PC    </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
1054 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1055 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1056 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1057 50 olivier.gi 
        <tr> <td rowspan="5" align="center"> EDE   </td> <td align="center"> Rm    </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
1058 
        <tr>                                             <td align="center"> PC    </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
1059 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1060 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1061 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1062 
        <tr> <td rowspan="5" align="center"> &amp;EDE  </td> <td align="center"> Rm    </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
1063 50 olivier.gi 
        <tr>                                             <td align="center"> PC    </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
1064 
        <tr>                                             <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1065 
        <tr>                                             <td align="center"> EDE   </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1066 135 olivier.gi 
        <tr>                                             <td align="center"> &amp;EDE  </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
1067 
</tbody></table>
1068 50 olivier.gi 
 
1069 116 olivier.gi 
<a name="2.1.7 Serial Debug Interface"></a>
1070 
<h3>2.1.7 Serial Debug Interface</h3>
1071 50 olivier.gi 
 
1072 135 olivier.gi 
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
1073 
<br>
1074 166 olivier.gi 
 
1075 
<a name="2.1.8 Benchmark results"></a>
1076 
<h3>2.1.8 Benchmark results</h3>
1077 
 
1078 
<a name="2.1.8.1 Dhrystone"></a>
1079 
<h4>2.1.8.1 Dhrystone (DMIPS/MHz)</h4>
1080 
Dhrystone is known for being susceptible to compiler optimizations (among other issues).<br>However,
1081 
as it is still quite a popular metric, some results are provided here
1082 
(ranging from 0.30 to 0.45 DMIPS/MHz depending on the compiler version
1083 
and options).<br>
1084 
Note that the used C-code is available in the repository <a href="http://opencores.org/websvn,listing?repname=openmsp430&amp;path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fdhrystone_v2.1%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_dhrystone_v2.1_">here</a> and <a href="http://opencores.org/websvn,listing?repname=openmsp430&amp;path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fdhrystone_4mcu%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_dhrystone_4mcu_">here</a>.<br>
1085 
<br>
1086 
 
1087 
<table style="text-align: left; width: 40%;" border="1" cellpadding="2" cellspacing="2">
1088 
  <tbody>
1089 
    <tr>
1090 
      <td style="text-align: center;" colspan="1" rowspan="2"><span style="font-weight: bold;">Dhrystone flavor</span></td>
1091 
      <td style="font-weight: bold; text-align: right;">Compiler options</td>
1092 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-Os</td>
1093 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O2</td>
1094 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O3</td>
1095 
    </tr>
1096 
    <tr align="left">
1097 
      <td style="font-weight: bold;">Compiler version
1098 
      </td>
1099 
    </tr>
1100 
    <tr>
1101 
      <td style="text-align: center;" colspan="1" rowspan="2">Dhrystone v2.1<br>
1102 
                     (<a href="http://ftp.unicamp.br/pub/unix-c/benchmark/system/">common version</a>)</td>
1103 
      <td style="text-align: left;">mspgcc v4.4.5</td>
1104 
      <td style="text-align: center;">0.30</td>
1105 
      <td style="text-align: center;">0.32</td>
1106 
      <td style="text-align: center;">0.33</td>
1107 
    </tr>
1108 
    <tr>
1109 
      <td style="text-align: left;">mspgcc v4.6.3</td>
1110 
      <td style="text-align: center;">0.37</td>
1111 
      <td style="text-align: center;">0.39</td>
1112 
      <td style="text-align: center;">0.40</td>
1113 
    </tr>
1114 
    <tr>
1115 
      <td style="text-align: center;" colspan="1" rowspan="2">Dhrystone v2.1<br>
1116 
                     (<a href="http://www.ecrostech.com/Other/Resources/Dhrystone.htm">MCU adapted</a>)</td>
1117 
      <td style="text-align: left;">mspgcc v4.4.5</td>
1118 
      <td style="text-align: center;">0.30</td>
1119 
      <td style="text-align: center;">0.30</td>
1120 
      <td style="text-align: center;">0.31</td>
1121 
    </tr>
1122 
    <tr>
1123 
      <td style="text-align: left;">mspgcc v4.6.3</td>
1124 
      <td style="text-align: center;">0.37</td>
1125 
      <td style="text-align: center;">0.44</td>
1126 
      <td style="text-align: center;">0.45</td>
1127 
    </tr>
1128 
  </tbody>
1129 
</table>
1130 
 
1131 
<a name="2.1.8.2 CoreMark"></a>
1132 
<h4>2.1.8.2 CoreMark (CoreMark/MHz)</h4>
1133 
CoreMark tries to address most of Dhrystone's pitfall by preventing the
1134 
compiler to optimize some code away and using "real-life" algorithm.<br>
1135 
Note that the used C-code is available in the repository <a href="http://opencores.org/websvn,listing?repname=openmsp430&amp;path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fcoremark_v1.0%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_coremark_v1.0_">here</a>.<br>
1136 
<br>
1137 
 
1138 
<table style="text-align: left; width: 40%;" border="1" cellpadding="2" cellspacing="2">
1139 
  <tbody>
1140 
    <tr>
1141 
      <td style="text-align: center;" colspan="1" rowspan="2"><br>
1142 
</td>
1143 
      <td style="font-weight: bold; text-align: right;">Compiler options</td>
1144 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-Os</td>
1145 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O2</td>
1146 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O3</td>
1147 
    </tr>
1148 
    <tr align="left">
1149 
      <td style="font-weight: bold;">Compiler version</td>
1150 
    </tr>
1151 
    <tr>
1152 
      <td style="text-align: center;" colspan="1" rowspan="2">CoreMark v1.0<br>
1153 
                     (<a href="http://www.coremark.org/">official version</a>)</td>
1154 
      <td style="text-align: left;">mspgcc v4.4.5</td>
1155 
      <td style="text-align: center;">0.78</td>
1156 
      <td style="text-align: center;">0.85</td>
1157 
      <td style="text-align: center;">0.83</td>
1158 
    </tr>
1159 
    <tr>
1160 
      <td style="text-align: left;">mspgcc v4.6.3</td>
1161 
      <td style="text-align: center;">0.74</td>
1162 
      <td style="text-align: center;">0.91</td>
1163 
      <td style="text-align: center;">0.87</td>
1164 
    </tr>
1165 
  </tbody>
1166 
</table>
1167 
<br>
1168 
 
1169 135 olivier.gi 
<a name="2.2_System_Peripherals"></a>
1170 
<h2>2.2 System Peripherals</h2>
1171 
In addition to the CPU core itself, several peripherals are also
1172 
provided and can be easily connected to the core during integration.
1173 
The followings are directly integrated within the core because of their
1174 
tight links with the CPU.<br>
1175 
It is to be noted that <span style="font-weight: bold;">ALL</span> system peripherals support both ASIC and FPGA versions.<br>
1176 50 olivier.gi 
<a name="2.2.1 Basic Clock Module"></a>
1177 135 olivier.gi 
<h3>2.2.1 Basic Clock Module: FPGA<br>
1178 
</h3>In order to make an FPGA
1179 
implementation as simple as possible (ideally, a non-professional designer should be
1180 
able to do it), clock gates are not used in this design configuration and neither are
1181 
clock muxes.
1182 
<br>
1183 50 olivier.gi 
With these constrains, the Basic Clock Module is implemented as following:
1184 135 olivier.gi 
<br><br>
1185 
<img src="usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="80%">
1186 
<br>
1187 
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the
1188 
CPU state machines in an IDLE state while MCLK will still be running.
1189 
<br><br>
1190 50 olivier.gi 
 
1191 
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
1192 135 olivier.gi 
<br><br>
1193 
<img src="usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example">
1194 
<br><br>For example, the following Verilog code would implement a counter clocked with SMCLK:
1195 
<br>
1196 
<table border="0" cellpadding="0" cellspacing="4">
1197 
<tbody><tr>
1198 
<td width="35"><br>
1199 
</td>
1200 
<td bgcolor="#d0d0d0" width="3"><br>
1201 
</td>
1202 
<td width="15"><br>
1203 
</td>
1204 50 olivier.gi 
<td>
1205 
        <code>
1206 
                      reg  [7:0] test_cnt;
1207 135 olivier.gi 
                <br>
1208 
                <br>always @ (posedge mclk or posedge puc_rst)
1209 
                <br>  if (puc_rst)       test_cnt &lt;=  8'h00;
1210 
                <br>  else if (smclk_en) test_cnt &lt;=  test_cnt + 8'h01;
1211 50 olivier.gi 
        </code>
1212 
</td>
1213 
</tr>
1214 135 olivier.gi 
</tbody></table>
1215 
<br><br>
1216 50 olivier.gi 
<b>Register Description</b>
1217 
<ul>
1218 
        <li>DCOCTL: Not implemented</li>
1219 
        <li>BCSCTL1:
1220 
        <ul>
1221 
      <li>BCSCTL1[7:6]: Unused</li>
1222 
      <li>BCSCTL1[5:4]: DIVAx</li>
1223 
      <li>BCSCTL1[4:0]: Unused</li>
1224 
        </ul>
1225 
        </li>
1226 
        <li>BCSCTL2:
1227 
        <ul>
1228 
      <li>BCSCTL2[7:4]: Unused</li>
1229 
      <li>BCSCTL2[3]&nbsp;&nbsp;&nbsp;: SELS</li>
1230 
      <li>BCSCTL2[2:1]: DIVSx</li>
1231 
      <li>BCSCTL2[0]&nbsp;&nbsp;&nbsp;: Unused</li>
1232 135 olivier.gi 
        </ul></li>
1233 
</ul><a name="2.2.2_Basic_Clock_Module_ASIC"></a>
1234 
<h3>2.2.2 Basic Clock Module: ASIC<br>
1235 
</h3>
1236 
When targeting an ASIC, up to all clock management
1237 
options available in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 4) can be included:<br><br>
1238 50 olivier.gi 
 
1239 135 olivier.gi 
<img src="usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="80%"><br>
1240 
Additional info can be found in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
1241 
section.<br>
1242 
<br>
1243 
<a name="2.2.3_SFR"></a>
1244 
<h3>2.2.3 SFR</h3>Following the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a>, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:<br>
1245 
<br>
1246 
<table border="1">
1247 
 
1248 
 
1249 
<tbody><tr align="center">
1250 
<td rowspan="2"><b><small>Register Name</small></b></td>
1251 
<td rowspan="2"><b><small>Address</small></b></td>
1252 
      <td colspan="8" rowspan="1" style="vertical-align: top;"><small style="font-weight: bold;">Bit Fields</small><br>
1253 
      </td>
1254 
 
1255 
</tr>
1256 
<tr align="center">
1257 
 
1258 
 
1259 
 
1260 
 
1261 
 
1262 
 
1263 
      <td style="vertical-align: top;"><small>7<br>
1264 
      </small></td>
1265 
      <td style="vertical-align: top;"><small>6<br>
1266 
      </small></td>
1267 
      <td style="vertical-align: top;"><small>5<br>
1268 
      </small></td>
1269 
      <td style="vertical-align: top;"><small>4<br>
1270 
      </small></td>
1271 
      <td style="vertical-align: top;"><small>3<br>
1272 
      </small></td>
1273 
      <td style="vertical-align: top;"><small>2<br>
1274 
      </small></td>
1275 
      <td style="vertical-align: top;"><small>1<br>
1276 
      </small></td>
1277 
      <td style="vertical-align: top;"><small>0<br>
1278 
      </small></td>
1279 
 
1280 
 
1281 
</tr>
1282 
<tr align="center">
1283 
<td>IE1<br>
1284 
</td>
1285 
<td><small>0x0000</small></td>
1286 
 
1287 
 
1288 
 
1289 
      <td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><small>&nbsp;Reserved <br>
1290 
      </small></td>
1291 
 
1292 
 
1293 
      <td style="vertical-align: top;">NMIIE <b><sup><font color="#ff0000">1</font></sup></b></td>
1294 
      <td colspan="3" rowspan="1" style="vertical-align: top;"><small>&nbsp; Reserved&nbsp;</small>
1295 
      </td>
1296 
 
1297 
 
1298 
      <td style="vertical-align: top;">WDTIE <b><sup><font color="#ff0000">2</font></sup></b></td>
1299 
 
1300 
</tr>
1301 
<tr align="center">
1302 
<td>IFG1<br>
1303 
</td>
1304 
<td><small>0x0002</small></td>
1305 
 
1306 
      <td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small><br>
1307 
 
1308 
      </td>
1309 
 
1310 
 
1311 
      <td style="vertical-align: top;">NMIIFG <b><sup><font color="#ff0000">1</font></sup></b></td>
1312 
      <td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small></td>
1313 
 
1314 
 
1315 
      <td style="vertical-align: top;">WDTIFG <b><sup><font color="#ff0000">2</font></sup></b></td>
1316 
 
1317 
 
1318 
</tr>
1319 
</tbody>
1320 
</table>
1321 
<br>
1322 
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
1323 
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
1324 
<br>
1325 166 olivier.gi 
In addition, three 16-bit read-only registers have been added in order
1326 135 olivier.gi 
to let the software know with which version of the openMSP430 it is
1327 
running:<br>
1328 
<br>
1329 
<table border="1">
1330 
 
1331 
<tbody><tr align="center">
1332 
<td rowspan="2"><b><small>Register Name</small></b></td>
1333 
<td rowspan="2"><b><small>Address</small></b></td>
1334 
<td colspan="16"><b><small>Bit Field</small></b></td>
1335 
</tr>
1336 
<tr align="center">
1337 
<td><small>15</small></td><td><small>14</small></td>
1338 
<td><small>13</small></td><td><small>12</small></td>
1339 
<td><small>11</small></td><td><small>10</small></td>
1340 
<td><small> 9</small></td><td><small> 8</small></td>
1341 
<td><small> 7</small></td><td><small> 6</small></td>
1342 
<td><small> 5</small></td><td><small> 4</small></td>
1343 
<td><small> 3</small></td><td><small> 2</small></td>
1344 
<td><small> 1</small></td><td><small> 0</small></td>
1345 
</tr>
1346 
<tr align="center">
1347 
<td><small>CPU_ID_LO</small></td>
1348 
<td><small>0x0004</small></td>
1349 
<td colspan="7"><font size="-5">PER_SPACE</font></td>
1350 
<td colspan="5"><font size="-5">USER_VERSION</font></td>
1351 
<td colspan="1"><font size="-5">ASIC</font></td>
1352 
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
1353 
</tr>
1354 
<tr align="center">
1355 
<td><small>CPU_ID_HI</small></td>
1356 
<td><small>0x0006</small></td>
1357 
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
1358 
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
1359 
<td colspan="1"><font size="-5">MPY</font></td>
1360 166 olivier.gi 
</tr><tr>
1361 
      <td style="vertical-align: top; text-align: center;"><small>CPU_NR</small></td>
1362 
      <td style="vertical-align: top; text-align: center;"><small>0x0008</small></td>
1363 
      <td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_TOTAL_NR</font></td>
1364 
      <td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_INST_NR</font></td>
1365 
    </tr>
1366 
 
1367 135 olivier.gi 
</tbody>
1368 
</table>
1369 
<br>
1370 
<table border="0">
1371 
 
1372 
<tbody><tr>
1373 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_VERSION</b></li></td>
1374 
   <td>: Current CPU version<br>
1375 
</td>
1376 
</tr>
1377 
<tr>
1378 
   <td>&nbsp;</td><td valign="top"><li><b>ASIC</b></li></td>
1379 
   <td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
1380 
</tr>
1381 
<tr>
1382 
   <td>&nbsp;</td><td valign="top"><li><b>USER_VERSION</b></li></td>
1383 
   <td>: Reflects the value defined in the <b style="font-style: italic;">openMSP430_defines.v</b> file.</td>
1384 
</tr>
1385 
<tr>
1386 
   <td>&nbsp;</td><td valign="top"><li><b>PER_SPACE</b></li></td>
1387 
   <td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
1388 
</tr>
1389 
<tr>
1390 
   <td>&nbsp;</td><td valign="top"><li><b>MPY</b></li></td>
1391 
   <td>: This bit is set if the hardware multiplier is included in the current implementation</td>
1392 
</tr>
1393 
<tr>
1394 
   <td>&nbsp;</td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
1395 
   <td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
1396 
</tr>
1397 
<tr>
1398 
   <td>&nbsp;</td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
1399 
   <td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
1400 
</tr>
1401 166 olivier.gi 
<tr>
1402 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_INST_NR</b></li></td>
1403 
   <td>: Current oMSP instance number (for multicore systems)</td>
1404 
</tr>
1405 
<tr>
1406 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_TOTAL_NR</b></li></td>
1407 
   <td>: Total number of oMSP instances-1 (for multicore systems)</td>
1408 
</tr>
1409 135 olivier.gi 
</tbody>
1410 
</table>
1411 
<br>
1412 166 olivier.gi 
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span>, <span style="font-style: italic;">CPU_ID_HI</span> and <span style="font-style: italic;">CPU_NR</span> are identical to the Serial Debug Interface register counterparts.<br>
1413 50 olivier.gi 
<a name="2.2.2 Watchdog Timer"></a>
1414 135 olivier.gi 
<h3>2.2.4 Watchdog Timer</h3>
1415 50 olivier.gi 
 
1416 
 
1417 135 olivier.gi 
 
1418 
 
1419 
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.<br>
1420 
 
1421 
<br>
1422 
 
1423 
The following parameter in the <i>openMSP430_defines.v</i> file controls if the watchdog timer should be included or not:<br>
1424 
<br>
1425 
<table border="0" cellpadding="0" cellspacing="4">
1426 
 
1427 
<tbody><tr>
1428 
<td width="35"><br>
1429 
</td>
1430 
<td bgcolor="#d0d0d0" width="3"><br>
1431 
</td>
1432 
<td width="15"><br>
1433 
</td>
1434 
<td>
1435 
        <code>//-------------------------------------------------------<br>
1436 
// Include/Exclude Watchdog timer<br>
1437 
//-------------------------------------------------------<br>
1438 
// When excluded, the following functionality will be<br>
1439 
// lost:<br>
1440 
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - Watchog (both interval and watchdog modes)<br>
1441 
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - NMI interrupt edge selection<br>
1442 
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - Possibility to generate a software PUC reset<br>
1443 
//-------------------------------------------------------<br>
1444 
`define WATCHDOG</code></td></tr></tbody>
1445 
</table>
1446 
<br>
1447 
<a name="2.2.5 16x16 Hardware Multiplier"></a>
1448 
<h3>2.2.5 16x16 Hardware Multiplier</h3>
1449 
 
1450 
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
1451 
<br><br>
1452 
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not:<br><br>
1453 
<table border="0" cellpadding="0" cellspacing="4">
1454 
<tbody><tr>
1455 
<td width="35"><br>
1456 
</td>
1457 
<td bgcolor="#d0d0d0" width="3"><br>
1458 
</td>
1459 
<td width="15"><br>
1460 
</td>
1461 
<td>
1462 
        <code>
1463 
            // Include/Exclude Hardware Multiplier
1464 
                <br>`define MULTIPLIER
1465 
        </code>
1466 
</td>
1467 
</tr>
1468 
</tbody></table>
1469 
<a name="2.3_Peripherals"></a>
1470 
<h2>2.3 External Peripherals</h2>
1471 
The external peripherals labeld with the "FPGA ONLY" tag do not contain
1472 
any clock gate nor clock muxes and are clocked with MCLK only. This
1473 
mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.<br>
1474 
<br>
1475 50 olivier.gi 
<a name="2.2.3 Digital I/O"></a>
1476 135 olivier.gi 
<h3>2.3.1 Digital I/O (FPGA ONLY)<br>
1477 
</h3>
1478 50 olivier.gi 
 
1479 135 olivier.gi 
 
1480 69 olivier.gi 
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
1481 135 olivier.gi 
<br>
1482 
<br>
1483 
 
1484 50 olivier.gi 
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
1485 135 olivier.gi 
<br>
1486 
<br>
1487 
 
1488 
<table border="0" cellpadding="0" cellspacing="4">
1489 
 
1490 
<tbody><tr>
1491 
<td width="35"><br>
1492 
</td>
1493 
<td bgcolor="#d0d0d0" width="3"><br>
1494 
</td>
1495 
<td width="15"><br>
1496 
</td>
1497 50 olivier.gi 
<td>
1498 
        <code>
1499 
                      parameter           P1_EN = 1'b1;   // Enable Port 1
1500 135 olivier.gi 
                <br>parameter           P2_EN = 1'b1;   // Enable Port 2
1501 
                <br>parameter           P3_EN = 1'b0;   // Enable Port 3
1502 
                <br>parameter           P4_EN = 1'b0;   // Enable Port 4
1503 
                <br>parameter           P5_EN = 1'b0;   // Enable Port 5
1504 
                <br>parameter           P6_EN = 1'b0;   // Enable Port 6
1505 50 olivier.gi 
        </code>
1506 
</td>
1507 
</tr>
1508 135 olivier.gi 
</tbody>
1509 50 olivier.gi 
</table>
1510 135 olivier.gi 
 
1511 
<br>
1512 
 
1513 50 olivier.gi 
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
1514 135 olivier.gi 
<br>
1515 
<br>
1516 
 
1517 
<table border="0" cellpadding="0" cellspacing="4">
1518 
 
1519 
<tbody><tr>
1520 
<td width="35"><br>
1521 
</td>
1522 
<td bgcolor="#d0d0d0" width="3"><br>
1523 
</td>
1524 
<td width="15"><br>
1525 
</td>
1526 50 olivier.gi 
<td>
1527 
        <code>
1528 
                      gpio #(.P1_EN(1),
1529 135 olivier.gi 
                <br>       .P2_EN(1),
1530 
                <br>       .P3_EN(1),
1531 
                <br>       .P4_EN(0),
1532 
                <br>       .P5_EN(0),
1533 
                <br>       .P6_EN(0)) gpio_0 (
1534 50 olivier.gi 
        </code>
1535 
</td>
1536 
</tr>
1537 135 olivier.gi 
</tbody>
1538 50 olivier.gi 
</table>
1539 135 olivier.gi 
 
1540 
<br>
1541 
 
1542 50 olivier.gi 
The full pinout of the GPIO module is provided in the following table:
1543 135 olivier.gi 
<br>
1544 
<br>
1545 
 
1546 50 olivier.gi 
<table border="1">
1547 135 olivier.gi 
 
1548 
        <tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b>    </td> <td align="center"><b>Description</b></td> </tr>
1549 
        <tr> <td colspan="4" align="center"> <b><i>Clocks &amp; Resets</i></b>  </td></tr>
1550 50 olivier.gi 
        <tr> <td> mclk           </td> <td>  Input         </td> <td>       1        </td> <td> Main system clock                           </td> </tr>
1551 116 olivier.gi 
        <tr> <td> puc_rst        </td> <td>  Input         </td> <td>       1        </td> <td> Main system reset                           </td> </tr>
1552 50 olivier.gi 
        <tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b>  </td></tr>
1553 
        <tr> <td> irq_port1      </td> <td>  Output        </td> <td>       1        </td> <td> Port 1 interrupt                            </td> </tr>
1554 
        <tr> <td> irq_port2      </td> <td>  Output        </td> <td>       1        </td> <td> Port 2 interrupt                            </td> </tr>
1555 
        <tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b>  </td></tr>
1556 
        <tr> <td> per_addr       </td> <td>  Input         </td> <td>       8        </td> <td> Peripheral address                          </td> </tr>
1557 
        <tr> <td> per_din        </td> <td>  Input         </td> <td>      16        </td> <td> Peripheral data input                       </td> </tr>
1558 
        <tr> <td> per_dout       </td> <td>  Output        </td> <td>      16        </td> <td> Peripheral data output                      </td> </tr>
1559 
        <tr> <td> per_en         </td> <td>  Input         </td> <td>       1        </td> <td> Peripheral enable (high active)             </td> </tr>
1560 
        <tr> <td> per_wen        </td> <td>  Input         </td> <td>       2        </td> <td> Peripheral write enable (high active)       </td> </tr>
1561 
        <tr> <td colspan="4" align="center"> <b><i>Port 1</i></b>  </td></tr>
1562 
        <tr> <td> p1_din         </td> <td>  Input         </td> <td>       8        </td> <td> Port 1 data input                           </td> </tr>
1563 
        <tr> <td> p1_dout        </td> <td>  Output        </td> <td>       8        </td> <td> Port 1 data output                          </td> </tr>
1564 
        <tr> <td> p1_dout_en     </td> <td>  Output        </td> <td>       8        </td> <td> Port 1 data output enable                   </td> </tr>
1565 
        <tr> <td> p1_sel         </td> <td>  Output        </td> <td>       8        </td> <td> Port 1 function select                      </td> </tr>
1566 
        <tr> <td colspan="4" align="center"> <b><i>Port 2</i></b>  </td></tr>
1567 
        <tr> <td> p2_din         </td> <td>  Input         </td> <td>       8        </td> <td> Port 2 data input                           </td> </tr>
1568 
        <tr> <td> p2_dout        </td> <td>  Output        </td> <td>       8        </td> <td> Port 2 data output                          </td> </tr>
1569 
        <tr> <td> p2_dout_en     </td> <td>  Output        </td> <td>       8        </td> <td> Port 2 data output enable                   </td> </tr>
1570 
        <tr> <td> p2_sel         </td> <td>  Output        </td> <td>       8        </td> <td> Port 2 function select                      </td> </tr>
1571 
        <tr> <td colspan="4" align="center"> <b><i>Port 3</i></b>  </td></tr>
1572 
        <tr> <td> p3_din         </td> <td>  Input         </td> <td>       8        </td> <td> Port 3 data input                           </td> </tr>
1573 
        <tr> <td> p3_dout        </td> <td>  Output        </td> <td>       8        </td> <td> Port 3 data output                          </td> </tr>
1574 
        <tr> <td> p3_dout_en     </td> <td>  Output        </td> <td>       8        </td> <td> Port 3 data output enable                   </td> </tr>
1575 
        <tr> <td> p3_sel         </td> <td>  Output        </td> <td>       8        </td> <td> Port 3 function select                      </td> </tr>
1576 
        <tr> <td colspan="4" align="center"> <b><i>Port 4</i></b>  </td></tr>
1577 
        <tr> <td> p4_din         </td> <td>  Input         </td> <td>       8        </td> <td> Port 4 data input                           </td> </tr>
1578 
        <tr> <td> p4_dout        </td> <td>  Output        </td> <td>       8        </td> <td> Port 4 data output                          </td> </tr>
1579 
        <tr> <td> p4_dout_en     </td> <td>  Output        </td> <td>       8        </td> <td> Port 4 data output enable                   </td> </tr>
1580 
        <tr> <td> p4_sel         </td> <td>  Output        </td> <td>       8        </td> <td> Port 4 function select                      </td> </tr>
1581 
        <tr> <td colspan="4" align="center"> <b><i>Port 5</i></b>  </td></tr>
1582 
        <tr> <td> p5_din         </td> <td>  Input         </td> <td>       8        </td> <td> Port 5 data input                           </td> </tr>
1583 
        <tr> <td> p5_dout        </td> <td>  Output        </td> <td>       8        </td> <td> Port 5 data output                          </td> </tr>
1584 
        <tr> <td> p5_dout_en     </td> <td>  Output        </td> <td>       8        </td> <td> Port 5 data output enable                   </td> </tr>
1585 
        <tr> <td> p5_sel         </td> <td>  Output        </td> <td>       8        </td> <td> Port 5 function select                      </td> </tr>
1586 
        <tr> <td colspan="4" align="center"> <b><i>Port 6</i></b>  </td></tr>
1587 
        <tr> <td> p6_din         </td> <td>  Input         </td> <td>       8        </td> <td> Port 6 data input                           </td> </tr>
1588 
        <tr> <td> p6_dout        </td> <td>  Output        </td> <td>       8        </td> <td> Port 6 data output                          </td> </tr>
1589 
        <tr> <td> p6_dout_en     </td> <td>  Output        </td> <td>       8        </td> <td> Port 6 data output enable                   </td> </tr>
1590 
        <tr> <td> p6_sel         </td> <td>  Output        </td> <td>       8        </td> <td> Port 6 function select                      </td> </tr>
1591 135 olivier.gi 
      </tbody>
1592 
</table>
1593 
 
1594 50 olivier.gi 
 
1595 
<a name="2.2.4 Timer A"></a>
1596 135 olivier.gi 
<h3>2.3.2 Timer A (FPGA ONLY)</h3>
1597 50 olivier.gi 
 
1598 135 olivier.gi 
 
1599 
 
1600 69 olivier.gi 
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
1601 135 olivier.gi 
<br>
1602 
<br>
1603 
 
1604 50 olivier.gi 
The full pinout of the Timer A module is provided in the following table:
1605 135 olivier.gi 
<br>
1606 
<br>
1607 
 
1608 50 olivier.gi 
<table border="1">
1609 135 olivier.gi 
 
1610 
        <tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b>    </td> <td align="center"><b>Description</b></td> </tr>
1611 
        <tr> <td colspan="4" align="center"> <b><i>Clocks, Resets &amp; Debug</i></b>  </td></tr>
1612 50 olivier.gi 
        <tr> <td> mclk           </td> <td>  Input         </td> <td>       1        </td> <td> Main system clock                          </td> </tr>
1613 
        <tr> <td> aclk_en        </td> <td>  Input         </td> <td>       1        </td> <td> ACLK enable (from CPU)                     </td> </tr>
1614 
        <tr> <td> smclk_en       </td> <td>  Input         </td> <td>       1        </td> <td> SMCLK enable (from CPU)                    </td> </tr>
1615 
        <tr> <td> inclk          </td> <td>  Input         </td> <td>       1        </td> <td> INCLK external timer clock (SLOW)          </td> </tr>
1616 
        <tr> <td> taclk          </td> <td>  Input         </td> <td>       1        </td> <td> TACLK external timer clock (SLOW)          </td> </tr>
1617 116 olivier.gi 
        <tr> <td> puc_rst        </td> <td>  Input         </td> <td>       1        </td> <td> Main system reset                          </td> </tr>
1618 50 olivier.gi 
        <tr> <td> dbg_freeze     </td> <td>  Input         </td> <td>       1        </td> <td> Freeze Timer A counter                     </td> </tr>
1619 
        <tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b>  </td></tr>
1620 
        <tr> <td> irq_ta0        </td> <td>  Output        </td> <td>       1        </td> <td> Timer A interrupt: TACCR0                  </td> </tr>
1621 
        <tr> <td> irq_ta1        </td> <td>  Output        </td> <td>       1        </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2    </td> </tr>
1622 
        <tr> <td> irq_ta0_acc    </td> <td>  Input         </td> <td>       1        </td> <td> Interrupt request TACCR0 accepted          </td> </tr>
1623 
        <tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b>  </td></tr>
1624 
        <tr> <td> per_addr       </td> <td>  Input         </td> <td>       8        </td> <td> Peripheral address                         </td> </tr>
1625 
        <tr> <td> per_din        </td> <td>  Input         </td> <td>      16        </td> <td> Peripheral data input                      </td> </tr>
1626 
        <tr> <td> per_dout       </td> <td>  Output        </td> <td>      16        </td> <td> Peripheral data output                     </td> </tr>
1627 
        <tr> <td> per_en         </td> <td>  Input         </td> <td>       1        </td> <td> Peripheral enable (high active)            </td> </tr>
1628 
        <tr> <td> per_wen        </td> <td>  Input         </td> <td>       2        </td> <td> Peripheral write enable (high active)      </td> </tr>
1629 
        <tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b>  </td></tr>
1630 
        <tr> <td> ta_cci0a       </td> <td>  Input         </td> <td>       1        </td> <td> Timer A capture 0 input A                  </td> </tr>
1631 
        <tr> <td> ta_cci0b       </td> <td>  Input         </td> <td>       1        </td> <td> Timer A capture 0 input B                  </td> </tr>
1632 
        <tr> <td> ta_out0        </td> <td>  Output        </td> <td>       1        </td> <td> Timer A output 0                           </td> </tr>
1633 
        <tr> <td> ta_out0_en     </td> <td>  Output        </td> <td>       1        </td> <td> Timer A output 0 enable                    </td> </tr>
1634 
        <tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b>  </td></tr>
1635 
        <tr> <td> ta_cci1a       </td> <td>  Input         </td> <td>       1        </td> <td> Timer A capture 1 input A                  </td> </tr>
1636 
        <tr> <td> ta_cci1b       </td> <td>  Input         </td> <td>       1        </td> <td> Timer A capture 1 input B                  </td> </tr>
1637 
        <tr> <td> ta_out1        </td> <td>  Output        </td> <td>       1        </td> <td> Timer A output 1                           </td> </tr>
1638 
        <tr> <td> ta_out1_en     </td> <td>  Output        </td> <td>       1        </td> <td> Timer A output 1 enable                    </td> </tr>
1639 
        <tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b>  </td></tr>
1640 
        <tr> <td> ta_cci2a       </td> <td>  Input         </td> <td>       1        </td> <td> Timer A capture 2 input A                  </td> </tr>
1641 
        <tr> <td> ta_cci2b       </td> <td>  Input         </td> <td>       1        </td> <td> Timer A capture 2 input B                  </td> </tr>
1642 
        <tr> <td> ta_out2        </td> <td>  Output        </td> <td>       1        </td> <td> Timer A output 2                           </td> </tr>
1643 
        <tr> <td> ta_out2_en     </td> <td>  Output        </td> <td>       1        </td> <td> Timer A output 2 enable                    </td> </tr>
1644 135 olivier.gi 
</tbody>
1645 69 olivier.gi 
</table>
1646 135 olivier.gi 
 
1647 
<br>
1648 69 olivier.gi 
 
1649 135 olivier.gi 
<b>Note</b>: for the same reason as with the Basic Clock Module FPGA version, the
1650 
two additional clock inputs (TACLK and INCLK) are internally
1651 
synchronized with the MCLK domain.
1652 
As a consequence, TACLK and INCLK should be at least 2 times slowlier
1653 
than MCLK, and if these clock are used toghether with the Timer A
1654 
output unit, some jitter might be observed on the generated output.
1655 
If this jitter is critical for the application, ACLK and INCLK should
1656 
idealy be derivated from DCO_CLK.
1657 
<br>
1658 
<br>
1659 
<br>
1660 
 
1661 
<br><br>
1662 
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