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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html>
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<head>
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<title>openMSP430 Core</title>
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</head>
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<body>
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<h3>Table of content</h3>
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<ul>
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<li><a href="#1. Introduction">1. Introduction</a></li>
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<li><a href="#2. Design"> 2. Design</a>
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<ul>
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<li><a href="#2.1 Core"> 2.1 Core</a>
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<ul>
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<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
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<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
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<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
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<li><a href="#2.1.4 Pinout"> 2.1.4 Pinout</a></li>
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<li><a href="#2.1.5 Instruction Cycles and Lengths">2.1.5 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.6 Serial Debug Interface"> 2.1.6 Serial Debug Interface</a></li>
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</ul>
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</li>
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<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
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<ul>
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<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
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<li><a href="#2.2.2 Watchdog Timer"> 2.2.2 Watchdog Timer</a></li>
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<li><a href="#2.2.3 Digital I/O"> 2.2.3 Digital I/O</a></li>
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<li><a href="#2.2.4 Timer A"> 2.2.4 Timer A</a></li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The openMSP430 is a 16-bit microcontroller core compatible with TI's MSP430 family (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
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<br /><br />
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This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
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<br /><br />
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This IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
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However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
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<br /><br />
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In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
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<br /><br />
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<a name="2. Design"></a>
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<h1>2. Design</h1>
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<a name="2.1 Core"></a>
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<h2>2.1 Core</h2>
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<a name="2.1.1 Design structure"></a>
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<h3>2.1.1 Design structure</h3>
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The following diagram shows the openMSP430 design structure:
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<br /><br />
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<img src="getimg.php?1262105776" width="100%" alt="CPU Structure" title="CPU Structure" />
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<br />
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<ul>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li>
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<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
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<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
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<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
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</ul>
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<a name="2.1.2 Limitations"></a>
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<h3>2.1.2 Limitations</h3>
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The known core limitations are the following:
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<br />
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<ul>
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<li>Instructions can't be executed from the data memory.</li>
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<li>SCG0 is not implemented (turns off DCO).</li>
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<li>MCLK can't be divided and can only have DCO_CLK as source (see <a href="#2.2.1 Basic Clock Module">Basic Clock Module</a> section).</li>
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</ul>
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<a name="2.1.3 Configuration"></a>
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<h3>2.1.3 Configuration</h3>
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It is possible to configure the openMSP430 core through the "openMSP430_defines.v" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
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Two parameters can be adjusted by the user in order to define the program and data memory sizes:
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<br /><br />
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<table border="0" cellspacing="4" cellpadding="0">
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<tr>
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<td width="35"></td>
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<td bgcolor="#d0d0d0" width="3"></td>
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<td width="15"></td>
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<td>
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<code>
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// Program Memory Size
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<br />// 9 -> 1 kB
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<br />// 10 -> 2 kB
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<br />// 11 -> 4 kB
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<br />// 12 -> 8 kB
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<br />// 13 -> 16 kB
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<br />// 14 -> 32 kB
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<br />`define PMEM_AWIDTH 10
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<br />
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<br />// Data Memory Size
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<br />// 6 -> 128 B
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<br />// 7 -> 256 B
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<br />// 8 -> 512 B
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<br />// 9 -> 1 kB
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<br />// 10 -> 2 kB
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<br />// 11 -> 4 kB
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<br />// 12 -> 8 kB
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<br />// 13 -> 16 kB
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<br />// 14 -> 32 kB
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<br />`define DMEM_AWIDTH 6
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</code>
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</td>
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</tr>
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</table>
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<br /><br />
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<b>Note:</b> Program and data memories <b>SHOULD NOT</b> be both set to 32 kB
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<br /><br /><br />
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The following parameters define if the debug interface should be included or not and how many hardware breakpoint units should be included.
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<br /><br />
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<table border="0" cellspacing="4" cellpadding="0">
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<tr>
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<td width="35"></td>
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<td bgcolor="#d0d0d0" width="3"></td>
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<td width="15"></td>
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<td>
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<code>
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//----------------------------------------------------------------------------
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<br />// REMOTE DEBUGGING INTERFACE CONFIGURATION
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<br />//----------------------------------------------------------------------------
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<br />
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<br />// Include Debug interface
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<br />`define DBG_EN
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<br />
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<br />// Debug interface selection
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<br />// `define DBG_UART -> Enable UART (8N1) debug interface
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<br />// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
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<br />//
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<br />`define DBG_UART
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<br />//`define DBG_JTAG
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<br />
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<br />// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
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<br />// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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<br />// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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<br />// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
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<br />// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
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<br />//
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<br />`define DBG_HWBRK_0
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<br />`define DBG_HWBRK_1
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<br />`define DBG_HWBRK_2
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<br />`define DBG_HWBRK_3
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</code>
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</td>
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</tr>
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</table>
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<br /><br />
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<b>Note:</b> Since the hardware breakpoint units are relatively big, it is recommended to include as many as you plan to use. These units are particularly useful if your instruction memory is a ROM (i.e. when you can't use software breakpoints) or if you want to be able to stop the CPU whenever some particular data addresses are accessed.
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<br /><br /><br />
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All remaining defines located in this file are system constants and should not be edited.
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<a name="2.1.4 Pinout"></a>
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<h3>2.1.4 Pinout</h3>
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The full pinout of the openMSP430 core is provided in the following table:
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<br /><br />
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<table border="1">
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<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
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<tr>
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<td> dco_clk </td>
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<td> Input </td>
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<td> 1 </td>
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<td> Fast oscillator (fast clock), CPU clock </td>
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</tr>
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<tr>
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<td> lfxt_clk </td>
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<td> Input </td>
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<td> 1 </td>
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<td> Low frequency oscillator (typ. 32kHz) </td>
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</tr>
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<tr>
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<td> mclk </td>
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<td> Output </td>
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<td> 1 </td>
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<td> Main system clock </td>
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</tr>
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<tr>
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<td> aclk_en </td>
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<td> Output </td>
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<td> 1 </td>
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<td> ACLK enable </td>
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</tr>
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<tr>
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<td> smclk_en </td>
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<td> Output </td>
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<td> 1 </td>
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<td> SMCLK enable </td>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
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<tr>
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<td> puc </td>
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<td> Output </td>
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<td> 1 </td>
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<td> Main system reset </td>
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</tr>
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<tr>
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<td> reset_n </td>
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<td> Input </td>
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<td> 1 </td>
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<td> Reset Pin (low active) </td>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
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<tr>
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<td> pmem_addr </td>
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<td> Output </td>
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<td> `PMEM_AWIDTH<sup>1</sup> </td>
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<td> Program Memory address </td>
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</tr>
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<tr>
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<td> pmem_cen </td>
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<td> Output </td>
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<td> 1 </td>
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<td> Program Memory chip enable (low active) </td>
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</tr>
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<tr>
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<td> pmem_din </td>
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<td> Output </td>
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<td> 16 </td>
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<td> Program Memory data input (optional<sup>2</sup>) </td>
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</tr>
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<tr>
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<td> pmem_dout </td>
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<td> Input </td>
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<td> 16 </td>
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<td> Program Memory data output </td>
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</tr>
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<tr>
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<td> pmem_wen </td>
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<td> Output </td>
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<td> 2 </td>
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<td> Program Memory write enable (low active) (optional<sup>2</sup>) </td>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
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<tr>
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<td> dmem_addr </td>
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<td> Output </td>
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<td> `DMEM_AWIDTH<sup>1</sup> </td>
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<td> Data Memory address </td>
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</tr>
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<tr>
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<td> dmem_cen </td>
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<td> Output </td>
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<td> 1 </td>
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<td> Data Memory chip enable (low active) </td>
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</tr>
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<tr>
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<td> dmem_din </td>
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<td> Output </td>
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<td> 16 </td>
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<td> Data Memory data input </td>
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</tr>
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<tr>
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<td> dmem_dout </td>
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<td> Input </td>
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<td> 16 </td>
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<td> Data Memory data output </td>
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</tr>
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<tr>
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<td> dmem_wen </td>
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<td> Output </td>
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<td> 2 </td>
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<td> Data Memory write enable (low active) </td>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
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<tr>
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<td> per_addr </td>
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<td> Output </td>
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<td> 8 </td>
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<td> Peripheral address </td>
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</tr>
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<tr>
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<td> per_din </td>
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<td> Output </td>
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<td> 16 </td>
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<td> Peripheral data input </td>
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</tr>
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<tr>
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<td> per_dout </td>
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<td> Input </td>
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<td> 16 </td>
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<td> Peripheral data output </td>
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</tr>
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<tr>
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<td> per_en </td>
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<td> Output </td>
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<td> 1 </td>
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<td> Peripheral enable (high active) </td>
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</tr>
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<tr>
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<td> per_wen </td>
|
| 310 |
|
|
<td> Output </td>
|
| 311 |
|
|
<td> 2 </td>
|
| 312 |
|
|
<td> Peripheral write enable (high active) </td>
|
| 313 |
|
|
</tr>
|
| 314 |
|
|
|
| 315 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 316 |
|
|
<tr>
|
| 317 |
|
|
<td> irq </td>
|
| 318 |
|
|
<td> Input </td>
|
| 319 |
|
|
<td> 14 </td>
|
| 320 |
|
|
<td> Maskable interrupts (one-hot signal) </td>
|
| 321 |
|
|
</tr>
|
| 322 |
|
|
<tr>
|
| 323 |
|
|
<td> nmi </td>
|
| 324 |
|
|
<td> Input </td>
|
| 325 |
|
|
<td> 1 </td>
|
| 326 |
|
|
<td> Non-maskable interrupt (asynchronous) </td>
|
| 327 |
|
|
</tr>
|
| 328 |
|
|
<tr>
|
| 329 |
|
|
<td> irq_acc </td>
|
| 330 |
|
|
<td> Output </td>
|
| 331 |
|
|
<td> 14 </td>
|
| 332 |
|
|
<td> Interrupt request accepted (one-hot signal) </td>
|
| 333 |
|
|
</tr>
|
| 334 |
|
|
|
| 335 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
| 336 |
|
|
<tr>
|
| 337 |
|
|
<td> dbg_freeze </td>
|
| 338 |
|
|
<td> Output </td>
|
| 339 |
|
|
<td> 1 </td>
|
| 340 |
|
|
<td> Freeze peripherals </td>
|
| 341 |
|
|
</tr>
|
| 342 |
|
|
<tr>
|
| 343 |
|
|
<td> dbg_uart_txd </td>
|
| 344 |
|
|
<td> Output </td>
|
| 345 |
|
|
<td> 1 </td>
|
| 346 |
|
|
<td> Debug interface: UART TXD </td>
|
| 347 |
|
|
</tr>
|
| 348 |
|
|
<tr>
|
| 349 |
|
|
<td> dbg_uart_rxd </td>
|
| 350 |
|
|
<td> Input </td>
|
| 351 |
|
|
<td> 1 </td>
|
| 352 |
|
|
<td> Debug interface: UART RXD </td>
|
| 353 |
|
|
</tr>
|
| 354 |
|
|
</table>
|
| 355 |
|
|
<br />
|
| 356 |
|
|
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
|
| 357 |
|
|
<sup>2</sup>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.
|
| 358 |
|
|
<br /><br />
|
| 359 |
|
|
|
| 360 |
|
|
<a name="2.1.5 Instruction Cycles and Lengths"></a>
|
| 361 |
|
|
<h3>2.1.5 Instruction Cycles and Lengths</h3>
|
| 362 |
|
|
|
| 363 |
|
|
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.
|
| 364 |
|
|
<br />In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
| 365 |
|
|
Differences with the original MSP430 are highlighted in green (the original value being red).
|
| 366 |
|
|
<ul>
|
| 367 |
|
|
<li><b>Interrupt and Reset Cycles</b></li>
|
| 368 |
|
|
</ul>
|
| 369 |
|
|
<table border="1">
|
| 370 |
|
|
<tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
|
| 371 |
|
|
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
|
| 372 |
|
|
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
|
| 373 |
|
|
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
| 374 |
|
|
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
| 375 |
|
|
</table>
|
| 376 |
|
|
|
| 377 |
|
|
<ul>
|
| 378 |
|
|
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
|
| 379 |
|
|
</ul>
|
| 380 |
|
|
<table border="1">
|
| 381 |
|
|
<tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
| 382 |
|
|
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
|
| 383 |
|
|
|
| 384 |
|
|
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 385 |
|
|
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
|
| 386 |
|
|
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 387 |
|
|
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 388 |
|
|
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 389 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 390 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 391 |
|
|
</table>
|
| 392 |
|
|
|
| 393 |
|
|
<ul>
|
| 394 |
|
|
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
|
| 395 |
|
|
</ul>
|
| 396 |
|
|
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
|
| 397 |
|
|
|
| 398 |
|
|
<ul>
|
| 399 |
|
|
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
|
| 400 |
|
|
</ul>
|
| 401 |
|
|
<table border="1">
|
| 402 |
|
|
<tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
| 403 |
|
|
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
|
| 404 |
|
|
|
| 405 |
|
|
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
|
| 406 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 407 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 408 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 409 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
| 410 |
|
|
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 411 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
|
| 412 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 413 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 414 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 415 |
|
|
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
| 416 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
|
| 417 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 418 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 419 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
| 420 |
|
|
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
|
| 421 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 422 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 423 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 424 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
| 425 |
|
|
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 426 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
| 427 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 428 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 429 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 430 |
|
|
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 431 |
|
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
| 432 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 433 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 434 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 435 |
|
|
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 436 |
|
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
| 437 |
|
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 438 |
|
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 439 |
|
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
| 440 |
|
|
</table>
|
| 441 |
|
|
|
| 442 |
|
|
<a name="2.1.6 Serial Debug Interface"></a>
|
| 443 |
|
|
<h3>2.1.6 Serial Debug Interface</h3>
|
| 444 |
|
|
|
| 445 |
|
|
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
|
| 446 |
|
|
<a name="2.2 Peripherals"></a>
|
| 447 |
|
|
<h2>2.2 Peripherals</h2>
|
| 448 |
|
|
|
| 449 |
|
|
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
|
| 450 |
|
|
|
| 451 |
|
|
<a name="2.2.1 Basic Clock Module"></a>
|
| 452 |
|
|
<h3>2.2.1 Basic Clock Module</h3>
|
| 453 |
|
|
|
| 454 |
|
|
In order to make an FPGA implementation as simple as possible (ideally, a non-designer should be able to do it), clock gates are not used in the design and neither are clock muxes.
|
| 455 |
|
|
<br />
|
| 456 |
|
|
With these constrains, the Basic Clock Module is implemented as following:
|
| 457 |
|
|
<br /><br />
|
| 458 |
|
|
<img src="getimg.php?1249244393" alt="Clock structure diagram" title="Clock structure diagram" />
|
| 459 |
|
|
<br />
|
| 460 |
|
|
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.
|
| 461 |
|
|
<br /><br />
|
| 462 |
|
|
|
| 463 |
|
|
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
|
| 464 |
|
|
<br /><br />
|
| 465 |
|
|
<img src="getimg.php?1246434793" alt="Clock implementation example" title="Clock implementation example" />
|
| 466 |
|
|
<br /><br />
|
| 467 |
|
|
The following Verilog code would implement a counter clocked with SMCLK:
|
| 468 |
|
|
<br />
|
| 469 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 470 |
|
|
<tr>
|
| 471 |
|
|
<td width="35"></td>
|
| 472 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 473 |
|
|
<td width="15"></td>
|
| 474 |
|
|
<td>
|
| 475 |
|
|
<code>
|
| 476 |
|
|
reg [7:0] test_cnt;
|
| 477 |
|
|
<br />
|
| 478 |
|
|
<br />always @ (posedge mclk or posedge puc)
|
| 479 |
|
|
<br /> if (puc) test_cnt <= 8'h00;
|
| 480 |
|
|
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
| 481 |
|
|
</code>
|
| 482 |
|
|
</td>
|
| 483 |
|
|
</tr>
|
| 484 |
|
|
</table>
|
| 485 |
|
|
<br /><br />
|
| 486 |
|
|
<b>Register Description</b>
|
| 487 |
|
|
<ul>
|
| 488 |
|
|
<li>DCOCTL: Not implemented</li>
|
| 489 |
|
|
<li>BCSCTL1:
|
| 490 |
|
|
<ul>
|
| 491 |
|
|
<li>BCSCTL1[7:6]: Unused</li>
|
| 492 |
|
|
<li>BCSCTL1[5:4]: DIVAx</li>
|
| 493 |
|
|
<li>BCSCTL1[4:0]: Unused</li>
|
| 494 |
|
|
</ul>
|
| 495 |
|
|
</li>
|
| 496 |
|
|
<li>BCSCTL2:
|
| 497 |
|
|
<ul>
|
| 498 |
|
|
<li>BCSCTL2[7:4]: Unused</li>
|
| 499 |
|
|
<li>BCSCTL2[3] : SELS</li>
|
| 500 |
|
|
<li>BCSCTL2[2:1]: DIVSx</li>
|
| 501 |
|
|
<li>BCSCTL2[0] : Unused</li>
|
| 502 |
|
|
</ul>
|
| 503 |
|
|
</li>
|
| 504 |
|
|
</ul>
|
| 505 |
|
|
|
| 506 |
|
|
<a name="2.2.2 Watchdog Timer"></a>
|
| 507 |
|
|
<h3>2.2.2 Watchdog Timer</h3>
|
| 508 |
|
|
|
| 509 |
|
|
100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 10) have been implemented.
|
| 510 |
|
|
|
| 511 |
|
|
<a name="2.2.3 Digital I/O"></a>
|
| 512 |
|
|
<h3>2.2.3 Digital I/O</h3>
|
| 513 |
|
|
|
| 514 |
|
|
100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 9) have been implemented.
|
| 515 |
|
|
<br /><br />
|
| 516 |
|
|
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
|
| 517 |
|
|
<br /><br />
|
| 518 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 519 |
|
|
<tr>
|
| 520 |
|
|
<td width="35"></td>
|
| 521 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 522 |
|
|
<td width="15"></td>
|
| 523 |
|
|
<td>
|
| 524 |
|
|
<code>
|
| 525 |
|
|
parameter P1_EN = 1'b1; // Enable Port 1
|
| 526 |
|
|
<br />parameter P2_EN = 1'b1; // Enable Port 2
|
| 527 |
|
|
<br />parameter P3_EN = 1'b0; // Enable Port 3
|
| 528 |
|
|
<br />parameter P4_EN = 1'b0; // Enable Port 4
|
| 529 |
|
|
<br />parameter P5_EN = 1'b0; // Enable Port 5
|
| 530 |
|
|
<br />parameter P6_EN = 1'b0; // Enable Port 6
|
| 531 |
|
|
</code>
|
| 532 |
|
|
</td>
|
| 533 |
|
|
</tr>
|
| 534 |
|
|
</table>
|
| 535 |
|
|
<br />
|
| 536 |
|
|
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
|
| 537 |
|
|
<br /><br />
|
| 538 |
|
|
<table border="0" cellspacing="4" cellpadding="0">
|
| 539 |
|
|
<tr>
|
| 540 |
|
|
<td width="35"></td>
|
| 541 |
|
|
<td bgcolor="#d0d0d0" width="3"></td>
|
| 542 |
|
|
<td width="15"></td>
|
| 543 |
|
|
<td>
|
| 544 |
|
|
<code>
|
| 545 |
|
|
gpio #(.P1_EN(1),
|
| 546 |
|
|
<br /> .P2_EN(1),
|
| 547 |
|
|
<br /> .P3_EN(1),
|
| 548 |
|
|
<br /> .P4_EN(0),
|
| 549 |
|
|
<br /> .P5_EN(0),
|
| 550 |
|
|
<br /> .P6_EN(0)) gpio_0 (
|
| 551 |
|
|
</code>
|
| 552 |
|
|
</td>
|
| 553 |
|
|
</tr>
|
| 554 |
|
|
</table>
|
| 555 |
|
|
<br />
|
| 556 |
|
|
The full pinout of the GPIO module is provided in the following table:
|
| 557 |
|
|
<br /><br />
|
| 558 |
|
|
<table border="1">
|
| 559 |
|
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 560 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
| 561 |
|
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 562 |
|
|
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 563 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 564 |
|
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
| 565 |
|
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
| 566 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 567 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 568 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 569 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 570 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 571 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 572 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
|
| 573 |
|
|
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
|
| 574 |
|
|
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
|
| 575 |
|
|
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
|
| 576 |
|
|
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
|
| 577 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
|
| 578 |
|
|
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
|
| 579 |
|
|
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
|
| 580 |
|
|
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
|
| 581 |
|
|
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
|
| 582 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
|
| 583 |
|
|
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
|
| 584 |
|
|
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
|
| 585 |
|
|
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
|
| 586 |
|
|
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
|
| 587 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
|
| 588 |
|
|
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
|
| 589 |
|
|
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
|
| 590 |
|
|
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
|
| 591 |
|
|
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
|
| 592 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
|
| 593 |
|
|
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
|
| 594 |
|
|
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
|
| 595 |
|
|
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
|
| 596 |
|
|
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
|
| 597 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
|
| 598 |
|
|
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
|
| 599 |
|
|
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
|
| 600 |
|
|
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
|
| 601 |
|
|
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
|
| 602 |
|
|
</table>
|
| 603 |
|
|
|
| 604 |
|
|
<a name="2.2.4 Timer A"></a>
|
| 605 |
|
|
<h3>2.2.4 Timer A</h3>
|
| 606 |
|
|
|
| 607 |
|
|
100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 11) have been implemented.
|
| 608 |
|
|
<br /><br />
|
| 609 |
|
|
The full pinout of the Timer A module is provided in the following table:
|
| 610 |
|
|
<br /><br />
|
| 611 |
|
|
<table border="1">
|
| 612 |
|
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 613 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
|
| 614 |
|
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 615 |
|
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
| 616 |
|
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
| 617 |
|
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
| 618 |
|
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
| 619 |
|
|
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 620 |
|
|
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
|
| 621 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 622 |
|
|
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
|
| 623 |
|
|
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
|
| 624 |
|
|
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
|
| 625 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 626 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 627 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 628 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 629 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 630 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 631 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
|
| 632 |
|
|
<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
|
| 633 |
|
|
<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
|
| 634 |
|
|
<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
|
| 635 |
|
|
<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
|
| 636 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
|
| 637 |
|
|
<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
|
| 638 |
|
|
<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
|
| 639 |
|
|
<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
|
| 640 |
|
|
<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
|
| 641 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
|
| 642 |
|
|
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
|
| 643 |
|
|
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
|
| 644 |
|
|
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
|
| 645 |
|
|
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
|
| 646 |
|
|
</table>
|
| 647 |
|
|
<br />
|
| 648 |
|
|
<b>Note</b>: for the same reason as with the Basic Clock Module, the two additional clock inputs (TACLK and INCLK) are internally synchronized with the MCLK domain.
|
| 649 |
|
|
As a consequence, TACLK and INCLK should be at least 2 times slowlier than MCLK, and if these clock are used toghether with the Timer A output unit, some jitter might be observed on the generated output.
|
| 650 |
|
|
If this jitter is critical for the application, ACLK and INCLK should idealy be derivated from DCO_CLK.
|
| 651 |
|
|
|
| 652 |
|
|
</body>
|
| 653 |
|
|
</html>
|
