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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 DMA Interface</title>
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<meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body>
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<h3>Table of content</h3>
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<ul>
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  <li><a href="#1.%20Introduction">         1. Introduction</a></li>
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  <li><a href="#2.%20Signal%20list">        2. Signal list</a></li>
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  <li><a href="#3.%20Protocol">             3. Protocol</a></li>
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        <ul>
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       <li><a href="#3.1%20Simple%20transfer">               3.1 Simple transfer</a></li>
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       <li><a href="#3.2%20Transfer%20with%20wait%20states"> 3.2 Transfer with wait states</a></li>
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       <li><a href="#3.3%20Multiple%20transfers">            3.3 Multiple transfers</a></li>
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       <li><a href="#3.4%20Transfer%20response">             3.4 Transfer response</a></li>
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       <li><a href="#3.5%20Priority%20control">              3.5 Priority control</a></li>
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           <ul>
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          <li><a href="#3.5.1%20Data%20rate%20control">      3.5.1 Data rate control</a></li>
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          <li><a href="#3.5.2%20Bootloader%20case">          3.5.2 Bootloader case</a></li>
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           </ul>
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        </ul>
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  <li><a href="#4.%20ASIC%20Implementation">4. ASIC Implementation</a></li>
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        <ul>
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           <li><a href="#4.1%20Clock%20domains">     4.1 Clock domains</a></li>
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       <li><a href="#4.2%20DMA%20wakeup">        4.2 DMA wakeup</a></li>
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        </ul>
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</ul>
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<a name="1.%20Introduction"></a>
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<h1>1. Introduction</h1>
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The openMSP430 Direct-Memory-Access interface acts as a gateway to the whole logical 64kB memory space and can
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be enabled be uncommenting the DMA_IF_EN macro in the <i>"openMSP430_defines.sv"</i> file:<br><br>
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<code>
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//-------------------------------------------------------<br>
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// Include/Exclude DMA interface support<br>
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//-------------------------------------------------------<br>
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`define DMA_IF_EN<br>
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</code>
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<br>
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It supports the efficient connection of Bootloader, DMA controller, Memory-BIST or any other hardware
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unit requiring direct read/write access to the CPU memory space.
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<br>
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The interface is also designed as to reuse the existing arbitration logic within the memory-backbone
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and thus minimize to timing costs of its physical implementation (i.e. no additional muxing layer on
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an already critical timing path).
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<br><br>
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An simple system using the DMA interface typically consists of a DMA master directly connected to
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openMSP430 core:
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<br><img src="http://opencores.org/usercontent,img,1431381105" alt="DMA simple systems" title="DMA simple systems" width="80%">
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<br><br>
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However, it is also possible to combine different DMA masters using a custom arbitration logic:
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<br><img src="http://opencores.org/usercontent,img,1431381122" alt="DMA complex system" title="DMA complex system" width="80%">
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<br><br>
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<a name="2.%20Signal%20list"></a>
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<h1>2. Signal list</h1>
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<table border="1">
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<tbody>
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<tr align="center">
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   <td><b>Name</b></td>
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   <td><b>Source</b></td>
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   <td><b>Type</b></td>
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   <td><b>Description</b></td>
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</tr>
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<tr>
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   <td><b>MCLK</b><br><small>System clock</small></td>
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   <td align="center">&nbsp;openMSP430&nbsp;</td>
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   <td align="center">System</td>
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   <td>This clock times all DMA transfers. All signal timings are related to the rising edge of MCLK.</td>
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</tr>
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<tr>
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   <td><b>PUC_RST</b><br><small>System reset</small></td>
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   <td align="center">&nbsp;openMSP430&nbsp;</td>
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   <td align="center">System</td>
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   <td>The system reset is active HIGH and is used to reset the sytem, including the DMA master(s).</td>
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</tr>
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<tr>
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   <td><b>DMA_WKUP</b><br><small>Wakeup</small></td>
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   <td align="center">DMA Master<br><small>(Asynchronous)</small></td>
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   <td align="center">System</td>
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   <td>When HIGH in a Low-Power-Mode, the wakeup signal restores the clocks necessary for the DMA transfer (see <a href="#4.%20ASIC%20Implementation">ASIC Implementation</a> section).</td>
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</tr>
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<tr>
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   <td><b>DMA_ADDR[15:1]</b><br><small>Address bus</small></td>
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   <td align="center">DMA Master</td>
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   <td align="center">Address</td>
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   <td>This is the 15-bit address bus allowing to access the 64kB address space (16b words).</td>
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</tr>
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<tr>
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   <td><b>DMA_DIN[15:0]</b><br><small>Write data bus</small></td>
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   <td align="center">DMA Master</td>
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   <td align="center">Data</td>
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   <td>The write data bus is used to transfer data from the DMA master to openMSP430 system during write operations.</td>
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</tr>
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<tr>
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   <td><b>DMA_DOUT[15:0]</b><br><small>Read data bus</small></td>
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   <td align="center">&nbsp;openMSP430&nbsp;</td>
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   <td align="center">Data</td>
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   <td>The read data bus is used to transfer data from the openMSP430 system to the DMA master during read operations.</td>
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</tr>
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<tr>
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   <td><b>DMA_EN</b><br><small>Transfer enable</small></td>
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   <td align="center">DMA Master</td>
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   <td align="center">Control</td>
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   <td>Indicates that the current DMA transfer is active.</td>
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</tr>
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<tr>
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   <td><b>DMA_WE[1:0]</b><br><small>Transfer direction</small></td>
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   <td align="center">DMA Master</td>
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   <td align="center">Control</td>
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   <td>When HIGH, this signal indicates a write transfer on the selected byte, and a read transfer when LOW.</td>
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</tr>
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<tr>
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   <td><b>DMA_PRIORITY</b><br><small>Transfer priority</small></td>
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   <td align="center">DMA Master</td>
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   <td align="center">Control</td>
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   <td>When HIGH, this signal indicates a high priority DMA transfer (i.e. CPU is stopped). When LOW, low priority DMA transfer have to wait for the CPU to free the accessed ressource.</td>
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</tr>
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<tr>
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   <td><b>DMA_READY</b><br><small>Transfer done</small></td>
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   <td align="center">&nbsp;openMSP430&nbsp;</td>
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   <td align="center">Response</td>
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   <td>When HIGH the DMA_READY signal indicates that a transfer has finished on the bus. This signal may be driven LOW to add wait states to the transfer.</td>
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</tr>
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<tr>
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   <td><b>DMA_RESP</b><br><small>Transfer response</small></td>
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   <td align="center">&nbsp;openMSP430&nbsp;</td>
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   <td align="center">Response</td>
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   <td>The transfer response provides additional information on the status of a transfer (OKAY if LOW, ERROR when HIGH).</td>
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</tr>
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</tbody>
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</table>
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<br>
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<a name="3.%20Protocol"></a>
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<h1>3. Protocol</h1>
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<a name="3.1%20Simple%20transfer"></a>
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<h2>3.1 Simple transfer</h2>
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The following figure shows the simplest transfer, one with no wait states.<br>
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<br><img src="http://opencores.org/usercontent,img,1431552266" alt="DMA simple transfer" title="DMA simple transfer" width="60%"><br>
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In a simple transfer with no wait states:
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<ul>
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  <li>The DMA master drives the address, control signals and write data onto the bus after the rising edge of MCLK.</li>
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  <li>The openMSP430 ressource (pmem/dmem/peripheral) then samples the address, control and write data information on the next rising edge of the clock.</li>
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  <li>For read access, after the openMSP430 ressource has sampled the address and control it can start to drive the read data
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          and this is sampled by the DMA master on the third rising edge of the clock.</li>
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</ul>
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<a name="3.2%20Transfer%20with%20wait%20states"></a>
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<h2>3.2 Transfer with wait states</h2>
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The openMSP430 can insert wait states into any transfer, as shown in the following figure, which extends
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the transfer by two clock cycles, thus taking additional time for completion.
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<br><img src="http://opencores.org/usercontent,img,1431552287" alt="DMA transfer with wait states" title="DMA transfer with wait states" width="90%"><br>
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For both read and write operations the DMA master must hold the address, control and write data stable throughout the extended cycles.
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<br><br>
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<b>Note:</b> wait states are inserted by the openMSP430 if the CPU is currently busy reading or writing to the same ressource that the DMA controller also wants to access.
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<br>
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<a name="3.3%20Multiple%20transfers"></a>
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<h2>3.3 Multiple transfers</h2>
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The following figure shows three transfers to unrelated addresses, A, B & C.
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<br><img src="http://opencores.org/usercontent,img,1431552310" alt="DMA multiple transfer" title="DMA multiple transfer" width="100%"><br>
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We can here observe:
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<ul>
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  <li>the transfers to addresses A and C are both zero wait state.</li>
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  <li>the transfer to address B is one wait state.</li>
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  <li>the read data from A is available during the <b>first</b> clock cycle when the address and control B are applied.</li>
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  <li>the read data from B is available during the clock cycle when the address and control C are applied.</li>
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</ul>
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<a name="3.4%20Transfer%20response"></a>
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<h2>3.4 Transfer response</h2>
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The following figure shows two transfers to unrelated addresses, A & B.
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<br><img src="http://opencores.org/usercontent,img,1431552329" alt="DMA error response" title="DMA error response" width="70%"><br>
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We can here observe:
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<ul>
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  <li>the transfer to address A returns an ERROR response (note that transfer returning an ERROR response <b>never</b> have wait states).</li>
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  <li>the transfer to address B is a regular transfer (i.e. OKAY response) without wait state.</li>
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</ul>
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<b>Note:</b> an ERROR response are generated if the transfer address lays between the program and data memories, where nothing is mapped.
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<br>
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<a name="3.5%20Priority%20control"></a>
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<h2>3.5 Priority control</h2>
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<a name="3.5.1%20Data%20rate%20control"></a>
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<h3>3.5.1 Data rate control</h3>
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The DMA_PRIORITY control signal is available to the DMA master for controlling the application data rate requirements.<br>
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<ul>
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  <li>When CLEARED, DMA transfers have a <b>fixed lower priority</b> than the CPU. This means that depending on the
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exact kind of instructions currently executed by the CPU, the completion time of the DMA transfers cannot be
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predicted (i.e. DMA transfers are completed only when the CPU is not accessing the trageted ressource).</li>
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  <li>When SET, DMA transfers have a <b>fixed higher priority</b> over the CPU. This means that the CPU will
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will stop execution and give the full bandwidth to the DMA controller. In that scenario, DMA transfers complete
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in a single clock cycle (i.e. without any wait states), as the targeted ressources are always available
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(i.e. the CPU is not executing).</li>
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  <li>If the application requirements need something in between (namely a minimum DMA transfer data-rate with reduced effect
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on the firmware exection), then the DMA master can dynamically change the DMA_PRIORITY as required.</li>
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</ul>
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These scenario are illustrated in the following figure.
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<br><img src="http://opencores.org/usercontent,img,1431638398" alt="DMA error response" title="DMA error response" width="100%"><br>
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We can here observe:
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<ul>
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  <li>phase <b>A</b> illustrates LOW-PRIORITY transfers. Less DMA transfer are completed during that time as shown by the number of wait states.</li>
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  <li>phase <b>B</b> illustrates HIGH-PRIORITY transfers. DMA transfers are completed with each clock cycle (i.e. no wait state).</li>
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  <li>phase <b>C</b> illustrates MIXED-PRIORITY transfers where the DMA controller is dynamically adjusting the priority to achieve its target minimum data-rate.</li>
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</ul>
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<a name="3.5.2%20Bootloader%20case"></a>
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<h3>3.5.2 Bootloader case</h3>
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In general, the purpose of a bootloader is to initialize the program memory at startup (i.e after Power-On-Reset).<br>
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DMA transfers driven by the bootloader should therefore be performed in HIGH-PRIORITY mode, as the CPU should not start
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executing instructions on a non-initialized memory.<br>
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Once the memory initialization is completed, a reset pulse should be generated by the bootloader to make sure the CPU
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re-fetches the new RESET vector from the program memory.<br>
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<br>
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A bootloader could be for example be connected as following:
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<br><img src="http://opencores.org/usercontent,img,1431724552" alt="DMA bootloader" title="DMA bootloader" width="50%"><br>
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The bootloading sequence is illustrated in the following figure:
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<br><img src="http://opencores.org/usercontent,img,1431724534" alt="DMA bootloader waveform" title="DMA bootloader waveform" width="100%"><br>
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<a name="4.%20ASIC%20Implementation"></a>
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<h1>4. ASIC Implementation</h1>
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<a name="4.1%20Clock%20domains"></a>
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<h2>4.1 Clock domains</h2>
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If the ASIC low power options are enabled, it is possible to perform DMA accesses when the main CPU is in <b>any</b> Low-Power-Mode (LPMx).<br>
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However, in order to avoid unnecessary power consumption while restoring the clocks for the DMA transfer, the MCLK
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system clock has been split into two clock domains.
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<ul>
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  <li>MCLK_CPU : clocks the CPU core itself, namely the frontend and execution logic.
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                     When the CPU is in LPMx mode, this clock is ALWAYS OFF, even if a DMA transfer is currently on going.</li>
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  <li>MCLK_DMA : clocks the rest of the system (excluding the DBG interface) and gives access to the 64kB memory
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                     adddress range to the DMA master. This clock is restored in LPMx modes by asserting the DMA_WKUP pin.</li>
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</ul>
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This table summarizes the clock operating modes:<br><br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b>Clock Name</b></td>
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<td rowspan="2"><b>CPU Active</b></td>
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<td colspan="2"><b>CPU Low-Power-Mode</b></td>
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</tr>
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<tr align="center">
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<td>DMA_WKUP=0</td>
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<td>DMA_WKUP=1</td>
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</tr>
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<tr align="center">
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<td>MCLK_CPU</td>
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<td>ON</td>
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<td>OFF</td>
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<td>OFF</td>
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</tr>
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<tr align="center">
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<td>MCLK_DMA</td>
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<td>ON</td>
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<td>OFF</td>
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<td>ON</td>
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</tr>
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</tbody>
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</table>
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<br>
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Clock domains are illustrated in the following diagram:
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<br><img src="http://opencores.org/usercontent,img,1431726489" alt="DMA clock domains" title="DMA clock domains" width="50%"><br>
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<a name="4.2%20DMA%20wakeup"></a>
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<h2>4.2 DMA wakeup</h2>
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As shown in the "Peripherals" chapter, the Basic-Clock-Module has several
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control registers giving some flexibility to the firmware as to which clocks
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are restored when the DMA_WKUP pin is asserted.<br><br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b>Register Name</b></td>
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<td rowspan="2"><b>Address</b></td>
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<td colspan="16"><b>Bit Field</b></td>
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</tr>
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<tr align="center">
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<td>7</td><td>6</td><td>5</td><td>4</td>
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<td>3</td><td>2</td><td>1</td><td>0</td>
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</tr>
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<tr align="center">
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<td>BCSTL1</td>
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<td>0x0006</td>
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<td colspan="2"><small><i>unused</i></small></td>
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<td colspan="2"><b>DIVAx</b></td>
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<td colspan="1"><b><small>DMA_SCG1</small></b></td>
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<td colspan="1"><b><small>DMA_SCG0</small></b></td>
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<td colspan="1"><b><small>DMA_OSCOFF</small></b></td>
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<td colspan="1"><b><small>DMA_CPUOFF</small></b></td>
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</tr>
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</tbody>
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</table>
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<ul>
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        <li><b>DMA_SCG1</b>&nbsp;&nbsp;&emsp;&emsp;: Restore SMCLK with DMA wakeup</li>
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        <li><b>DMA_SCG0</b>&nbsp;&nbsp;&emsp;&emsp;: Restore DCO oscillator with DMA wakeup</li>
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        <li><b>DMA_OSCOFF</b>&emsp;: Restore LFXT oscillator with DMA wakeup</li>
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        <li><b>DMA_CPUOFF</b>&emsp;: Restore MCLK_DMA with DMA wakeup</li>
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</ul>
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Note that the DMA_WKUP functionality can be disabled by keeping all these bitfields <b>CLEARED</b>.
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<br>
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<br>
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