| 1 |
50 |
olivier.gi |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
|
| 2 |
100 |
olivier.gi |
<html><head><title>openMSP430 File & Directory description</title></head><body>
|
| 3 |
50 |
olivier.gi |
<a name="TOC"></a>
|
| 4 |
|
|
<h3>Table of content</h3>
|
| 5 |
|
|
<ul>
|
| 6 |
100 |
olivier.gi |
<li><a href="#1.%20Introduction"> 1. Introduction</a></li>
|
| 7 |
|
|
<li><a href="#2.%20Directory%20structure:%20openMSP430%20core"> 2. Directory structure: openMSP430 core</a></li>
|
| 8 |
|
|
<li><a href="#3.%20Directory%20structure:%20FGPA%20projects"> 3. Directory structure: FGPA projects</a>
|
| 9 |
50 |
olivier.gi |
<ul>
|
| 10 |
100 |
olivier.gi |
<li><a href="#3.1%20Xilinx%20Spartan%203%20example"> 3.1 Xilinx Spartan 3 example</a></li>
|
| 11 |
|
|
<li><a href="#3.2%20Altera%20Cyclone%20II%20example"> 3.2 Altera Cyclone II example</a></li>
|
| 12 |
|
|
<li><a href="#3.3%20Actel%20ProASIC3%20example"> 3.3 Actel ProASIC3 example</a></li>
|
| 13 |
50 |
olivier.gi |
</ul>
|
| 14 |
|
|
</li>
|
| 15 |
100 |
olivier.gi |
<li><a href="#4.%20Directory%20structure:%20Software%20Development%20Tools">4. Directory structure: Software Development Tools</a></li>
|
| 16 |
50 |
olivier.gi |
</ul>
|
| 17 |
|
|
|
| 18 |
|
|
<a name="1. Introduction"></a>
|
| 19 |
|
|
<h1>1. Introduction</h1>
|
| 20 |
|
|
|
| 21 |
|
|
To simplify the integration of this IP, the directory structure is based on the <a href="http://www.opencores.org/downloads/opencores_coding_guidelines.pdf">OpenCores</a> recommendations.
|
| 22 |
100 |
olivier.gi |
<br>
|
| 23 |
50 |
olivier.gi |
<a name="2. Directory structure: openMSP430 core"></a>
|
| 24 |
100 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 25 |
50 |
olivier.gi |
<h1>2. Directory structure: openMSP430 core</h1>
|
| 26 |
|
|
|
| 27 |
|
|
<table border="1">
|
| 28 |
100 |
olivier.gi |
<tbody><tr><td colspan="5"><b>core</b></td> <td><i><b>openMSP430 Core top level directory</b></i></td></tr>
|
| 29 |
69 |
olivier.gi |
<tr><td rowspan="80" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
| 30 |
100 |
olivier.gi |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br>
|
| 31 |
|
|
</td></tr>
|
| 32 |
|
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr>
|
| 33 |
50 |
olivier.gi |
<tr><td colspan="2">ram.v</td> <td><i>RAM verilog model</i></td></tr>
|
| 34 |
|
|
<tr><td colspan="2">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
| 35 |
|
|
<tr><td colspan="2">dbg_uart_tasks.v</td> <td><i>UART tasks for the serial debug interface</i></td></tr>
|
| 36 |
|
|
<tr><td colspan="2">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
| 37 |
|
|
<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
| 38 |
|
|
<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
|
| 39 |
|
|
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
| 40 |
100 |
olivier.gi |
<tr><td rowspan="22" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i><br>
|
| 41 |
|
|
</td></tr>
|
| 42 |
69 |
olivier.gi |
<tr><td rowspan="21" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration)</i></td></tr>
|
| 43 |
50 |
olivier.gi |
<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr>
|
| 44 |
|
|
<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
|
| 45 |
|
|
<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
|
| 46 |
|
|
<tr><td colspan="2">omsp_execution_unit.v</td> <td><i>Execution unit</i></td></tr>
|
| 47 |
|
|
<tr><td colspan="2">omsp_alu.v</td> <td><i>ALU</i></td></tr>
|
| 48 |
|
|
<tr><td colspan="2">omsp_register_file.v</td> <td><i>Register file</i></td></tr>
|
| 49 |
|
|
<tr><td colspan="2">omsp_mem_backbone.v</td> <td><i>Memory backbone</i></td></tr>
|
| 50 |
|
|
<tr><td colspan="2">omsp_clock_module.v</td> <td><i>Basic Clock Module</i></td></tr>
|
| 51 |
|
|
<tr><td colspan="2">omsp_sfr.v</td> <td><i>Special function registers</i></td></tr>
|
| 52 |
|
|
<tr><td colspan="2">omsp_watchdog.v</td> <td><i>Watchdog Timer</i></td></tr>
|
| 53 |
69 |
olivier.gi |
<tr><td colspan="2">omsp_multiplier.v</td> <td><i>16x16 Hardware Multiplier</i></td></tr>
|
| 54 |
50 |
olivier.gi |
<tr><td colspan="2">omsp_dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr>
|
| 55 |
|
|
<tr><td colspan="2">omsp_dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr>
|
| 56 |
|
|
<tr><td colspan="2">omsp_dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr>
|
| 57 |
|
|
<tr><td colspan="2">timescale.v</td> <td><i>Global time scale definition for simulation.</i></td></tr>
|
| 58 |
|
|
<tr><td colspan="2"><b>periph</b></td> <td><i><b>Peripherals directory</b></i></td></tr>
|
| 59 |
|
|
<tr><td rowspan="4"><font color="white">abcd</font></td> <td>omsp_gpio.v</td> <td><i>Digital I/O (Port 1 to 6)</i></td></tr>
|
| 60 |
|
|
<tr><td colspan="1">omsp_timerA.v</td> <td><i>Timer A</i></td></tr>
|
| 61 |
|
|
<tr><td colspan="1">template_periph_16b.v</td> <td><i>Verilog template for 16 bit peripherals</i></td></tr>
|
| 62 |
|
|
<tr><td colspan="1">template_periph_8b.v</td> <td><i>Verilog template for 8 bit peripherals</i></td></tr>
|
| 63 |
|
|
<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
| 64 |
69 |
olivier.gi |
<tr><td rowspan="36" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
| 65 |
|
|
<tr><td rowspan="35" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
|
| 66 |
100 |
olivier.gi |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">msp430sim</td> <td><i>Main simulation script</i></td></tr>
|
| 67 |
50 |
olivier.gi |
<tr><td colspan="1">asm2ihex.sh</td> <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr>
|
| 68 |
|
|
<tr><td colspan="1">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
|
| 69 |
|
|
<tr><td colspan="1">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
|
| 70 |
|
|
<tr><td colspan="1">template.def</td> <td><i>ASM linker definition file template</i></td></tr>
|
| 71 |
|
|
<tr><td colspan="2"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
|
| 72 |
100 |
olivier.gi |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">run</td> <td><i>Run single simulation of a given vector</i></td></tr>
|
| 73 |
50 |
olivier.gi |
<tr><td colspan="1">run_all</td> <td><i>Run regression of all vectors</i></td></tr>
|
| 74 |
|
|
<tr><td colspan="1">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
|
| 75 |
|
|
<tr><td colspan="1">load_waveform.sav</td> <td><i>SAV file for gtkWave</i></td></tr>
|
| 76 |
|
|
<tr><td colspan="2"><b>src</b></td> <td><i><b>RTL simulation vectors sources</b></i></td></tr>
|
| 77 |
69 |
olivier.gi |
<tr><td rowspan="23" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
|
| 78 |
50 |
olivier.gi |
<tr><td colspan="1">sing-op_*.s43</td> <td><i>Single-operand assembler vector files</i></td></tr>
|
| 79 |
|
|
<tr><td colspan="1">sing-op_*.v</td> <td><i>Single-operand verilog stimulus vector files</i></td></tr>
|
| 80 |
|
|
<tr><td colspan="1">two-op_*.s43</td> <td><i>Two-operand assembler vector files</i></td></tr>
|
| 81 |
|
|
<tr><td colspan="1">two-op_*.v</td> <td><i>Two-operand verilog stimulus vector files</i></td></tr>
|
| 82 |
|
|
<tr><td colspan="1">c-jump_*.s43</td> <td><i>Jump assembler vector files</i></td></tr>
|
| 83 |
|
|
<tr><td colspan="1">c-jump_*.v</td> <td><i>Jump verilog stimulus vector files</i></td></tr>
|
| 84 |
|
|
<tr><td colspan="1">op_modes.s43</td> <td><i>CPU operating modes assembler vector files (CPUOFF, OSCOFF, SCG1)</i></td></tr>
|
| 85 |
|
|
<tr><td colspan="1">op_modes.v</td> <td><i>CPU operating modes verilog stimulus vector files (CPUOFF, OSCOFF, SCG1)</i></td></tr>
|
| 86 |
|
|
<tr><td colspan="1">clock_module.s43</td> <td><i>Basic Clock Module assembler vector files</i></td></tr>
|
| 87 |
|
|
<tr><td colspan="1">clock_module.v</td> <td><i>Basic Clock Module verilog stimulus vector files</i></td></tr>
|
| 88 |
|
|
<tr><td colspan="1">dbg_*.s43</td> <td><i>Serial Debug Interface assembler vector files</i></td></tr>
|
| 89 |
|
|
<tr><td colspan="1">dbg_*.v</td> <td><i>Serial Debug Interface verilog stimulus vector files</i></td></tr>
|
| 90 |
|
|
<tr><td colspan="1">gpio_*.s43</td> <td><i>Digital I/O assembler vector files</i></td></tr>
|
| 91 |
|
|
<tr><td colspan="1">gpio_*.v</td> <td><i>Digital I/O verilog stimulus vector files</i></td></tr>
|
| 92 |
|
|
<tr><td colspan="1">template_periph_*.s43</td> <td><i>Peripheral templates assembler vector files</i></td></tr>
|
| 93 |
|
|
<tr><td colspan="1">template_periph_*.v</td> <td><i>Peripheral templates verilog stimulus vector files</i></td></tr>
|
| 94 |
|
|
<tr><td colspan="1">wdt_*.s43</td> <td><i>Watchdog timer assembler vector files</i></td></tr>
|
| 95 |
|
|
<tr><td colspan="1">wdt_*.v</td> <td><i>Watchdog timer verilog stimulus vector files</i></td></tr>
|
| 96 |
|
|
<tr><td colspan="1">tA_*.s43</td> <td><i>Timer A assembler vector files</i></td></tr>
|
| 97 |
|
|
<tr><td colspan="1">tA_*.v</td> <td><i>Timer A verilog stimulus vector files</i></td></tr>
|
| 98 |
69 |
olivier.gi |
<tr><td colspan="1">mpy_*.s43</td> <td><i>16x16 Multiplier assembler vector files</i></td></tr>
|
| 99 |
|
|
<tr><td colspan="1">mpy_*.v</td> <td><i>16x16 Multiplier verilog stimulus vector files</i></td></tr>
|
| 100 |
|
|
<tr><td colspan="4"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
| 101 |
|
|
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>synopsys</b></td><td><i>Synopsys (Design Compiler) directory</i></td></tr>
|
| 102 |
|
|
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run_syn</td> <td><i>Run synthesis</i></td></tr>
|
| 103 |
50 |
olivier.gi |
<tr><td colspan="2">synthesis.tcl</td> <td><i>Main synthesis TCL script</i></td></tr>
|
| 104 |
|
|
<tr><td colspan="2">library.tcl</td> <td><i>Load library, set operating conditions and wire load models</i></td></tr>
|
| 105 |
|
|
<tr><td colspan="2">read.tcl</td> <td><i>Read RTL</i></td></tr>
|
| 106 |
|
|
<tr><td colspan="2">constraints.tcl</td> <td><i>Set design constrains</i></td></tr>
|
| 107 |
69 |
olivier.gi |
<tr><td colspan="2"><b>results</b></td> <td><i>Results directory</i></td></tr>
|
| 108 |
100 |
olivier.gi |
<tr><td colspan="3"><b>actel</b></td> <td><i>Actel synthesis setup for area & speed analysis</i></td></tr>
|
| 109 |
|
|
<tr><td colspan="3"><b>altera</b></td> <td><i>Altera synthesis setup for area & speed analysis</i></td></tr>
|
| 110 |
|
|
<tr><td colspan="3"><b>xilinx</b></td> <td><i>Xilinx synthesis setup for area & speed analysis</i></td></tr>
|
| 111 |
|
|
</tbody></table>
|
| 112 |
|
|
<br>
|
| 113 |
50 |
olivier.gi |
<a name="3. Directory structure: FGPA projects"></a>
|
| 114 |
100 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 115 |
50 |
olivier.gi |
<h1>3. Directory structure: FGPA projects</h1>
|
| 116 |
|
|
|
| 117 |
|
|
<a name="3.1 Xilinx Spartan 3 example"></a>
|
| 118 |
|
|
<h2>3.1 Xilinx Spartan 3 example</h2>
|
| 119 |
|
|
|
| 120 |
|
|
<table border="1">
|
| 121 |
100 |
olivier.gi |
<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
| 122 |
50 |
olivier.gi |
<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr>
|
| 123 |
|
|
<tr><td rowspan="51" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
| 124 |
100 |
olivier.gi |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
| 125 |
|
|
</td></tr>
|
| 126 |
|
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
|
| 127 |
50 |
olivier.gi |
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
| 128 |
|
|
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
| 129 |
|
|
<tr><td colspan="3">glbl.v</td> <td><i>Xilinx "glbl.v" file</i></td></tr>
|
| 130 |
|
|
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
| 131 |
|
|
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">board_user_guide.pdf</td> <td><i>Spartan-3 FPGA Starter Kit Board User Guide</i></td></tr>
|
| 132 |
|
|
<tr><td colspan="4">msp430f1121a.pdf</td> <td><i>msp430f1121a Specification</i></td></tr>
|
| 133 |
|
|
<tr><td colspan="4">xapp462.pdf</td> <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr>
|
| 134 |
|
|
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
| 135 |
100 |
olivier.gi |
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
| 136 |
|
|
</td></tr>
|
| 137 |
50 |
olivier.gi |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
|
| 138 |
|
|
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
|
| 139 |
|
|
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
|
| 140 |
|
|
<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
|
| 141 |
|
|
<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr>
|
| 142 |
|
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">ram_8x512_hi.*</td> <td><i>512 Byte RAM (upper byte)</i></td></tr>
|
| 143 |
|
|
<tr><td colspan="2">ram_8x512_lo.*</td> <td><i>512 Byte RAM (lower byte)</i></td></tr>
|
| 144 |
|
|
<tr><td colspan="2">ram_8x2k_hi.*</td> <td><i>2 kByte RAM (upper byte)</i></td></tr>
|
| 145 |
|
|
<tr><td colspan="2">ram_8x2k_lo.*</td> <td><i>2 kByte RAM (lower byte)</i></td></tr>
|
| 146 |
|
|
<tr><td colspan="5"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
| 147 |
|
|
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
| 148 |
|
|
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
|
| 149 |
100 |
olivier.gi |
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td> <td><i>Main simulation script</i></td></tr>
|
| 150 |
50 |
olivier.gi |
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
|
| 151 |
|
|
<tr><td colspan="2">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
|
| 152 |
|
|
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
|
| 153 |
|
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td> <td><i>Run simulation of a given software project</i></td></tr>
|
| 154 |
|
|
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
|
| 155 |
|
|
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
| 156 |
|
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
|
| 157 |
|
|
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
| 158 |
|
|
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
| 159 |
|
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
|
| 160 |
100 |
olivier.gi |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td> <td><i></i><br>
|
| 161 |
|
|
</td></tr>
|
| 162 |
|
|
<tr><td colspan="3">hardware.h</td> <td><i></i><br>
|
| 163 |
|
|
</td></tr>
|
| 164 |
|
|
<tr><td colspan="3">main.c</td> <td><i></i><br>
|
| 165 |
|
|
</td></tr>
|
| 166 |
|
|
<tr><td colspan="3">7seg.h</td> <td><i></i><br>
|
| 167 |
|
|
</td></tr>
|
| 168 |
|
|
<tr><td colspan="3">7seg.c</td> <td><i></i><br>
|
| 169 |
|
|
</td></tr>
|
| 170 |
50 |
olivier.gi |
<tr><td colspan="4"><b>ta_uart</b></td> <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr>
|
| 171 |
|
|
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
| 172 |
100 |
olivier.gi |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><i></i><br>
|
| 173 |
|
|
</td></tr>
|
| 174 |
50 |
olivier.gi |
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream.sh</td> <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr>
|
| 175 |
|
|
<tr><td colspan="3">create_bitstream.bat</td> <td><i>Run Xilinx ISE synthesis in a Windows environment</i></td></tr>
|
| 176 |
|
|
<tr><td colspan="3">openMSP430_fpga.ucf</td> <td><i>UCF file</i></td></tr>
|
| 177 |
|
|
<tr><td colspan="3">openMSP430_fpga.prj</td> <td><i>RTL file list to be synthesized</i></td></tr>
|
| 178 |
|
|
<tr><td colspan="3">xst_verilog.opt</td> <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr>
|
| 179 |
|
|
<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's program memory with a given software ELF file in a Linux environment</i></td></tr>
|
| 180 |
|
|
<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's program memory with a given software ELF file in a Windows environment</i></td></tr>
|
| 181 |
|
|
<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's program memory update</i></td></tr>
|
| 182 |
100 |
olivier.gi |
</tbody></table>
|
| 183 |
|
|
<br>
|
| 184 |
50 |
olivier.gi |
|
| 185 |
|
|
<a name="3.2 Altera Cyclone II example"></a>
|
| 186 |
100 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 187 |
50 |
olivier.gi |
<h2>3.2 Altera Cyclone II example</h2>
|
| 188 |
|
|
|
| 189 |
|
|
|
| 190 |
|
|
<table border="1">
|
| 191 |
100 |
olivier.gi |
<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
| 192 |
50 |
olivier.gi |
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr>
|
| 193 |
|
|
<tr><td rowspan="48" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td> <td><i>README file</i></td></tr>
|
| 194 |
|
|
<tr><td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
| 195 |
100 |
olivier.gi |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
| 196 |
|
|
</td></tr>
|
| 197 |
|
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
|
| 198 |
50 |
olivier.gi |
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
| 199 |
|
|
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
| 200 |
|
|
<tr><td colspan="3">altsyncram.v</td> <td><i>Altera verilog model of the altsyncram module.</i></td></tr>
|
| 201 |
|
|
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
| 202 |
|
|
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">DE1_Board_Schematic.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Schematics</i></td></tr>
|
| 203 |
|
|
<tr><td colspan="4">DE1_Reference_Manual.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Reference Manual</i></td></tr>
|
| 204 |
|
|
<tr><td colspan="4">DE1_User_Guide.pdf</td> <td><i>Cyclone II FPGA Starter Development Board User Guide</i></td></tr>
|
| 205 |
|
|
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
| 206 |
100 |
olivier.gi |
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
| 207 |
|
|
</td></tr>
|
| 208 |
50 |
olivier.gi |
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">OpenMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
|
| 209 |
|
|
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
|
| 210 |
|
|
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
|
| 211 |
|
|
<tr><td colspan="3">ext_de1_sram.v</td> <td><i>Interface with altera DE1's external async SRAM (256kwords x 16bits)</i></td></tr>
|
| 212 |
|
|
<tr><td colspan="3">ram16x512.v</td> <td><i>Single port RAM generated with the megafunction wizard</i></td></tr>
|
| 213 |
|
|
<tr><td colspan="3">rom16x2048.v</td> <td><i>Single port ROM generated with the megafunction wizard</i></td></tr>
|
| 214 |
|
|
<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
|
| 215 |
|
|
<tr><td colspan="5"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
| 216 |
|
|
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
| 217 |
|
|
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
|
| 218 |
100 |
olivier.gi |
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td> <td><i>Main simulation script</i></td></tr>
|
| 219 |
50 |
olivier.gi |
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
|
| 220 |
|
|
<tr><td colspan="2">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
|
| 221 |
|
|
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
|
| 222 |
|
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td> <td><i>Run simulation of a given software project</i></td></tr>
|
| 223 |
|
|
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
|
| 224 |
|
|
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
| 225 |
|
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
|
| 226 |
|
|
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
| 227 |
|
|
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
| 228 |
|
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>bin</b></td> <td><i>Specific binaries required for software development.</i></td></tr>
|
| 229 |
100 |
olivier.gi |
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">mifwrite.cpp</td> <td><i>This
|
| 230 |
|
|
prog is taken from
|
| 231 |
|
|
http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly
|
| 232 |
|
|
changed to satisfy quartus6.1 *.mif eating engine.</i></td></tr>
|
| 233 |
50 |
olivier.gi |
<tr><td colspan="3">mifwrite.exe</td> <td><i>Windows executable.</i></td></tr>
|
| 234 |
|
|
<tr><td colspan="3">mifwrite</td> <td><i>Linux executable.</i></td></tr>
|
| 235 |
|
|
<tr><td colspan="4"><b>memledtest</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
|
| 236 |
|
|
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
| 237 |
100 |
olivier.gi |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>altera</b></td> <td><i></i><br>
|
| 238 |
|
|
</td></tr>
|
| 239 |
50 |
olivier.gi |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">main.qsf</td> <td><i>Global Assignments file</i></td></tr>
|
| 240 |
|
|
<tr><td colspan="3">main.sof</td> <td><i>SOF file</i></td></tr>
|
| 241 |
|
|
<tr><td colspan="3">OpenMSP430_fpga.qpf</td> <td><i>Quartus II project file</i></td></tr>
|
| 242 |
|
|
<tr><td colspan="3">openMSP430_fpga_top.v</td> <td><i>RTL file list to be synthesized</i></td></tr>
|
| 243 |
100 |
olivier.gi |
</tbody></table>
|
| 244 |
|
|
<br>
|
| 245 |
|
|
|
| 246 |
|
|
<a name="3.3 Actel ProASIC3 example"></a>
|
| 247 |
|
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 248 |
|
|
<h2>3.3 Actel ProASIC3 example</h2>
|
| 249 |
|
|
|
| 250 |
|
|
<table border="1">
|
| 251 |
|
|
<tbody><tr><td colspan="6"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
| 252 |
|
|
<tr><td rowspan="43" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>actel_m1a3pl_dev_kit</b></td> <td><i><b>Actel FPGA Project based on the ProASIC3 M1A3PL development kit<br>
|
| 253 |
|
|
</b></i></td></tr>
|
| 254 |
|
|
|
| 255 |
|
|
<tr><td rowspan="42" style="vertical-align: top;"><font color="white">abcd</font></td>
|
| 256 |
|
|
<td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
| 257 |
|
|
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br>
|
| 258 |
|
|
</td></tr>
|
| 259 |
|
|
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">tb_openMSP430_fpga.v</td>
|
| 260 |
|
|
<td><i>FPGA testbench top level module</i></td></tr>
|
| 261 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">registers.v</td>
|
| 262 |
|
|
<td><i>Connections to Core internals for easy debugging</i></td></tr>
|
| 263 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td>
|
| 264 |
|
|
<td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
| 265 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">proasic3l.v</td>
|
| 266 |
|
|
<td><i>Actel ProASIC3L library file.<br>
|
| 267 |
|
|
</i></td></tr>
|
| 268 |
|
|
<tr>
|
| 269 |
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">DAC121S101.v<br>
|
| 270 |
|
|
</td>
|
| 271 |
|
|
<td style="vertical-align: top;"><i>Verilog model of National's DAC121S101 12 bit DAC.</i></td>
|
| 272 |
|
|
</tr>
|
| 273 |
|
|
<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
| 274 |
|
|
<tr><td rowspan="2"><font color="white">abcd</font></td> <td colspan="3">M1A3PL_DEV_KIT_QS.pdf</td> <td><i>Development Kit Quickstart Card.</i></td></tr>
|
| 275 |
|
|
<tr><td colspan="3">M1IGLOO_StarterKit_v1_5_UG.pdf</td> <td><i>Development Kit User's Guide.</i></td></tr>
|
| 276 |
|
|
|
| 277 |
|
|
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
| 278 |
|
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><br>
|
| 279 |
|
|
</td></tr>
|
| 280 |
|
|
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">openMSP430_fpga.v</td>
|
| 281 |
|
|
<td><i>FPGA top level file</i></td></tr>
|
| 282 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">dac_spi_if.v</td>
|
| 283 |
|
|
<td><i>SPI interface to National's DAC121S101 12 bit DAC.<br>
|
| 284 |
|
|
</i></td></tr>
|
| 285 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">smartgen</span><br>
|
| 286 |
|
|
</td>
|
| 287 |
|
|
<td><i>Actel's smartgen directory.</i></td></tr>
|
| 288 |
|
|
|
| 289 |
|
|
<tr><td style="vertical-align: top;"><font color="white">abcd</font></td>
|
| 290 |
|
|
<td colspan="1">dmem_128B.v</td> <td><i>128 Byte RAM (for data memory).<br>
|
| 291 |
|
|
</i></td></tr>
|
| 292 |
|
|
<tr><td style="vertical-align: top;"><br>
|
| 293 |
|
|
</td>
|
| 294 |
|
|
<td colspan="1">pmem_2kB.v</td> <td><i>2 kByte RAM (for program memory).<br>
|
| 295 |
|
|
</i></td></tr>
|
| 296 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>openmsp430</b></td>
|
| 297 |
|
|
<td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
|
| 298 |
|
|
<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
| 299 |
|
|
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
<tr> <td rowspan="10" style="vertical-align: top;"><br>
|
| 304 |
|
|
</td>
|
| 305 |
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">bin</span><br>
|
| 306 |
|
|
</td>
|
| 307 |
|
|
<td style="font-style: italic;"><span style="font-weight: bold;">RTL simulation scripts</span><br>
|
| 308 |
|
|
</td></tr>
|
| 309 |
|
|
<tr>
|
| 310 |
|
|
<td colspan="1" rowspan="3" style="vertical-align: top;"><br>
|
| 311 |
|
|
</td>
|
| 312 |
|
|
<td style="vertical-align: top;">msp430sim<br>
|
| 313 |
|
|
</td>
|
| 314 |
|
|
<td style="vertical-align: top;">Main simulation script<br>
|
| 315 |
|
|
</td>
|
| 316 |
|
|
</tr>
|
| 317 |
|
|
<tr>
|
| 318 |
|
|
<td style="vertical-align: top;">ihex2mem.tcl<br>
|
| 319 |
|
|
</td>
|
| 320 |
|
|
<td style="vertical-align: top;">Verilog program memory file generation<br>
|
| 321 |
|
|
</td>
|
| 322 |
|
|
</tr>
|
| 323 |
|
|
<tr>
|
| 324 |
|
|
<td style="vertical-align: top;">rtlsim.sh<br>
|
| 325 |
|
|
</td>
|
| 326 |
|
|
<td style="vertical-align: top;">Verilog Icarus simulation script<br>
|
| 327 |
|
|
</td>
|
| 328 |
|
|
</tr>
|
| 329 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>run</b></td>
|
| 330 |
|
|
<td><i><b>For running RTL simulations</b></i></td></tr>
|
| 331 |
|
|
|
| 332 |
|
|
<tr> <td colspan="1" rowspan="2" style="vertical-align: top;"><br>
|
| 333 |
|
|
</td>
|
| 334 |
|
|
<td style="vertical-align: top;">run<br>
|
| 335 |
|
|
</td>
|
| 336 |
|
|
<td><i>Run simulation of a given software project<br>
|
| 337 |
|
|
</i></td></tr>
|
| 338 |
|
|
<tr>
|
| 339 |
|
|
<td style="vertical-align: top;">run_disassemble<br>
|
| 340 |
|
|
</td>
|
| 341 |
|
|
<td style="vertical-align: top;"><i>Disassemble the program memory content of the latest simulation</i></td>
|
| 342 |
|
|
</tr>
|
| 343 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>src</b></td>
|
| 344 |
|
|
<td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
| 345 |
|
|
|
| 346 |
|
|
<tr>
|
| 347 |
|
|
<td colspan="1" rowspan="2" style="vertical-align: top;"><br>
|
| 348 |
|
|
</td>
|
| 349 |
|
|
<td style="vertical-align: top;">submit.f<br>
|
| 350 |
|
|
</td>
|
| 351 |
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">Verilog simulator command file</span><br>
|
| 352 |
|
|
</td>
|
| 353 |
|
|
</tr>
|
| 354 |
|
|
<tr> <td style="vertical-align: top;">*.v<br>
|
| 355 |
|
|
</td>
|
| 356 |
|
|
<td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
| 357 |
|
|
<tr><td colspan="4"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
| 358 |
|
|
|
| 359 |
|
|
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
<tr><td colspan="1" rowspan="2" style="vertical-align: top;"><br>
|
| 363 |
|
|
</td>
|
| 364 |
|
|
<td colspan="3"><span style="font-weight: bold;">spacewar</span><br>
|
| 365 |
|
|
</td> <td><span style="font-style: italic;">SpaceWar oscilloscope game.</span><br>
|
| 366 |
|
|
</td></tr>
|
| 367 |
|
|
<tr>
|
| 368 |
|
|
<td style="vertical-align: top;"><br>
|
| 369 |
|
|
</td>
|
| 370 |
|
|
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><img src="usercontent,img,1299013492" alt="Spacewar" title="Spacewar" width="25%"/><br>
|
| 371 |
|
|
</td>
|
| 372 |
|
|
</tr>
|
| 373 |
|
|
<tr><td colspan="4"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
| 374 |
|
|
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>actel</b></td> <td><br>
|
| 375 |
|
|
</td></tr>
|
| 376 |
|
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">prepare_implementation.tcl<br>
|
| 377 |
|
|
</td>
|
| 378 |
|
|
<td style="font-style: italic;">Generate required files prior synthesis and P&R.<br>
|
| 379 |
|
|
</td></tr>
|
| 380 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">synplify.tcl<br>
|
| 381 |
|
|
</td>
|
| 382 |
|
|
<td style="font-style: italic;">Synplify template for the synthesis run.<br>
|
| 383 |
|
|
</td></tr>
|
| 384 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">libero_designer.tcl<br>
|
| 385 |
|
|
</td>
|
| 386 |
|
|
<td style="font-style: italic;">Libero Designer template for the P&R run.<br>
|
| 387 |
|
|
</td></tr>
|
| 388 |
|
|
<tr>
|
| 389 |
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">design_files.v<br>
|
| 390 |
|
|
</td>
|
| 391 |
|
|
<td style="vertical-align: top; font-style: italic;">RTL file list to be synthesized.<br>
|
| 392 |
|
|
</td>
|
| 393 |
|
|
</tr>
|
| 394 |
|
|
<tr>
|
| 395 |
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.pre.sdc<br>
|
| 396 |
|
|
</td>
|
| 397 |
|
|
<td style="vertical-align: top; font-style: italic;">Synthesis timing constraints.<br>
|
| 398 |
|
|
</td>
|
| 399 |
|
|
</tr>
|
| 400 |
|
|
<tr>
|
| 401 |
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.post.sdc<br>
|
| 402 |
|
|
</td>
|
| 403 |
|
|
<td style="vertical-align: top; font-style: italic;">P&R timing constraints.<br>
|
| 404 |
|
|
</td>
|
| 405 |
|
|
</tr>
|
| 406 |
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.pdc<br>
|
| 407 |
|
|
</td>
|
| 408 |
|
|
<td style="font-style: italic;">P&R physical constraints.<br>
|
| 409 |
|
|
</td></tr>
|
| 410 |
|
|
</tbody></table>
|
| 411 |
|
|
|
| 412 |
|
|
<br>
|
| 413 |
50 |
olivier.gi |
<a name="4. Directory structure: Software Development Tools"></a>
|
| 414 |
100 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 415 |
50 |
olivier.gi |
<h1>4. Directory structure: Software Development Tools</h1>
|
| 416 |
|
|
|
| 417 |
|
|
<table border="1">
|
| 418 |
100 |
olivier.gi |
<tbody><tr><td colspan="5"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr>
|
| 419 |
50 |
olivier.gi |
<tr><td rowspan="72" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bin</b></td> <td><i><b>Contains the executable files</b></i></td></tr>
|
| 420 |
100 |
olivier.gi |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openmsp430-loader.tcl</td> <td><i>Simple command line boot loader: TCL Script</i></td></tr>
|
| 421 |
50 |
olivier.gi |
<tr><td colspan="3">openmsp430-loader.exe</td> <td><i>Simple command line boot loader: Windows executable</i></td></tr>
|
| 422 |
|
|
<tr><td colspan="3">openmsp430-minidebug.tcl</td> <td><i>Minimalistic debugger with simple GUI: TCL Script</i></td></tr>
|
| 423 |
|
|
<tr><td colspan="3">openmsp430-minidebug.exe</td> <td><i>Minimalistic debugger with simple GUI: Windows executable</i></td></tr>
|
| 424 |
|
|
<tr><td colspan="3">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends: TCL Script</i></td></tr>
|
| 425 |
|
|
<tr><td colspan="3">openmsp430-gdbproxy.exe</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends: Windows executable</i></td></tr>
|
| 426 |
|
|
<tr><td colspan="4"><b>lib</b></td> <td><i><b>Common library</b></i></td></tr>
|
| 427 |
|
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>tcl-lib</b></td> <td><i><b>Common TCL library</b></i></td></tr>
|
| 428 |
|
|
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">dbg_uart.tcl</td> <td><i>Low level UART communication functions</i></td></tr>
|
| 429 |
|
|
<tr><td colspan="2">dbg_functions.tcl</td> <td><i>Main utility functions for the openMSP430 serial debug interface</i></td></tr>
|
| 430 |
|
|
<tr><td colspan="2">combobox.tcl</td> <td><i>A combobox listbox widget written in pure tcl (from Bryan Oakley)</i></td></tr>
|
| 431 |
|
|
<tr><td colspan="4"><b>openmsp430-gdbproxy</b></td> <td><i><b>GDB Proxy server main project directory</b></i></td></tr>
|
| 432 |
|
|
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server main TCL Script (symbolic link with the script in the <b>bin</b> directory)</i></td></tr>
|
| 433 |
|
|
<tr><td colspan="3">server.tcl</td> <td><i>TCP/IP Server utility functions. Send/Receive RSP packets from GDB.</i></td></tr>
|
| 434 |
|
|
<tr><td colspan="3">commands.tcl</td> <td><i>RSP command execution functions.</i></td></tr>
|
| 435 |
|
|
<tr><td colspan="3"><b>doc</b></td> <td><i><b>Some documentation regarding GDB and the RSP protocol.</b></i></td></tr>
|
| 436 |
|
|
<tr><td rowspan="2"><font color="white">abcd</font></td> <td colspan="2">ew_GDB_RSP.pdf</td> <td><i>Document from Bill Gatliff: Embedding with GNU: the gdb Remote Serial Protocol</i></td></tr>
|
| 437 |
|
|
<tr><td colspan="2">Howto-GDB_Remote_Serial_Protocol.pdf</td> <td><i>Document from Jeremy Bennett (Embecosm): Howto: GDB Remote Serial Protocol - Writing a RSP Server</i></td></tr>
|
| 438 |
|
|
<tr><td colspan="4"><b>freewrap642</b></td> <td><i><b>The freeWrap program turns TCL/TK scripts into single-file binary executable programs for Windows.</b></i></td></tr>
|
| 439 |
100 |
olivier.gi |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">freewrap.exe</td> <td><i>freeWrap executable to run on TCL/TK scripts (i.e. with GUI)</i></td></tr>
|
| 440 |
50 |
olivier.gi |
<tr><td colspan="3">freewrapTCLSH.exe</td> <td><i>freeWrap executable to run on pure TCL scripts (i.e. command line)</i></td></tr>
|
| 441 |
|
|
<tr><td colspan="3">tclpip85s.dll</td> <td><i>freeWrap mandatory DLL</i></td></tr>
|
| 442 |
|
|
<tr><td colspan="3">generate_exec.bat</td> <td><i>Simple Batch file for auto generation of the tools' windows executables</i></td></tr>
|
| 443 |
100 |
olivier.gi |
</tbody></table>
|
| 444 |
|
|
<br>
|
| 445 |
|
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 446 |
50 |
olivier.gi |
|
| 447 |
100 |
olivier.gi |
</body></html>
|
