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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 File &amp; Directory description</title></head><body>
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<a name="TOC"></a>
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<h3>Table of content</h3>
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<ul>
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        <li><a href="#1.%20Introduction">                                   1. Introduction</a></li>
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        <li><a href="#2.%20Directory%20structure:%20openMSP430%20core">           2. Directory structure: openMSP430 core</a></li>
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   <li><a href="#3.%20Directory%20structure:%20FGPA%20projects">             3. Directory structure: FGPA projects</a>
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        <ul>
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      <li><a href="#3.1%20Xilinx%20Spartan%203%20example">                       3.1 Xilinx Spartan 3 example</a></li>
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      <li><a href="#3.2%20Altera%20Cyclone%20II%20example">                      3.2 Altera Cyclone II example</a></li>
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      <li><a href="#3.3%20Actel%20ProASIC3%20example">                         3.3 Actel ProASIC3 example</a></li>
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        </ul>
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        </li>
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        <li><a href="#4.%20Directory%20structure:%20Software%20Development%20Tools">4. Directory structure: Software Development Tools</a></li>
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</ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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To simplify the integration of this IP, the directory structure is based on the <a href="http://cdn.opencores.org/downloads/opencores_coding_guidelines.pdf">OpenCores</a> recommendations.
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<br>
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<a name="2. Directory structure: openMSP430 core"></a>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>2. Directory structure: openMSP430 core</h1>
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<table border="1">
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        <tbody><tr><td colspan="5"><b>core</b></td>                                                                           <td><i><b>openMSP430 Core top level directory</b></i></td></tr>
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        <tr><td rowspan="107" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td>    <td><i><b>Top level testbench directory</b></i></td></tr>
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        <tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td>  <td><i></i><br>
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</td></tr>
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        <tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr>
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        <tr><td colspan="2">ram.v</td>                                                                                 <td><i>RAM verilog model</i></td></tr>
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        <tr><td colspan="2">registers.v</td>                                                                           <td><i>Connections to Core internals for easy debugging</i></td></tr>
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        <tr><td colspan="2">dbg_uart_tasks.v</td>                                                                      <td><i>UART tasks for the serial debug interface</i></td></tr>
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        <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td>
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      <td style="vertical-align: top;"><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td>
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    </tr>
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<tr><td colspan="2">timescale.v</td>                                                                           <td><i>Global time scale definition for simulation.</i></td></tr>
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        <tr><td colspan="4"><b>doc</b></td>                                                                            <td><i><b>Diverse documentation</b></i></td></tr>
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        <tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td>                                 <td><i>MSP430x1xx Family User's Guide</i></td></tr>
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        <tr><td colspan="4"><b>rtl</b></td>                                                                            <td><i><b>RTL sources</b></i></td></tr>
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        <tr><td rowspan="30" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td>   <td><i></i><br>
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</td></tr>
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        <tr><td rowspan="29" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td>  <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration, ...)</i></td></tr>
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        <tr><td colspan="2">openMSP430_undefines.v</td>                                                                <td><i>openMSP430 Verilog `undef file</i></td></tr>
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        <tr><td colspan="2">openMSP430.v</td>                                                                          <td><i>openMSP430 top level</i></td></tr>
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        <tr><td colspan="2">omsp_frontend.v</td>                                                                       <td><i>Instruction fetch and decode</i></td></tr>
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        <tr><td colspan="2">omsp_execution_unit.v</td>                                                                 <td><i>Execution unit</i></td></tr>
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        <tr><td colspan="2">omsp_alu.v</td>                                                                            <td><i>ALU</i></td></tr>
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        <tr><td colspan="2">omsp_register_file.v</td>                                                                  <td><i>Register file</i></td></tr>
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        <tr><td colspan="2">omsp_mem_backbone.v</td>                                                                   <td><i>Memory backbone</i></td></tr>
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        <tr><td colspan="2">omsp_clock_module.v</td>                                                                   <td><i>Basic Clock Module</i></td></tr>
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        <tr><td colspan="2">omsp_sfr.v</td>                                                                            <td><i>Special function registers</i></td></tr>
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        <tr><td colspan="2">omsp_watchdog.v</td>                                                                       <td><i>Watchdog Timer</i></td></tr>
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        <tr><td colspan="2">omsp_multiplier.v</td>                                                                     <td><i>16x16 Hardware Multiplier</i></td></tr>
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        <tr><td colspan="2">omsp_dbg.v</td>                                                                            <td><i>Serial Debug Interface main block</i></td></tr>
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        <tr><td colspan="2">omsp_dbg_hwbrk.v</td>                                                                      <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr>
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        <tr><td colspan="2">omsp_dbg_uart.v</td>                                                                       <td><i>Serial Debug Interface UART communication block</i></td></tr>
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        <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_sync_cell.v</td>
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      <td style="vertical-align: top;"><i>Simple synchronization module (double flip-flop).</i></td>
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    </tr>
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    <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_sync_reset.v</td>
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      <td style="vertical-align: top;"><i>Generic Reset synchronizer (double flip-flop).</i></td>
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    </tr>
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    <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_clock_gate.v</td>
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      <td style="vertical-align: top;"><i>Generic Clock gate (NAND2 or LATCH-AND based).</i></td>
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    </tr>
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    <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_clock_mux.v</td>
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      <td style="vertical-align: top;"><i>Standard Clock Mux (used in the clock module &amp; watchdog timer).<br>
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      </i></td>
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    </tr>
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    <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_and_gate.v</td>
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      <td style="vertical-align: top;"><i>AND gate module used on sensitive glitch free data paths.<br>
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      </i></td>
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    </tr>
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    <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_wakeup_cell.v</td>
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      <td style="vertical-align: top;"><i>Generic Wake-up module.<br>
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      </i></td>
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    </tr>
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    <tr>
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      <td colspan="2" rowspan="1" style="vertical-align: top;">omsp_scan_mux.v</td>
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      <td style="vertical-align: top;"><i>Scan MUX.<br>
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      </i></td>
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    </tr>
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        <tr><td colspan="2"><b>periph</b></td>                                                                         <td><i><b>Peripherals directory</b></i></td></tr>
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        <tr><td rowspan="6"><font color="white">abcd</font></td> <td>omsp_gpio.v</td>                                  <td><i>Digital I/O (Port 1 to 6)</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">omsp_timerA_defines.v<br>
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      </td>
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      <td style="vertical-align: top;"><i>Timer A configuration file</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">omsp_timerA_undefines.v<br>
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      </td>
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      <td style="vertical-align: top;"><i>Timer A Verilog `undef file</i></td>
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    </tr>
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<tr><td colspan="1">omsp_timerA.v</td>                                                                         <td><i>Timer A</i></td></tr>
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        <tr><td colspan="1">template_periph_16b.v</td>                                                                 <td><i>Verilog template for 16 bit peripherals</i></td></tr>
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        <tr><td colspan="1">template_periph_8b.v</td>                                                                  <td><i>Verilog template for 8 bit peripherals</i></td></tr>
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        <tr><td colspan="4"><b>sim</b></td>                                                                            <td><i><b>Top level simulations directory</b></i></td></tr>
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        <tr><td rowspan="54" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>rtl_sim</b></td>  <td><i><b>RTL simulations</b></i></td></tr>
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        <tr><td rowspan="53" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td>      <td><i><b>RTL simulation scripts</b></i></td></tr>
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        <tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">msp430sim</td>       <td><i>Main simulation script for assembler vector sources (located in the <span style="font-weight: bold;">src</span> directory)<br>
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</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">msp430sim_c<br>
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      </td>
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      <td style="vertical-align: top;"><i>Main simulation script for C vector sources</i><i> (located in the <span style="font-weight: bold;">src-c</span> directory)</i></td>
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    </tr>
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<tr><td colspan="1">asm2ihex.sh</td>                                                                           <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr>
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        <tr><td colspan="1">ihex2mem.tcl</td>                                                                          <td><i>Verilog program memory file generation</i></td></tr>
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        <tr><td colspan="1">rtlsim.sh</td>                                                                             <td><i>Verilog Icarus simulation script</i></td></tr>
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        <tr><td colspan="1">template.x</td>                                                                          <td><i>ASM linker definition file template</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;"><br>
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      </td>
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      <td style="vertical-align: top;">cov_*<br>
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      </td>
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      <td style="vertical-align: top;"><span style="font-style: italic;">Code coverage scripts for NC-Verilog and ICM</span><br>
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      </td>
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    </tr>
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<tr><td colspan="2"><b>run</b></td>                                                                            <td><i><b>For running RTL simulations</b></i></td></tr>
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        <tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">run</td>             <td><i>Run single simulation of a given assembler vector</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">run_c<br>
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      </td>
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      <td style="vertical-align: top;"><i>Run single simulation of a given C vector</i></td>
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    </tr>
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<tr><td colspan="1">run_all</td>                                                                               <td><i>Run regression of all vectors</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">run_all_mpy<br>
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      </td>
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      <td style="vertical-align: top;"><span style="font-style: italic;">Run regression of all hardware multiplier vectors (!!! very long simulation time !!!)</span><br>
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      </td>
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    </tr>
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<tr><td colspan="1">run_disassemble</td>                                                                       <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">run_coverage_analysis<br>
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      </td>
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      <td style="vertical-align: top; font-style: italic;">Performs the coverage report merging of the regression run and starts ICM for the analysis.<br>
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      </td>
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    </tr>
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<tr><td colspan="1">load_waveform.sav</td>                                                                     <td><i>SAV file for gtkWave</i></td></tr>
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        <tr><td colspan="2"><b>src</b></td>                                                                            <td><i><b>RTL simulation vectors sources</b></i></td></tr>
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        <tr><td rowspan="36" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">ldscript_example.x<br>
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</td>        <td><i>MSPGCC toolchain linker script example</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">submit.prj<br>
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      </td>
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      <td style="vertical-align: top;"><span style="font-style: italic;">ISIM simulator verilog command file</span><br>
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      </td>
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    </tr>
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<tr>
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      <td style="vertical-align: top;">submit.f</td>
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      <td style="vertical-align: top;"><i>Verilog simulator command file</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">core.f<br>
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      </td>
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      <td style="vertical-align: top;"><span style="font-style: italic;">Command file listing the CPU files only.</span><br>
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      </td>
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    </tr>
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<tr><td colspan="1">sing-op_*.s43</td>                                                                         <td><i>Single-operand assembler vector files</i></td></tr>
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        <tr><td colspan="1">sing-op_*.v</td>                                                                           <td><i>Single-operand verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="1">two-op_*.s43</td>                                                                          <td><i>Two-operand assembler vector files</i></td></tr>
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        <tr><td colspan="1">two-op_*.v</td>                                                                            <td><i>Two-operand verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="1">c-jump_*.s43</td>                                                                          <td><i>Jump assembler vector files</i></td></tr>
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        <tr><td colspan="1">c-jump_*.v</td>                                                                            <td><i>Jump verilog stimulus vector files</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">nmi.s43</td>
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      <td style="vertical-align: top;"><i>NMI assembler vector files</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">nmi.v</td>
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      <td style="vertical-align: top;"><i>NMI verilog stimulus vector files</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">cpu_startup_asic.s43</td>
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      <td style="vertical-align: top;"><i>CPU startup assembler vector files</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">cpu_startup_asic.v</td>
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      <td style="vertical-align: top;"><i>CPU startup stimulus vector files</i></td>
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    </tr>
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<tr><td colspan="1">op_modes*.s43</td>                                                                          <td><i>CPU operating modes assembler vector files (CPUOFF, OSCOFF, SCG1)</i></td></tr>
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        <tr><td colspan="1">op_modes*.v</td>                                                                            <td><i>CPU operating modes verilog stimulus vector files (CPUOFF, OSCOFF, SCG1)</i></td></tr>
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        <tr><td colspan="1">clock_module*.s43</td>                                                                      <td><i>Basic Clock Module assembler vector files</i></td></tr>
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        <tr><td colspan="1">clock_module*.v</td>                                                                        <td><i>Basic Clock Module verilog stimulus vector files</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">lp_modes_*.s43</td>
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      <td style="vertical-align: top;"><i>Low Power modes assembler vector files</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">lp_modes_*.v</td>
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      <td style="vertical-align: top;"><i>Low Power modes verilog stimulus vector files</i></td>
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    </tr>
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<tr><td colspan="1">dbg_*.s43</td>                                                                             <td><i>Serial Debug Interface assembler vector files</i></td></tr>
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        <tr><td colspan="1">dbg_*.v</td>                                                                               <td><i>Serial Debug Interface verilog stimulus vector files</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">sfr.s43</td>
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      <td style="vertical-align: top;"><i>SFR assembler vector files</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">sfr.v</td>
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      <td style="vertical-align: top;"><i>SFR verilog stimulus vector files</i></td>
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    </tr>
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<tr><td colspan="1">gpio_*.s43</td>                                                                            <td><i>Digital I/O assembler vector files</i></td></tr>
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        <tr><td colspan="1">gpio_*.v</td>                                                                              <td><i>Digital I/O verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="1">template_periph_*.s43</td>                                                                 <td><i>Peripheral templates assembler vector files</i></td></tr>
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        <tr><td colspan="1">template_periph_*.v</td>                                                                   <td><i>Peripheral templates verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="1">wdt_*.s43</td>                                                                             <td><i>Watchdog timer assembler vector files</i></td></tr>
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        <tr><td colspan="1">wdt_*.v</td>                                                                               <td><i>Watchdog timer verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="1">tA_*.s43</td>                                                                              <td><i>Timer A assembler vector files</i></td></tr>
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        <tr><td colspan="1">tA_*.v</td>                                                                                <td><i>Timer A verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="1">mpy_*.s43</td>                                                                             <td><i>16x16 Multiplier assembler vector files</i></td></tr>
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        <tr>
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      <td style="vertical-align: top;">mpy_*.v</td>
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      <td style="vertical-align: top;"><i>16x16 Multiplier verilog stimulus vector files</i></td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">scan.s43</td>
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      <td style="vertical-align: top;"><i>Scan test assembler vector files</i></td>
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    </tr>
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<tr><td colspan="1">scan.v</td>                                                                               <td><i>Scan test verilog stimulus vector files</i></td></tr>
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        <tr><td colspan="4"><b>synthesis</b></td>                                                                     <td><i><b>Top level synthesis directory</b></i></td></tr>
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        <tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>synopsys</b></td><td><i>Synopsys (Design Compiler) directory</i></td></tr>
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        <tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run_syn</td>        <td><i>Run synthesis</i></td></tr>
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        <tr><td colspan="2">synthesis.tcl</td>                                                                         <td><i>Main synthesis TCL script</i></td></tr>
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        <tr><td colspan="2">library.tcl</td>                                                                           <td><i>Load library, set operating conditions and wire load models</i></td></tr>
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        <tr><td colspan="2">read.tcl</td>                                                                              <td><i>Read RTL</i></td></tr>
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        <tr><td colspan="2">constraints.tcl</td>                                                                       <td><i>Set design constrains</i></td></tr>
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        <tr><td colspan="2"><b>results</b></td>                                                                       <td><i>Results directory</i></td></tr>
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        <tr><td colspan="3"><b>actel</b></td>                                                                         <td><i>Actel synthesis setup for area &amp; speed analysis</i></td></tr>
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        <tr><td colspan="3"><b>altera</b></td>                                                                        <td><i>Altera synthesis setup for area &amp; speed analysis</i></td></tr>
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        <tr><td colspan="3"><b>xilinx</b></td>                                                                        <td><i>Xilinx synthesis setup for area &amp; speed analysis</i></td></tr>
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</tbody></table>
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<br>
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<a name="3. Directory structure: FGPA projects"></a>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>3. Directory structure: FGPA projects</h1>
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<a name="3.1 Xilinx Spartan 3 example"></a>
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<h2>3.1 Xilinx Spartan 3 example</h2>
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<table border="1">
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        <tbody><tr><td colspan="7"><b>fpga</b></td>                                                                                    <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
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        <tr><td rowspan="53" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td>  <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr>
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        <tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td>             <td><i><b>Top level testbench directory</b></i></td></tr>
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        <tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td>           <td><i></i><br>
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</td></tr>
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        <tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td>     <td><i>FPGA testbench top level module</i></td></tr>
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        <tr><td colspan="3">registers.v</td>                                                                                    <td><i>Connections to Core internals for easy debugging</i></td></tr>
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        <tr><td colspan="3">msp_debug.v</td>                                                                                    <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
263
        <tr><td colspan="3">glbl.v</td>                                                                                         <td><i>Xilinx "glbl.v" file</i></td></tr>
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        <tr>
265
      <td colspan="3">timescale.v<br>
266
</td>      <td>   <i>Global time scale definition for simulation.</i>  </td>
267
    </tr>
268
<tr><td colspan="5"><b>doc</b></td>                                                                                     <td><i><b>Diverse documentation</b></i></td></tr>
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        <tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">board_user_guide.pdf</td>                      <td><i>Spartan-3 FPGA Starter Kit Board User Guide</i></td></tr>
270
        <tr><td colspan="4">msp430f1121a.pdf</td>                                                                               <td><i>msp430f1121a Specification</i></td></tr>
271
        <tr><td colspan="4">xapp462.pdf</td>                                                                                    <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr>
272
        <tr><td colspan="5"><b>rtl</b></td>                                                                                     <td><i><b>RTL sources</b></i></td></tr>
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        <tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td>            <td><br>
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</td></tr>
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        <tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td>         <td><i>FPGA top level file</i></td></tr>
276
        <tr><td colspan="3">driver_7segment.v</td>                                                                              <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
277
        <tr><td colspan="3">io_mux.v</td>                                                                                       <td><i>I/O mux for port function selection.</i></td></tr>
278
        <tr><td colspan="3"><b>openmsp430</b></td>                                                                              <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
279
        <tr><td colspan="3"><b>coregen</b></td>                                                                                 <td><i>Xilinx's coregen directory</i></td></tr>
280
        <tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">ram_8x512_hi.*</td>          <td><i>512 Byte RAM (upper byte)</i></td></tr>
281
        <tr><td colspan="2">ram_8x512_lo.*</td>                                                                               <td><i>512 Byte RAM (lower byte)</i></td></tr>
282
        <tr><td colspan="2">ram_8x2k_hi.*</td>                                                                                <td><i>2 kByte RAM (upper byte)</i></td></tr>
283
        <tr><td colspan="2">ram_8x2k_lo.*</td>                                                                                <td><i>2 kByte RAM (lower byte)</i></td></tr>
284
        <tr><td colspan="5"><b>sim</b></td>                                                                                     <td><i><b>Top level simulations directory</b></i></td></tr>
285
        <tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td>            <td><i><b>RTL simulations</b></i></td></tr>
286
        <tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td>               <td><i><b>RTL simulation scripts</b></i></td></tr>
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        <tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td>                <td><i>Main simulation script</i></td></tr>
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        <tr><td colspan="2">ihex2mem.tcl</td>                                                                                   <td><i>Verilog program memory file generation</i></td></tr>
289
        <tr><td colspan="2">rtlsim.sh</td>                                                                                      <td><i>Verilog Icarus simulation script</i></td></tr>
290
        <tr><td colspan="3"><b>run</b></td>                                                                                     <td><i><b>For running RTL simulations</b></i></td></tr>
291
        <tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td>                       <td><i>Run simulation of a given software project</i></td></tr>
292
        <tr><td colspan="2">run_disassemble</td>                                                                                <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
293
        <tr><td colspan="3"><b>src</b></td>                                                                                     <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
294
        <tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td>                  <td><i>Verilog simulator command file</i></td></tr>
295
        <tr><td colspan="2">*.v</td>                                                                                          <td><i>Stimulus vector for the corresponding software project</i></td></tr>
296
        <tr><td colspan="5"><b>software</b></td>                                                                                <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
297
        <tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td>                <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
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        <tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td>                  <td><i></i><br>
299
</td></tr>
300
        <tr><td colspan="3">hardware.h</td>                                                                                     <td><i></i><br>
301
</td></tr>
302
        <tr><td colspan="3">main.c</td>                                                                                         <td><i></i><br>
303
</td></tr>
304
        <tr><td colspan="3">7seg.h</td>                                                                                         <td><i></i><br>
305
</td></tr>
306
        <tr><td colspan="3">7seg.c</td>                                                                                         <td><i></i><br>
307
</td></tr>
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        <tr><td colspan="4"><b>ta_uart</b></td>                                                                                 <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr>
309
        <tr><td colspan="5"><b>synthesis</b></td>                                                                               <td><i><b>Top level synthesis directory</b></i></td></tr>
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        <tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td>              <td><i></i><br>
311
</td></tr>
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        <tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream.sh</td>       <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr>
313
        <tr><td colspan="3">create_bitstream.bat</td>                                                                           <td><i>Run Xilinx ISE synthesis in a Windows environment</i></td></tr>
314
        <tr><td colspan="3">openMSP430_fpga.ucf</td>                                                                            <td><i>UCF file</i></td></tr>
315
        <tr><td colspan="3">openMSP430_fpga.prj</td>                                                                            <td><i>RTL file list to be synthesized</i></td></tr>
316
        <tr><td colspan="3">xst_verilog.opt</td>                                                                                <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr>
317
        <tr><td colspan="3">load_rom.sh</td>                                                                                    <td><i>Update bitstream's program memory with a given software ELF file in a Linux environment</i></td></tr>
318
        <tr><td colspan="3">load_rom.bat</td>                                                                                   <td><i>Update bitstream's program memory with a given software ELF file in a Windows environment</i></td></tr>
319
        <tr><td colspan="3">memory.bmm</td>                                                                                     <td><i>FPGA memory description for bitstream's program memory update</i></td></tr>
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</tbody></table>
321
<br>
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323
<a name="3.2 Altera Cyclone II example"></a>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h2>3.2 Altera Cyclone II example</h2>
326
 
327
 
328
<table border="1">
329 100 olivier.gi
        <tbody><tr><td colspan="7"><b>fpga</b></td>                                                                                    <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
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        <tr><td rowspan="50" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr>
331
        <tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td>                   <td><i>README file</i></td></tr>
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        <tr><td colspan="5"><b>bench</b></td>                                                                                     <td><i><b>Top level testbench directory</b></i></td></tr>
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        <tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td>           <td><i></i><br>
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</td></tr>
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        <tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td>     <td><i>FPGA testbench top level module</i></td></tr>
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        <tr><td colspan="3">registers.v</td>                                                                                    <td><i>Connections to Core internals for easy debugging</i></td></tr>
337
        <tr><td colspan="3">msp_debug.v</td>                                                                                    <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
338
        <tr><td colspan="3">altsyncram.v</td>                                                                                   <td><i>Altera verilog model of the altsyncram module.</i></td></tr>
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        <tr>
340
      <td colspan="3" rowspan="1" style="vertical-align: top;">timescale.v<br>
341
      </td>
342
      <td style="vertical-align: top;"><i>Global time scale definition for simulation.</i>
343
      </td>
344
    </tr>
345
<tr><td colspan="5"><b>doc</b></td>                                                                                     <td><i><b>Diverse documentation</b></i></td></tr>
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        <tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">DE1_Board_Schematic.pdf</td>                   <td><i>Cyclone II FPGA Starter Development Board Schematics</i></td></tr>
347
        <tr><td colspan="4">DE1_Reference_Manual.pdf</td>                                                                       <td><i>Cyclone II FPGA Starter Development Board Reference Manual</i></td></tr>
348
        <tr><td colspan="4">DE1_User_Guide.pdf</td>                                                                             <td><i>Cyclone II FPGA Starter Development Board User Guide</i></td></tr>
349
        <tr><td colspan="5"><b>rtl</b></td>                                                                                     <td><i><b>RTL sources</b></i></td></tr>
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        <tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td>             <td><br>
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</td></tr>
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        <tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">OpenMSP430_fpga.v</td>         <td><i>FPGA top level file</i></td></tr>
353
        <tr><td colspan="3">driver_7segment.v</td>                                                                              <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
354
        <tr><td colspan="3">io_mux.v</td>                                                                                       <td><i>I/O mux for port function selection.</i></td></tr>
355
        <tr><td colspan="3">ext_de1_sram.v</td>                                                                                 <td><i>Interface with altera DE1's external async SRAM (256kwords x 16bits)</i></td></tr>
356
        <tr><td colspan="3">ram16x512.v</td>                                                                                    <td><i>Single port RAM generated with the megafunction wizard</i></td></tr>
357
        <tr><td colspan="3">rom16x2048.v</td>                                                                                   <td><i>Single port ROM generated with the megafunction wizard</i></td></tr>
358
        <tr><td colspan="3"><b>openmsp430</b></td>                                                                              <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
359
        <tr><td colspan="5"><b>sim</b></td>                                                                                     <td><i><b>Top level simulations directory</b></i></td></tr>
360
        <tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td>            <td><i><b>RTL simulations</b></i></td></tr>
361
        <tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td>               <td><i><b>RTL simulation scripts</b></i></td></tr>
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        <tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td>                <td><i>Main simulation script</i></td></tr>
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        <tr><td colspan="2">ihex2mem.tcl</td>                                                                                   <td><i>Verilog program memory file generation</i></td></tr>
364
        <tr><td colspan="2">rtlsim.sh</td>                                                                                      <td><i>Verilog Icarus simulation script</i></td></tr>
365
        <tr><td colspan="3"><b>run</b></td>                                                                                     <td><i><b>For running RTL simulations</b></i></td></tr>
366
        <tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td>                       <td><i>Run simulation of a given software project</i></td></tr>
367
        <tr><td colspan="2">run_disassemble</td>                                                                                <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
368
        <tr><td colspan="3"><b>src</b></td>                                                                                     <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
369
        <tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td>                  <td><i>Verilog simulator command file</i></td></tr>
370
        <tr><td colspan="2">*.v</td>                                                                                          <td><i>Stimulus vector for the corresponding software project</i></td></tr>
371
        <tr><td colspan="5"><b>software</b></td>                                                                                <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
372
        <tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>bin</b></td>                 <td><i>Specific binaries required for software development.</i></td></tr>
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        <tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">mifwrite.cpp</td>              <td><i>This
374
prog is taken from
375
http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly
376
changed to satisfy quartus6.1 *.mif eating engine.</i></td></tr>
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        <tr><td colspan="3">mifwrite.exe</td>                                                                                   <td><i>Windows executable.</i></td></tr>
378
        <tr><td colspan="3">mifwrite</td>                                                                                       <td><i>Linux executable.</i></td></tr>
379
        <tr><td colspan="4"><b>memledtest</b></td>                                                                              <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
380
        <tr><td colspan="5"><b>synthesis</b></td>                                                                               <td><i><b>Top level synthesis directory</b></i></td></tr>
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        <tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>altera</b></td>              <td><i></i><br>
382
</td></tr>
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        <tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">main.qsf</td>                  <td><i>Global Assignments file</i></td></tr>
384
        <tr><td colspan="3">main.sof</td>                                                                                       <td><i>SOF file</i></td></tr>
385
        <tr><td colspan="3">OpenMSP430_fpga.qpf</td>                                                                            <td><i>Quartus II project file</i></td></tr>
386
        <tr><td colspan="3">openMSP430_fpga_top.v</td>                                                                          <td><i>RTL file list to be synthesized</i></td></tr>
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</tbody></table>
388
<br>
389
 
390
<a name="3.3 Actel ProASIC3 example"></a>
391
<div style="text-align: right;"><a href="#TOC">Top</a></div>
392
<h2>3.3 Actel ProASIC3 example</h2>
393
 
394
<table border="1">
395
        <tbody><tr><td colspan="6"><b>fpga</b></td>                                                                                    <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
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        <tr><td rowspan="45" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>actel_m1a3pl_dev_kit</b></td> <td><i><b>Actel FPGA Project based on the ProASIC3 M1A3PL development kit<br>
397 100 olivier.gi
</b></i></td></tr>
398
 
399 116 olivier.gi
        <tr><td rowspan="44" style="vertical-align: top;"><font color="white">abcd</font></td>
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<td colspan="4"><b>bench</b></td>                                                                                     <td><i><b>Top level testbench directory</b></i></td></tr>
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        <tr><td colspan="1" rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td>           <td><i></i><br>
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</td></tr>
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        <tr><td colspan="1" rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">tb_openMSP430_fpga.v</td>
404 100 olivier.gi
     <td><i>FPGA testbench top level module</i></td></tr>
405
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;">registers.v</td>
406
                                                                                    <td><i>Connections to Core internals for easy debugging</i></td></tr>
407
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td>
408
                                                                                    <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
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        <tr>
410
      <td colspan="2" rowspan="1" style="vertical-align: top;">dbg_uart_tasks.v<br>
411
      </td>
412
      <td style="vertical-align: top;"><i>UART tasks for the serial debug interface.</i></td>
413
    </tr>
414
    <tr>
415
      <td colspan="2" rowspan="1" style="vertical-align: top;">timescale.v<br>
416
      </td>
417
      <td style="vertical-align: top;"><i>Global time scale definition for simulation.</i></td>
418
    </tr>
419
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">proasic3l.v</td>
420 100 olivier.gi
                                                                                   <td><i>Actel ProASIC3L library file.<br>
421
</i></td></tr>
422
        <tr>
423
      <td colspan="2" rowspan="1" style="vertical-align: top;">DAC121S101.v<br>
424
      </td>
425
      <td style="vertical-align: top;"><i>Verilog model of National's DAC121S101 12 bit DAC.</i></td>
426
    </tr>
427
<tr><td colspan="4"><b>doc</b></td>                                                                                     <td><i><b>Diverse documentation</b></i></td></tr>
428
        <tr><td rowspan="2"><font color="white">abcd</font></td> <td colspan="3">M1A3PL_DEV_KIT_QS.pdf</td>                   <td><i>Development Kit Quickstart Card.</i></td></tr>
429
        <tr><td colspan="3">M1IGLOO_StarterKit_v1_5_UG.pdf</td>                                                                       <td><i>Development Kit User's Guide.</i></td></tr>
430
 
431
        <tr><td colspan="4"><b>rtl</b></td>                                                                                     <td><i><b>RTL sources</b></i></td></tr>
432
        <tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td>             <td><br>
433
</td></tr>
434
        <tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">openMSP430_fpga.v</td>
435
         <td><i>FPGA top level file</i></td></tr>
436
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;">dac_spi_if.v</td>
437
                                                                              <td><i>SPI interface to National's DAC121S101 12 bit DAC.<br>
438
</i></td></tr>
439
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">smartgen</span><br>
440
      </td>
441
                                                                                       <td><i>Actel's smartgen directory.</i></td></tr>
442
 
443
        <tr><td style="vertical-align: top;"><font color="white">abcd</font></td>
444
<td colspan="1">dmem_128B.v</td>                                                                                    <td><i>128 Byte RAM (for data memory).<br>
445
</i></td></tr>
446
        <tr><td style="vertical-align: top;"><br>
447
      </td>
448
<td colspan="1">pmem_2kB.v</td>                                                                                   <td><i>2 kByte RAM (for program memory).<br>
449
</i></td></tr>
450
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>openmsp430</b></td>
451
                                                                              <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
452
        <tr><td colspan="4"><b>sim</b></td>                                                                                     <td><i><b>Top level simulations directory</b></i></td></tr>
453
        <tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>rtl_sim</b></td>            <td><i><b>RTL simulations</b></i></td></tr>
454
 
455
 
456
 
457
        <tr>                                                                                      <td rowspan="10" style="vertical-align: top;"><br>
458
      </td>
459
      <td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">bin</span><br>
460
      </td>
461
<td style="font-style: italic;"><span style="font-weight: bold;">RTL simulation scripts</span><br>
462
</td></tr>
463
        <tr>
464
      <td colspan="1" rowspan="3" style="vertical-align: top;"><br>
465
      </td>
466
      <td style="vertical-align: top;">msp430sim<br>
467
      </td>
468
      <td style="vertical-align: top;">Main simulation script<br>
469
      </td>
470
    </tr>
471
    <tr>
472
      <td style="vertical-align: top;">ihex2mem.tcl<br>
473
      </td>
474
      <td style="vertical-align: top;">Verilog program memory file generation<br>
475
      </td>
476
    </tr>
477
    <tr>
478
      <td style="vertical-align: top;">rtlsim.sh<br>
479
      </td>
480
      <td style="vertical-align: top;">Verilog Icarus simulation script<br>
481
      </td>
482
    </tr>
483
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>run</b></td>
484
                                                                                     <td><i><b>For running RTL simulations</b></i></td></tr>
485
 
486
        <tr>                                                                                <td colspan="1" rowspan="2" style="vertical-align: top;"><br>
487
      </td>
488
      <td style="vertical-align: top;">run<br>
489
      </td>
490
<td><i>Run simulation of a given software project<br>
491
</i></td></tr>
492
        <tr>
493
      <td style="vertical-align: top;">run_disassemble<br>
494
      </td>
495
      <td style="vertical-align: top;"><i>Disassemble the program memory content of the latest simulation</i></td>
496
    </tr>
497
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>src</b></td>
498
                                                                                     <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
499
 
500
        <tr>
501
      <td colspan="1" rowspan="2" style="vertical-align: top;"><br>
502
      </td>
503
      <td style="vertical-align: top;">submit.f<br>
504
      </td>
505
      <td style="vertical-align: top;"><span style="font-style: italic;">Verilog simulator command file</span><br>
506
      </td>
507
    </tr>
508
<tr>                                                                                          <td style="vertical-align: top;">*.v<br>
509
      </td>
510
<td><i>Stimulus vector for the corresponding software project</i></td></tr>
511
        <tr><td colspan="4"><b>software</b></td>                                                                                <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
512
 
513
 
514
 
515
 
516
        <tr><td colspan="1" rowspan="2" style="vertical-align: top;"><br>
517
      </td>
518
<td colspan="3"><span style="font-weight: bold;">spacewar</span><br>
519
</td>                                                                              <td><span style="font-style: italic;">SpaceWar oscilloscope game.</span><br>
520
</td></tr>
521
        <tr>
522
      <td style="vertical-align: top;"><br>
523
      </td>
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      <td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><img src="usercontent,img,1299013492" alt="Spacewar" title="Spacewar" width="25%"><br>
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      </td>
526
    </tr>
527
<tr><td colspan="4"><b>synthesis</b></td>                                                                               <td><i><b>Top level synthesis directory</b></i></td></tr>
528
        <tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>actel</b></td>              <td><br>
529
</td></tr>
530
        <tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">prepare_implementation.tcl<br>
531
      </td>
532
                  <td style="font-style: italic;">Generate required files prior synthesis and P&amp;R.<br>
533
</td></tr>
534
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;">synplify.tcl<br>
535
      </td>
536
                                                                                       <td style="font-style: italic;">Synplify template for the synthesis run.<br>
537
</td></tr>
538
        <tr><td colspan="2" rowspan="1" style="vertical-align: top;">libero_designer.tcl<br>
539
      </td>
540
                                                                            <td style="font-style: italic;">Libero Designer template for the P&amp;R run.<br>
541
</td></tr>
542
        <tr>
543
      <td colspan="2" rowspan="1" style="vertical-align: top;">design_files.v<br>
544
      </td>
545
      <td style="vertical-align: top; font-style: italic;">RTL file list to be synthesized.<br>
546
      </td>
547
    </tr>
548
    <tr>
549
      <td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.pre.sdc<br>
550
      </td>
551
      <td style="vertical-align: top; font-style: italic;">Synthesis timing constraints.<br>
552
      </td>
553
    </tr>
554
    <tr>
555
      <td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.post.sdc<br>
556
      </td>
557
      <td style="vertical-align: top; font-style: italic;">P&amp;R timing constraints.<br>
558
      </td>
559
    </tr>
560
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.pdc<br>
561
      </td>
562
                                                                          <td style="font-style: italic;">P&amp;R physical constraints.<br>
563
</td></tr>
564
</tbody></table>
565
 
566
<br>
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<a name="4. Directory structure: Software Development Tools"></a>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>4. Directory structure: Software Development Tools</h1>
570
 
571
<table border="1">
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        <tbody><tr><td colspan="4"><b>tools</b></td>                                                                                   <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr>
573
        <tr>
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      <td colspan="1" rowspan="19" style="vertical-align: top;"><font color="white">abcd</font></td>
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      <td colspan="3" rowspan="1" style="vertical-align: top;">omsp_alias.xml<br>
576
      </td>
577
      <td style="vertical-align: top;"><span style="font-style: italic;">This
578
XML file allows the software development tools to identify a openMSP430
579
implementation, and add customized extra information (Alias, URL, ...).</span><br>
580
      </td>
581
    </tr>
582
<tr> <td colspan="3"><b>bin</b></td>               <td><i><b>Contains the main TCL scripts (and the windows executable files if generated)<br>
583
</b></i></td></tr>
584
        <tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openmsp430-loader.tcl</td>    <td><i>Simple command line boot loader</i></td></tr>
585
 
586
        <tr><td colspan="2">openmsp430-minidebug.tcl</td>                                                                       <td><i>Minimalistic debugger with simple GUI</i></td></tr>
587
 
588
        <tr><td colspan="2">openmsp430-gdbproxy.tcl</td>                                                                        <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends<br>
589
</i></td></tr>
590
        <tr><td colspan="2">README.TXT</td>                                                                                     <td><i>README file regarding the use of TCL scripts in a Windows environment.</i></td></tr>
591
 
592
        <tr><td colspan="3"><b>lib</b></td>                                                                                     <td><i><b>Common library</b></i></td></tr>
593
        <tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="2"><b>tcl-lib</b></td>             <td><i><b>Common TCL library</b></i></td></tr>
594
        <tr><td colspan="1" rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="1">dbg_uart.tcl<i><br>
595
      </i></td>              <td style="vertical-align: top;"><i>Low level UART communication functions</i></td>
596
</tr>
597
        <tr><td rowspan="1" colspan="1">dbg_functions.tcl<i><br>
598
      </i></td>                                                                              <td style="vertical-align: top;"><i>Main utility functions for the openMSP430 serial debug interface</i></td>
599
</tr>
600
        <tr><td rowspan="1" colspan="1">combobox.tcl<i><br>
601
      </i></td>                                                                                   <td style="vertical-align: top;"><i>A combobox listbox widget written in pure tcl (from Bryan Oakley)</i></td>
602
</tr>
603
        <tr><td colspan="1">xml.tcl</td>                                                                                        <td style="vertical-align: top;"><i>Simple XML parser (from Keith Vetter)</i></td>
604
</tr>
605
        <tr><td colspan="3"><b>openmsp430-gdbproxy</b></td>                                                                     <td><i><b>GDB Proxy server main project directory</b></i></td></tr>
606
        <tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openmsp430-gdbproxy.tcl</td>  <td><i>GDB Proxy server main TCL Script (symbolic link with the script in the <b>bin</b> directory)</i></td></tr>
607
        <tr><td colspan="2">server.tcl</td>                                                                                     <td><i>TCP/IP Server utility functions. Send/Receive RSP packets from GDB.</i></td></tr>
608
        <tr><td colspan="2">commands.tcl</td>                                                                                   <td><i>RSP command execution functions.</i></td></tr>
609
        <tr><td colspan="2"><b>doc</b></td>                                                                                     <td><i><b>Some documentation regarding GDB and the RSP protocol.</b></i></td></tr>
610
        <tr><td rowspan="2"><font color="white">abcd</font></td> <td rowspan="1" colspan="1">ew_GDB_RSP.pdf<i><br>
611
      </i></td>                            <td style="vertical-align: top;"><i>Document from Bill Gatliff: Embedding with GNU: the gdb Remote Serial Protocol</i></td>
612
</tr>
613
        <tr><td rowspan="1" colspan="1">Howto-GDB_Remote_Serial_Protocol.pdf<i><br>
614
      </i></td>                                                           <td style="vertical-align: top;"><i>Document from Jeremy Bennett (Embecosm): Howto: GDB Remote Serial Protocol - Writing a RSP Server</i></td>
615
</tr>
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617
 
618
 
619
 
620
 
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</tbody></table>
622
<br>
623
<div style="text-align: right;"><a href="#TOC">Top</a></div>
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