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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 Core</title></head>
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<body>
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<h3>Table of content</h3>
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<ul>
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<li><a href="#1.%20Introduction"> 1. Introduction</a></li>
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<li><a href="#2.%20Peripherals"> 2. Peripherals</a>
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<ul>
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<li><a href="#2.1_System_Peripherals"> 2.1 System Peripherals</a>
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<ul>
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<li><a href="#2.1.1%20Basic%20Clock%20Module"> 2.1.1 Basic Clock Module: FPGA</a></li>
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<li><a href="#2.1.2_Basic_Clock_Module_ASIC"> 2.1.2 Basic Clock Module: ASIC</a></li>
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<li><a href="#2.1.3_SFR"> 2.1.3 SFR</a><br></li>
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<li><a href="#2.1.4%20Watchdog%20Timer"> 2.1.4 Watchdog Timer</a></li>
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<li><a href="#2.1.5%2016x16%20Hardware%20Multiplier"> 2.1.5 16x16 Hardware Multiplier</a></li>
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</ul>
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</li>
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<li><a href="#2.2_External_Peripherals"> 2.2 External Peripherals</a>
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<ul>
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<li><a href="#2.2.1%20Digital%20I/O"> 2.2.1 Digital I/O (FPGA ONLY)</a></li>
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<li><a href="#2.2.2%20Timer%20A"> 2.2.2 Timer A (FPGA ONLY)</a></li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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In addition to the CPU core itself, several peripherals are
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also provided and can be easily connected to the core during
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integration.
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<br><br>
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<a name="2. Peripherals"></a>
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<h1>2. Peripherals</h1>
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<a name="2.1_System_Peripherals"></a>
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<h2>2.1 System Peripherals</h2>
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In addition to the CPU core itself, several peripherals are also
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provided and can be easily connected to the core during integration.
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The followings are directly integrated within the core because of their
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tight links with the CPU.<br>
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It is to be noted that <span style="font-weight: bold;">ALL</span> system peripherals support both ASIC and FPGA versions.<br>
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<a name="2.1.1 Basic Clock Module"></a>
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<h3>2.1.1 Basic Clock Module: FPGA</h3>
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<br>
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In order to make an FPGA
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implementation as simple as possible (ideally, a non-professional designer should be
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able to do it), clock gates are not used in this design configuration and neither are
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clock muxes.
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<br>
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With these constrains, the Basic Clock Module is implemented as following:
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<br><br>
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<img src="http://opencores.org/usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="80%">
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<br>
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<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the
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CPU state machines in an IDLE state while MCLK will still be running.
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<br><br>
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In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
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<br><br>
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<img src="http://opencores.org/usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example">
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<br><br>For example, the following Verilog code would implement a counter clocked with SMCLK:
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<br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br>
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</td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td>
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<code>
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reg [7:0] test_cnt;
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<br>
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<br>always @ (posedge mclk or posedge puc_rst)
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<br> if (puc_rst) test_cnt <= 8'h00;
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<br> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
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</code>
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</td>
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</tr>
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</tbody></table>
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<br><br>
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<b>Register Description (FPGA)</b>
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<br><br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b>Register Name</b></td>
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<td rowspan="2"><b>Address</b></td>
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<td colspan="16"><b>Bit Field</b></td>
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</tr>
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<tr align="center">
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<td>7</td>
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<td>6</td>
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<td>5</td>
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<td>4</td>
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<td>3</td>
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<td>2</td>
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<td>1</td>
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<td>0</td>
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</tr>
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<tr align="center">
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<td>DCOCTL</td>
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<td>0x0004</td>
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<td colspan="8"><small><i>not implemented</i></small></td>
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</tr>
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<tr align="center">
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<td>BCSTL1</td>
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<td>0x0006</td>
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<td colspan="2"><small><i>unused</i></small></td>
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<td colspan="2"><b>DIVAx</b></td>
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<td colspan="4"><small><i>unused</i></small></td>
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</tr>
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<tr align="center">
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<td>BCSTL2</td>
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<td>0x0008</td>
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<td colspan="4"><small><i>unused</i></small></td>
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<td colspan="1"><b>SELS</b></td>
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<td colspan="2"><b>DIVSx</b></td>
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<td colspan="1"><small><i>unused</i></small></td>
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</tr>
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</tbody>
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</table>
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<ul>
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<li>BCSCTL1.<b>DIVAx</b> : ACLK_EN divider (1/2/4/8)</li>
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<li>BCSCTL2.<b>SELS</b>  : SMCLK_EN clock selection (0:DCO_CLK / 1:LFXT_CLK)</li>
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<li>BCSCTL2.<b>DIVSx</b> : SMCLK_EN divider (1/2/4/8)</li>
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</ul>
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<a name="2.1.2_Basic_Clock_Module_ASIC"></a>
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<h3>2.1.2 Basic Clock Module: ASIC</h3>
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<br>
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When targeting an ASIC, up to all clock management
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options available in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 4) can be included:<br><br>
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<img src="http://opencores.org/usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="80%"><br>
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Additional info can be found in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
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section.<br>
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<br>
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<b>Register Description (ASIC)</b>
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<br><br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b>Register Name</b></td>
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<td rowspan="2"><b>Address</b></td>
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<td colspan="16"><b>Bit Field</b></td>
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</tr>
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<tr align="center">
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<td>7</td>
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<td>6</td>
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<td>5</td>
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<td>4</td>
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<td>3</td>
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<td>2</td>
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<td>1</td>
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<td>0</td>
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</tr>
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<tr align="center">
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<td>DCOCTL</td>
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<td>0x0004</td>
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<td colspan="8"><small><i>not implemented</i></small></td>
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</tr>
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<tr align="center">
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<td>BCSTL1</td>
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<td>0x0006</td>
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<td colspan="2"><small><i>unused</i></small></td>
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<td colspan="2"><b>DIVAx</b></td>
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<td colspan="1"><b><small>DMA_SCG1</small></b></td>
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<td colspan="1"><b><small>DMA_SCG0</small></b></td>
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<td colspan="1"><b><small>DMA_OSCOFF</small></b></td>
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<td colspan="1"><b><small>DMA_CPUOFF</small></b></td>
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</tr>
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<tr align="center">
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<td>BCSTL2</td>
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<td>0x0008</td>
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<td colspan="1"><b>SELMx</b></td>
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<td colspan="1"><small><i>unused</i></small></td>
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<td colspan="2"><b>DIVMx</b></td>
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<td colspan="1"><b>SELS</b></td>
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<td colspan="2"><b>DIVSx</b></td>
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<td colspan="1"><small><i>unused</i></small></td>
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</tr>
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</tbody>
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</table>
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<ul>
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<li>BCSCTL1.<b>DIVAx</b>     : ACLK clock divider (1/2/4/8)</li>
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<li>BCSCTL1.<b>DMA_SCG1</b>   : Restore SMCLK with DMA wakeup</li>
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<li>BCSCTL1.<b>DMA_SCG0</b>   : Restore DCO oscillator with DMA wakeup</li>
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<li>BCSCTL1.<b>DMA_OSCOFF</b> : Restore LFXT oscillator with DMA wakeup</li>
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<li>BCSCTL1.<b>DMA_CPUOFF</b> : Restore MCLK with DMA wakeup</li>
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<li>BCSCTL2.<b>SELMx</b>     : MCLK clock selection (0:DCO_CLK / 1:LFXT_CLK)</li>
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<li>BCSCTL2.<b>DIVMx</b>     : MCLK clock divider (1/2/4/8)</li>
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<li>BCSCTL2.<b>SELS</b>      : SMCLK clock selection (0:DCO_CLK / 1:LFXT_CLK)</li>
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<li>BCSCTL2.<b>DIVSx</b>     : SMCLK clock divider (1/2/4/8)</li>
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</ul>
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<a name="2.1.3_SFR"></a>
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<h3>2.1.3 SFR</h3>
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Following the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a>, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:<br>
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<br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b><small>Register Name</small></b></td>
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<td rowspan="2"><b><small>Address</small></b></td>
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<td colspan="8" rowspan="1" style="vertical-align: top;"><small style="font-weight: bold;">Bit Fields</small><br>
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</td>
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</tr>
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<tr align="center">
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<td style="vertical-align: top;"><small>7<br>
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</small></td>
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<td style="vertical-align: top;"><small>6<br>
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</small></td>
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<td style="vertical-align: top;"><small>5<br>
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</small></td>
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<td style="vertical-align: top;"><small>4<br>
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</small></td>
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<td style="vertical-align: top;"><small>3<br>
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</small></td>
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<td style="vertical-align: top;"><small>2<br>
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</small></td>
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<td style="vertical-align: top;"><small>1<br>
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</small></td>
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<td style="vertical-align: top;"><small>0<br>
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</small></td>
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</tr>
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<tr align="center">
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<td>IE1<br>
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</td>
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<td><small>0x0000</small></td>
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<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><small> Reserved <br>
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</small></td>
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<td style="vertical-align: top;">NMIIE <b><sup><font color="#ff0000">1</font></sup></b></td>
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<td colspan="3" rowspan="1" style="vertical-align: top;"><small> Reserved </small>
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</td>
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<td style="vertical-align: top;">WDTIE <b><sup><font color="#ff0000">2</font></sup></b></td>
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</tr>
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<tr align="center">
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<td>IFG1<br>
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</td>
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<td><small>0x0002</small></td>
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<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small><br>
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</td>
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<td style="vertical-align: top;">NMIIFG <b><sup><font color="#ff0000">1</font></sup></b></td>
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<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small></td>
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<td style="vertical-align: top;">WDTIFG <b><sup><font color="#ff0000">2</font></sup></b></td>
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</tr>
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</tbody>
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</table>
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<br>
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<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
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<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
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<br>
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In addition, three 16-bit read-only registers have been added in order
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to let the software know with which version of the openMSP430 it is
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running:<br>
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<br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b><small>Register Name</small></b></td>
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<td rowspan="2"><b><small>Address</small></b></td>
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<td colspan="16"><b><small>Bit Field</small></b></td>
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</tr>
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<tr align="center">
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<td><small>15</small></td><td><small>14</small></td>
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| 293 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 294 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 295 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 296 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 297 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 298 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 299 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 300 |
|
|
</tr>
|
| 301 |
|
|
<tr align="center">
|
| 302 |
|
|
<td><small>CPU_ID_LO</small></td>
|
| 303 |
|
|
<td><small>0x0004</small></td>
|
| 304 |
|
|
<td colspan="7"><font size="-5">PER_SPACE</font></td>
|
| 305 |
|
|
<td colspan="5"><font size="-5">USER_VERSION</font></td>
|
| 306 |
|
|
<td colspan="1"><font size="-5">ASIC</font></td>
|
| 307 |
|
|
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
|
| 308 |
|
|
</tr>
|
| 309 |
|
|
<tr align="center">
|
| 310 |
|
|
<td><small>CPU_ID_HI</small></td>
|
| 311 |
|
|
<td><small>0x0006</small></td>
|
| 312 |
|
|
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
|
| 313 |
|
|
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
|
| 314 |
|
|
<td colspan="1"><font size="-5">MPY</font></td>
|
| 315 |
|
|
</tr><tr>
|
| 316 |
|
|
<td style="vertical-align: top; text-align: center;"><small>CPU_NR</small></td>
|
| 317 |
|
|
<td style="vertical-align: top; text-align: center;"><small>0x0008</small></td>
|
| 318 |
|
|
<td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_TOTAL_NR</font></td>
|
| 319 |
|
|
<td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_INST_NR</font></td>
|
| 320 |
|
|
</tr>
|
| 321 |
|
|
|
| 322 |
|
|
</tbody>
|
| 323 |
|
|
</table>
|
| 324 |
|
|
<br>
|
| 325 |
|
|
<table border="0">
|
| 326 |
|
|
|
| 327 |
|
|
<tbody><tr>
|
| 328 |
|
|
<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td>
|
| 329 |
|
|
<td>: Current CPU version<br>
|
| 330 |
|
|
</td>
|
| 331 |
|
|
</tr>
|
| 332 |
|
|
<tr>
|
| 333 |
|
|
<td> </td><td valign="top"><li><b>ASIC</b></li></td>
|
| 334 |
|
|
<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
|
| 335 |
|
|
</tr>
|
| 336 |
|
|
<tr>
|
| 337 |
|
|
<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td>
|
| 338 |
|
|
<td>: Reflects the value defined in the <b style="font-style: italic;">openMSP430_defines.v</b> file.</td>
|
| 339 |
|
|
</tr>
|
| 340 |
|
|
<tr>
|
| 341 |
|
|
<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td>
|
| 342 |
|
|
<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
|
| 343 |
|
|
</tr>
|
| 344 |
|
|
<tr>
|
| 345 |
|
|
<td> </td><td valign="top"><li><b>MPY</b></li></td>
|
| 346 |
|
|
<td>: This bit is set if the hardware multiplier is included in the current implementation</td>
|
| 347 |
|
|
</tr>
|
| 348 |
|
|
<tr>
|
| 349 |
|
|
<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
|
| 350 |
|
|
<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
|
| 351 |
|
|
</tr>
|
| 352 |
|
|
<tr>
|
| 353 |
|
|
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
|
| 354 |
|
|
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
|
| 355 |
|
|
</tr>
|
| 356 |
|
|
<tr>
|
| 357 |
|
|
<td> </td><td valign="top"><li><b>CPU_INST_NR</b></li></td>
|
| 358 |
|
|
<td>: Current oMSP instance number (for multicore systems)</td>
|
| 359 |
|
|
</tr>
|
| 360 |
|
|
<tr>
|
| 361 |
|
|
<td> </td><td valign="top"><li><b>CPU_TOTAL_NR</b></li></td>
|
| 362 |
|
|
<td>: Total number of oMSP instances-1 (for multicore systems)</td>
|
| 363 |
|
|
</tr>
|
| 364 |
|
|
</tbody>
|
| 365 |
|
|
</table>
|
| 366 |
|
|
<br>
|
| 367 |
|
|
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span>, <span style="font-style: italic;">CPU_ID_HI</span> and <span style="font-style: italic;">CPU_NR</span> are identical to the Serial Debug Interface register counterparts.<br>
|
| 368 |
|
|
|
| 369 |
|
|
<a name="2.1.4 Watchdog Timer"></a>
|
| 370 |
|
|
<h3>2.1.4 Watchdog Timer</h3>
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.<br>
|
| 376 |
|
|
|
| 377 |
|
|
<br>
|
| 378 |
|
|
|
| 379 |
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the watchdog timer should be included or not:<br>
|
| 380 |
|
|
<br>
|
| 381 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 382 |
|
|
|
| 383 |
|
|
<tbody><tr>
|
| 384 |
|
|
<td width="35"><br>
|
| 385 |
|
|
</td>
|
| 386 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 387 |
|
|
</td>
|
| 388 |
|
|
<td width="15"><br>
|
| 389 |
|
|
</td>
|
| 390 |
|
|
<td>
|
| 391 |
|
|
<code>//-------------------------------------------------------<br>
|
| 392 |
|
|
// Include/Exclude Watchdog timer<br>
|
| 393 |
|
|
//-------------------------------------------------------<br>
|
| 394 |
|
|
// When excluded, the following functionality will be<br>
|
| 395 |
|
|
// lost:<br>
|
| 396 |
|
|
// - Watchog (both interval and watchdog modes)<br>
|
| 397 |
|
|
// - NMI interrupt edge selection<br>
|
| 398 |
|
|
// - Possibility to generate a software PUC reset<br>
|
| 399 |
|
|
//-------------------------------------------------------<br>
|
| 400 |
|
|
`define WATCHDOG</code></td></tr></tbody>
|
| 401 |
|
|
</table>
|
| 402 |
|
|
<br>
|
| 403 |
|
|
<a name="2.1.5 16x16 Hardware Multiplier"></a>
|
| 404 |
|
|
<h3>2.1.5 16x16 Hardware Multiplier</h3>
|
| 405 |
|
|
|
| 406 |
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
|
| 407 |
|
|
<br><br>
|
| 408 |
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not:<br><br>
|
| 409 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 410 |
|
|
<tbody><tr>
|
| 411 |
|
|
<td width="35"><br>
|
| 412 |
|
|
</td>
|
| 413 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 414 |
|
|
</td>
|
| 415 |
|
|
<td width="15"><br>
|
| 416 |
|
|
</td>
|
| 417 |
|
|
<td>
|
| 418 |
|
|
<code>
|
| 419 |
|
|
// Include/Exclude Hardware Multiplier
|
| 420 |
|
|
<br>`define MULTIPLIER
|
| 421 |
|
|
</code>
|
| 422 |
|
|
</td>
|
| 423 |
|
|
</tr>
|
| 424 |
|
|
</tbody></table>
|
| 425 |
|
|
<a name="2.2_External_Peripherals"></a>
|
| 426 |
|
|
<h2>2.2 External Peripherals</h2>
|
| 427 |
|
|
The external peripherals labeld with the "FPGA ONLY" tag do not contain
|
| 428 |
|
|
any clock gate nor clock muxes and are clocked with MCLK only. This
|
| 429 |
|
|
mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.<br>
|
| 430 |
|
|
<br>
|
| 431 |
|
|
<a name="2.2.1 Digital I/O"></a>
|
| 432 |
|
|
<h3>2.2.1 Digital I/O (FPGA ONLY)<br>
|
| 433 |
|
|
</h3>
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
|
| 437 |
|
|
<br>
|
| 438 |
|
|
<br>
|
| 439 |
|
|
|
| 440 |
|
|
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
|
| 441 |
|
|
<br>
|
| 442 |
|
|
<br>
|
| 443 |
|
|
|
| 444 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 445 |
|
|
|
| 446 |
|
|
<tbody><tr>
|
| 447 |
|
|
<td width="35"><br>
|
| 448 |
|
|
</td>
|
| 449 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 450 |
|
|
</td>
|
| 451 |
|
|
<td width="15"><br>
|
| 452 |
|
|
</td>
|
| 453 |
|
|
<td>
|
| 454 |
|
|
<code>
|
| 455 |
|
|
parameter P1_EN = 1'b1; // Enable Port 1
|
| 456 |
|
|
<br>parameter P2_EN = 1'b1; // Enable Port 2
|
| 457 |
|
|
<br>parameter P3_EN = 1'b0; // Enable Port 3
|
| 458 |
|
|
<br>parameter P4_EN = 1'b0; // Enable Port 4
|
| 459 |
|
|
<br>parameter P5_EN = 1'b0; // Enable Port 5
|
| 460 |
|
|
<br>parameter P6_EN = 1'b0; // Enable Port 6
|
| 461 |
|
|
</code>
|
| 462 |
|
|
</td>
|
| 463 |
|
|
</tr>
|
| 464 |
|
|
</tbody>
|
| 465 |
|
|
</table>
|
| 466 |
|
|
|
| 467 |
|
|
<br>
|
| 468 |
|
|
|
| 469 |
|
|
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
|
| 470 |
|
|
<br>
|
| 471 |
|
|
<br>
|
| 472 |
|
|
|
| 473 |
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
| 474 |
|
|
|
| 475 |
|
|
<tbody><tr>
|
| 476 |
|
|
<td width="35"><br>
|
| 477 |
|
|
</td>
|
| 478 |
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
| 479 |
|
|
</td>
|
| 480 |
|
|
<td width="15"><br>
|
| 481 |
|
|
</td>
|
| 482 |
|
|
<td>
|
| 483 |
|
|
<code>
|
| 484 |
|
|
gpio #(.P1_EN(1),
|
| 485 |
|
|
<br> .P2_EN(1),
|
| 486 |
|
|
<br> .P3_EN(1),
|
| 487 |
|
|
<br> .P4_EN(0),
|
| 488 |
|
|
<br> .P5_EN(0),
|
| 489 |
|
|
<br> .P6_EN(0)) gpio_0 (
|
| 490 |
|
|
</code>
|
| 491 |
|
|
</td>
|
| 492 |
|
|
</tr>
|
| 493 |
|
|
</tbody>
|
| 494 |
|
|
</table>
|
| 495 |
|
|
|
| 496 |
|
|
<br>
|
| 497 |
|
|
|
| 498 |
|
|
The full pinout of the GPIO module is provided in the following table:
|
| 499 |
|
|
<br>
|
| 500 |
|
|
<br>
|
| 501 |
|
|
|
| 502 |
|
|
<table border="1">
|
| 503 |
|
|
|
| 504 |
|
|
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
| 505 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
| 506 |
|
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
| 507 |
|
|
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
| 508 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
| 509 |
|
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
| 510 |
|
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
| 511 |
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
| 512 |
|
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| 513 |
|
|
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
|
| 514 |
|
|
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
|
| 515 |
|
|
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
|
| 516 |
|
|
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
|
| 517 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
|
| 518 |
|
|
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
|
| 519 |
|
|
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
|
| 520 |
|
|
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
|
| 521 |
|
|
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
|
| 522 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
|
| 523 |
|
|
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
|
| 524 |
|
|
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
|
| 525 |
|
|
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
|
| 526 |
|
|
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
|
| 527 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
|
| 528 |
|
|
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
|
| 529 |
|
|
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
|
| 530 |
|
|
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
|
| 531 |
|
|
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
|
| 532 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
|
| 533 |
|
|
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
|
| 534 |
|
|
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
|
| 535 |
|
|
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
|
| 536 |
|
|
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
|
| 537 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
|
| 538 |
|
|
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
|
| 539 |
|
|
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
|
| 540 |
|
|
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
|
| 541 |
|
|
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
|
| 542 |
|
|
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
|
| 543 |
|
|
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
|
| 544 |
|
|
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
|
| 545 |
|
|
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
|
| 546 |
|
|
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
|
| 547 |
|
|
</tbody>
|
| 548 |
|
|
</table>
|
| 549 |
|
|
|
| 550 |
|
|
|
| 551 |
|
|
<a name="2.2.2 Timer A"></a>
|
| 552 |
|
|
<h3>2.2.2 Timer A (FPGA ONLY)</h3>
|
| 553 |
|
|
|
| 554 |
|
|
|
| 555 |
|
|
|
| 556 |
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100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
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<br>
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<br>
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The full pinout of the Timer A module is provided in the following table:
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<br>
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<br>
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<table border="1">
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<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
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<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
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<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
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<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
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<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
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<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
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<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
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<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
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<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
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<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
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<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
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<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
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<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
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<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
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<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
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<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
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<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
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<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
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<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
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<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
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<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
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<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
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<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
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<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
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<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
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<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
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<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
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<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
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</tbody>
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</table>
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<br>
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<b>Note</b>: for the same reason as with the Basic Clock Module FPGA version, the
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two additional clock inputs (TACLK and INCLK) are internally
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synchronized with the MCLK domain.
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As a consequence, TACLK and INCLK should be at least 2 times slowlier
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than MCLK, and if these clock are used toghether with the Timer A
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output unit, some jitter might be observed on the generated output.
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If this jitter is critical for the application, ACLK and INCLK should
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idealy be derivated from DCO_CLK.
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<br>
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<br>
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<br>
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<br><br>
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</body></html>
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