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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 Serial Debug Interface</title></head><body>
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<a name="TOC"></a>
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<h3>Table of content</h3>
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<ul>
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<li><a href="#1.%20Introduction"> 1. Introduction</a></li>
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<li><a href="#2.%20Debug%20Unit"> 2. Debug Unit</a>
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<ul>
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<li><a href="#2.1%20Register%20Mapping"> 2.1 Register Mapping</a></li>
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<li><a href="#2.2%20CPU%20Control/Status%20Registers"> 2.2 CPU Control/Status Registers</a></li>
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<ul>
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<li><a href="#2.2.1%20CPU_ID"> 2.2.1 CPU_ID</a></li>
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<li><a href="#2.2.2%20CPU_CTL"> 2.2.2 CPU_CTL</a></li>
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<li><a href="#2.2.3%20CPU_STAT"> 2.2.3 CPU_STAT</a></li>
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</ul>
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<li><a href="#2.3%20Memory%20Access%20Registers"> 2.3 Memory Access Registers</a></li>
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<ul>
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<li><a href="#2.3.1%20MEM_CTL"> 2.3.1 MEM_CTL</a></li>
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<li><a href="#2.3.2%20MEM_ADDR"> 2.3.2 MEM_ADDR</a></li>
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<li><a href="#2.3.3%20MEM_DATA"> 2.3.3 MEM_DATA</a></li>
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<li><a href="#2.3.4%20MEM_CNT"> 2.3.4 MEM_CNT</a></li>
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</ul>
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<li><a href="#2.4%20Hardware%20Breakpoint%20Unit%20Registers">2.4 Hardware Breakpoint Unit Registers</a></li>
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<ul>
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<li><a href="#2.4.1%20BRKx_CTL"> 2.4.1 BRKx_CTL</a></li>
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<li><a href="#2.4.2%20BRKx_STAT"> 2.4.2 BRKx_STAT</a></li>
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<li><a href="#2.4.3%20BRKx_ADDR0"> 2.4.3 BRKx_ADDR0</a></li>
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<li><a href="#2.4.4%20BRKx_ADDR1"> 2.4.4 BRKx_ADDR1</a></li>
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</ul>
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</ul>
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</li>
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<li><a href="#3.%20Debug%20Communication%20Interface:%20UART"> 3. Debug Communication Interface: UART</a>
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<ul>
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<li><a href="#3.1%20Serial%20communication%20protocol:%208N1"> 3.1 Serial communication protocol: 8N1</a></li>
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<li><a href="#3.2%20Synchronization%20frame"> 3.2 Synchronization frame</a></li>
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<li><a href="#3.3%20Read/Write%20access%20to%20the%20debug%20registers"> 3.3 Read/Write access to the debug registers</a></li>
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<ul>
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<li><a href="#3.3.1%20Command%20Frame"> 3.3.1 Command Frame</a></li>
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<li><a href="#3.3.2%20Write%20access"> 3.3.2 Write access</a></li>
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<li><a href="#3.3.3%20Read%20access"> 3.3.3 Read access</a></li>
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</ul>
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<li><a href="#3.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">3.4 Read/Write burst implementation for the CPU Memory access</a></li>
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<ul>
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<li><a href="#3.4.1%20Write%20Burst%20access"> 3.4.1 Write Burst access</a></li>
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<li><a href="#3.4.2%20Read%20Burst%20access"> 3.4.2 Read Burst access</a></li>
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</ul>
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</ul>
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</li></ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The original MSP430 from TI provides a serial debug interface to allow
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in-system software debugging. In that case, the communication
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with the host computer is typically built on a JTAG or Spy-Bi-Wire
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serial protocol. However, the global debug architecture from the MSP430
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is unfortunately poorly documented on the web (and is also probably
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tightly linked with the internal core architecture).
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<br><br>A custom module has therefore been implemented for the
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openMSP430. The communication with the host is done with a simple two-wire RS232
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cable (8N1 serial protocol) and the debug unit provides all the
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required features for Nexus Class 3 debugging (beside trace), namely: <ul>
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<li>CPU control (run, stop, step, reset).</li>
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<li>Software & hardware breakpoint support.</li>
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<li>Hardware watchpoint support.<br>
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</li>
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<li>Memory read/write on-the-fly (no need to halt execution).</li>
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<li>CPU registers read/write on-the-fly (no need to halt execution).</li>
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</ul>
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<a name="2. Debug Unit"></a>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>2. Debug Unit</h1>
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<a name="2.1 Register Mapping"></a>
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<h2>2.1 Register Mapping</h2>
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The following table summarize the complete debug register set accessible through the debug communication interface:
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<br><br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b><small>Register Name</small></b></td>
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<td rowspan="2"><b><small>Address</small></b></td>
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<td colspan="16"><b><small>Bit Field</small></b></td>
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</tr>
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<td><small>15</small></td><td><small>14</small></td>
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<td><small>13</small></td><td><small>12</small></td>
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<td><small>11</small></td><td><small>10</small></td>
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<td><small> 9</small></td><td><small> 8</small></td>
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<td><small> 7</small></td><td><small> 6</small></td>
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<td><small> 5</small></td><td><small> 4</small></td>
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<td><small> 3</small></td><td><small> 2</small></td>
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<td><small> 1</small></td><td><small> 0</small></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.2.1%20CPU_ID">CPU_ID_LO</a></small></td>
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<td><small>0x00</small></td>
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<td colspan="7"><font size="-5">PER_SPACE</font></td>
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<td colspan="5"><font size="-5">USER_VERSION</font></td>
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<td colspan="1"><font size="-5">ASIC</font></td>
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<td colspan="3"><font size="-5">CPU_VERSION</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.2.1%20CPU_ID">CPU_ID_HI</a></small></td>
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<td><small>0x01</small></td>
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<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
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<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
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<td colspan="1"><font size="-5">MPY</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.2.2%20CPU_CTL">CPU_CTL</a></small></td>
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<td><small>0x02</small></td>
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<td colspan="9"><font size="-5">Reserved</font></td>
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<td><font size="-5">CPU_RST</font></td>
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<td><font size="-5">RST_BRK_EN</font></td>
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<td><font size="-5">FRZ_BRK_EN</font></td>
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<td><font size="-5">SW_BRK_EN</font></td>
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<td><font size="-5">ISTEP</font></td>
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<td><font size="-5">RUN</font></td>
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<td><font size="-5">HALT</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.2.3%20CPU_STAT">CPU_STAT</a></small></td>
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<td><small>0x03</small></td>
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<td colspan="8"><font size="-5">Reserved</font></td>
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<td><font size="-5">HWBRK3_PND</font></td>
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<td><font size="-5">HWBRK2_PND</font></td>
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<td><font size="-5">HWBRK1_PND</font></td>
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<td><font size="-5">HWBRK0_PND</font></td>
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<td><font size="-5">SWBRK_PND</font></td>
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<td><font size="-5">PUC_PND</font></td>
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<td><font size="-5">Res.</font></td>
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<td><font size="-5">HALT_RUN</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.1%20MEM_CTL">MEM_CTL</a></small></td>
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<td><small>0x04</small></td>
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<td colspan="12"><font size="-5">Reserved</font></td>
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<td><font size="-5">B/W</font></td>
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<td><font size="-5">MEM/REG</font></td>
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<td><font size="-5">RD/WR</font></td>
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<td><font size="-5">START</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.2%20MEM_ADDR">MEM_ADDR</a></small></td>
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<td><small>0x05</small></td>
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<td colspan="16"><font size="-5">MEM_ADDR[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.3%20MEM_DATA">MEM_DATA</a></small></td>
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<td><small>0x06</small></td>
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<td colspan="16"><font size="-5">MEM_DATA[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.4%20MEM_CNT">MEM_CNT</a></small></td>
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<td><small>0x07</small></td>
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<td colspan="16"><font size="-5">MEM_CNT[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.1%20BRKx_CTL">BRK0_CTL</a></small></td>
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<td><small>0x08</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.2%20BRKx_STAT">BRK0_STAT</a></small></td>
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<td><small>0x09</small></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK0_ADDR0</a></small></td>
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<td><small>0x0A</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK0_ADDR1</a></small></td>
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<td><small>0x0B</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.1%20BRKx_CTL">BRK1_CTL</a></small></td>
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<td><small>0x0C</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.2%20BRKx_STAT">BRK1_STAT</a></small></td>
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<td><small>0x0D</small></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK1_ADDR0</a></small></td>
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<td><small>0x0E</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK1_ADDR1</a></small></td>
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<td><small>0x0F</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.1%20BRKx_CTL">BRK2_CTL</a></small></td>
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<td><small>0x10</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.2%20BRKx_STAT">BRK2_STAT</a></small></td>
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<td><small>0x11</small></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
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</tr>
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| 240 |
|
|
<tr align="center">
|
| 241 |
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<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK2_ADDR0</a></small></td>
|
| 242 |
|
|
<td><small>0x12</small></td>
|
| 243 |
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
|
| 244 |
|
|
</tr>
|
| 245 |
|
|
<tr align="center">
|
| 246 |
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<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK2_ADDR1</a></small></td>
|
| 247 |
|
|
<td><small>0x13</small></td>
|
| 248 |
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
|
| 249 |
|
|
</tr>
|
| 250 |
|
|
<tr align="center">
|
| 251 |
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<td><small><a href="#2.4.1%20BRKx_CTL">BRK3_CTL</a></small></td>
|
| 252 |
|
|
<td><small>0x14</small></td>
|
| 253 |
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<td colspan="11"><font size="-5">Reserved</font></td>
|
| 254 |
|
|
<td><font size="-5">RANGE_MODE</font></td>
|
| 255 |
|
|
<td><font size="-5">INST_EN</font></td>
|
| 256 |
|
|
<td><font size="-5">BREAK_EN</font></td>
|
| 257 |
|
|
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
|
| 258 |
|
|
</tr>
|
| 259 |
|
|
<tr align="center">
|
| 260 |
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<td><small><a href="#2.4.2%20BRKx_STAT">BRK3_STAT</a></small></td>
|
| 261 |
|
|
<td><small>0x15</small></td>
|
| 262 |
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<td colspan="10"><font size="-5">Reserved</font></td>
|
| 263 |
|
|
<td><font size="-5">RANGE_WR</font></td>
|
| 264 |
|
|
<td><font size="-5">RANGE_RD</font></td>
|
| 265 |
|
|
<td><font size="-5">ADDR1_WR</font></td>
|
| 266 |
|
|
<td><font size="-5">ADDR1_RD</font></td>
|
| 267 |
|
|
<td><font size="-5">ADDR0_WR</font></td>
|
| 268 |
|
|
<td><font size="-5">ADDR0_RD</font></td>
|
| 269 |
|
|
</tr>
|
| 270 |
|
|
<tr align="center">
|
| 271 |
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<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK3_ADDR0</a></small></td>
|
| 272 |
|
|
<td><small>0x16</small></td>
|
| 273 |
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
|
| 274 |
|
|
</tr>
|
| 275 |
|
|
<tr align="center">
|
| 276 |
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<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK3_ADDR1</a></small></td>
|
| 277 |
|
|
<td><small>0x17</small></td>
|
| 278 |
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
|
| 279 |
|
|
</tr>
|
| 280 |
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</tbody></table>
|
| 281 |
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|
| 282 |
|
|
<a name="2.2 CPU Control/Status Registers"></a>
|
| 283 |
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 284 |
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<h2>2.2 CPU Control/Status Registers</h2>
|
| 285 |
|
|
|
| 286 |
|
|
<a name="2.2.1 CPU_ID"></a>
|
| 287 |
|
|
<h3>2.2.1 CPU_ID</h3>
|
| 288 |
74 |
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This 32 bit read-only register holds the program and data memory size information of the implemented openMSP430.
|
| 289 |
135 |
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<br><br>
|
| 290 |
50 |
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<table border="1">
|
| 291 |
135 |
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<tbody><tr align="center">
|
| 292 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 293 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 294 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 295 |
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</tr>
|
| 296 |
|
|
<tr align="center">
|
| 297 |
135 |
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<td><small>15</small></td><td><small>14</small></td>
|
| 298 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 299 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 300 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 301 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 302 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 303 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 304 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 305 |
50 |
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</tr>
|
| 306 |
|
|
<tr align="center">
|
| 307 |
135 |
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<td><small>CPU_ID_LO</small></td>
|
| 308 |
|
|
<td><small>0x00</small></td>
|
| 309 |
116 |
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<td colspan="7"><font size="-5">PER_SPACE</font></td>
|
| 310 |
|
|
<td colspan="5"><font size="-5">USER_VERSION</font></td>
|
| 311 |
|
|
<td colspan="1"><font size="-5">ASIC</font></td>
|
| 312 |
|
|
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
|
| 313 |
50 |
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</tr>
|
| 314 |
|
|
<tr align="center">
|
| 315 |
135 |
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<td><small>CPU_ID_HI</small></td>
|
| 316 |
|
|
<td><small>0x01</small></td>
|
| 317 |
116 |
olivier.gi |
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
|
| 318 |
|
|
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
|
| 319 |
|
|
<td colspan="1"><font size="-5">MPY</font></td>
|
| 320 |
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</tr>
|
| 321 |
135 |
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</tbody></table>
|
| 322 |
|
|
<br>
|
| 323 |
50 |
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<table border="0">
|
| 324 |
135 |
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<tbody><tr>
|
| 325 |
116 |
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<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td>
|
| 326 |
135 |
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<td>: Current CPU version<br>
|
| 327 |
|
|
</td>
|
| 328 |
50 |
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</tr>
|
| 329 |
|
|
<tr>
|
| 330 |
116 |
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<td> </td><td valign="top"><li><b>ASIC</b></li></td>
|
| 331 |
|
|
<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
|
| 332 |
50 |
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</tr>
|
| 333 |
116 |
olivier.gi |
<tr>
|
| 334 |
|
|
<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td>
|
| 335 |
|
|
<td>: Reflects the value defined in the <b>openMSP430_defines.v</b> file.</td>
|
| 336 |
|
|
</tr>
|
| 337 |
|
|
<tr>
|
| 338 |
|
|
<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td>
|
| 339 |
|
|
<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
|
| 340 |
|
|
</tr>
|
| 341 |
|
|
<tr>
|
| 342 |
|
|
<td> </td><td valign="top"><li><b>MPY</b></li></td>
|
| 343 |
|
|
<td>: This bit is set if the hardware multiplier is included in the current implementation</td>
|
| 344 |
|
|
</tr>
|
| 345 |
|
|
<tr>
|
| 346 |
|
|
<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
|
| 347 |
|
|
<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
|
| 348 |
|
|
</tr>
|
| 349 |
|
|
<tr>
|
| 350 |
|
|
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
|
| 351 |
|
|
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
|
| 352 |
|
|
</tr>
|
| 353 |
135 |
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</tbody></table>
|
| 354 |
50 |
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|
| 355 |
|
|
<a name="2.2.2 CPU_CTL"></a>
|
| 356 |
135 |
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<h3>2.2.2 CPU_CTL</h3> This 8 bit read-write register is used to
|
| 357 |
|
|
control the CPU and to configure some basic debug features. After a
|
| 358 |
|
|
POR, this register is set to 0x10 or 0x30 (depending on the <span style="font-weight: bold;">DBG_RST_BRK_EN</span> configuration option).
|
| 359 |
|
|
<br><br>
|
| 360 |
50 |
olivier.gi |
<table border="1">
|
| 361 |
135 |
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<tbody><tr align="center">
|
| 362 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 363 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 364 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 365 |
50 |
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</tr>
|
| 366 |
|
|
<tr align="center">
|
| 367 |
135 |
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<td><small> 7</small></td><td><small> 6</small></td>
|
| 368 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 369 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 370 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 371 |
50 |
olivier.gi |
</tr>
|
| 372 |
|
|
<tr align="center">
|
| 373 |
135 |
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<td><small>CPU_CTL</small></td>
|
| 374 |
|
|
<td><small>0x02</small></td>
|
| 375 |
50 |
olivier.gi |
<td><font size="-5">Res.</font></td>
|
| 376 |
|
|
<td><font size="-5">CPU_RST</font></td>
|
| 377 |
|
|
<td><font size="-5">RST_BRK_EN</font></td>
|
| 378 |
|
|
<td><font size="-5">FRZ_BRK_EN</font></td>
|
| 379 |
|
|
<td><font size="-5">SW_BRK_EN</font></td>
|
| 380 |
|
|
<td><font size="-5">ISTEP</font></td>
|
| 381 |
|
|
<td><font size="-5">RUN</font></td>
|
| 382 |
|
|
<td><font size="-5">HALT</font></td>
|
| 383 |
|
|
</tr>
|
| 384 |
135 |
olivier.gi |
</tbody></table>
|
| 385 |
|
|
<br>
|
| 386 |
50 |
olivier.gi |
<table border="0">
|
| 387 |
135 |
olivier.gi |
<tbody><tr>
|
| 388 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>CPU_RST</b></li></td>
|
| 389 |
|
|
<td>: Setting this bit to 1 will activate the PUC reset. Setting it back to 0 will release it.</td>
|
| 390 |
|
|
</tr>
|
| 391 |
|
|
<tr>
|
| 392 |
|
|
<td> </td><td valign="top"><li><b>RST_BRK_EN</b></li></td>
|
| 393 |
|
|
<td>: If set to 1, the CPU will automatically break after a PUC occurrence.</td>
|
| 394 |
|
|
</tr>
|
| 395 |
|
|
<tr>
|
| 396 |
|
|
<td> </td><td valign="top"><li><b>FRZ_BRK_EN</b></li></td>
|
| 397 |
|
|
<td>: If set to 1, the timers and watchdog are frozen when the CPU is halted.</td>
|
| 398 |
|
|
</tr>
|
| 399 |
|
|
<tr>
|
| 400 |
|
|
<td> </td><td valign="top"><li><b>SW_BRK_EN</b></li></td>
|
| 401 |
|
|
<td>: Enables the software breakpoint detection.</td>
|
| 402 |
|
|
</tr>
|
| 403 |
|
|
<tr>
|
| 404 |
|
|
<td> </td><td valign="top"><li><b>ISTEP</b><sup>1</sup></li></td>
|
| 405 |
|
|
<td>: Writing 1 to this bit will perform a single instruction step if the CPU is halted.</td>
|
| 406 |
|
|
</tr>
|
| 407 |
|
|
<tr>
|
| 408 |
|
|
<td> </td><td valign="top"><li><b>RUN</b><sup>1</sup></li></td>
|
| 409 |
|
|
<td>: Writing 1 to this bit will get the CPU out of halt state.</td>
|
| 410 |
|
|
</tr>
|
| 411 |
|
|
<tr>
|
| 412 |
|
|
<td> </td><td valign="top"><li><b>HALT</b><sup>1</sup></li></td>
|
| 413 |
|
|
<td>: Writing 1 to this bit will put the CPU in halt state.</td>
|
| 414 |
|
|
</tr>
|
| 415 |
135 |
olivier.gi |
</tbody></table>
|
| 416 |
|
|
<br><sup>1</sup>:this field is write-only and always reads back 0.
|
| 417 |
|
|
<br>
|
| 418 |
50 |
olivier.gi |
<a name="2.2.3 CPU_STAT"></a>
|
| 419 |
|
|
<h3>2.2.3 CPU_STAT</h3>
|
| 420 |
|
|
|
| 421 |
|
|
This 8 bit read-write register gives the global status of the debug interface. After a POR, this register is set to 0x00.
|
| 422 |
135 |
olivier.gi |
<br><br>
|
| 423 |
50 |
olivier.gi |
<table border="1">
|
| 424 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 425 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 426 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 427 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 428 |
50 |
olivier.gi |
</tr>
|
| 429 |
|
|
<tr align="center">
|
| 430 |
135 |
olivier.gi |
<td><small> 7</small></td><td><small> 6</small></td>
|
| 431 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 432 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 433 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 434 |
50 |
olivier.gi |
</tr>
|
| 435 |
|
|
<tr align="center">
|
| 436 |
135 |
olivier.gi |
<td><small>CPU_STAT</small></td>
|
| 437 |
|
|
<td><small>0x03</small></td>
|
| 438 |
50 |
olivier.gi |
<td><font size="-5">HWBRK3_PND</font></td>
|
| 439 |
|
|
<td><font size="-5">HWBRK2_PND</font></td>
|
| 440 |
|
|
<td><font size="-5">HWBRK1_PND</font></td>
|
| 441 |
|
|
<td><font size="-5">HWBRK0_PND</font></td>
|
| 442 |
|
|
<td><font size="-5">SWBRK_PND</font></td>
|
| 443 |
|
|
<td><font size="-5">PUC_PND</font></td>
|
| 444 |
|
|
<td><font size="-5">Res.</font></td>
|
| 445 |
|
|
<td><font size="-5">HALT_RUN</font></td>
|
| 446 |
|
|
</tr>
|
| 447 |
135 |
olivier.gi |
</tbody></table>
|
| 448 |
|
|
<br>
|
| 449 |
50 |
olivier.gi |
<table border="0">
|
| 450 |
135 |
olivier.gi |
<tbody><tr>
|
| 451 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>HWBRK3_PND</b></li></td>
|
| 452 |
135 |
olivier.gi |
<td>: This bit reflects if one of the Hardware Breakpoint Unit 3 status bit is set (i.e. BRK3_STAT≠0).</td>
|
| 453 |
50 |
olivier.gi |
</tr>
|
| 454 |
|
|
<tr>
|
| 455 |
|
|
<td> </td><td valign="top"><li><b>HWBRK2_PND</b></li></td>
|
| 456 |
135 |
olivier.gi |
<td>: This bit reflects if one of the Hardware Breakpoint Unit 2 status bit is set (i.e. BRK2_STAT≠0).</td>
|
| 457 |
50 |
olivier.gi |
</tr>
|
| 458 |
|
|
<tr>
|
| 459 |
|
|
<td> </td><td valign="top"><li><b>HWBRK1_PND</b></li></td>
|
| 460 |
135 |
olivier.gi |
<td>: This bit reflects if one of the Hardware Breakpoint Unit 1 status bit is set (i.e. BRK1_STAT≠0).</td>
|
| 461 |
50 |
olivier.gi |
</tr>
|
| 462 |
|
|
<tr>
|
| 463 |
|
|
<td> </td><td valign="top"><li><b>HWBRK0_PND</b></li></td>
|
| 464 |
135 |
olivier.gi |
<td>: This bit reflects if one of the Hardware Breakpoint Unit 0 status bit is set (i.e. BRK0_STAT≠0).</td>
|
| 465 |
50 |
olivier.gi |
</tr>
|
| 466 |
|
|
<tr>
|
| 467 |
|
|
<td> </td><td valign="top"><li><b>SWBRK_PND</b></li></td>
|
| 468 |
|
|
<td>: This bit is set to 1 when a software breakpoint occurred. It can be cleared by writing 1 to it.</td>
|
| 469 |
|
|
</tr>
|
| 470 |
|
|
<tr>
|
| 471 |
|
|
<td> </td><td valign="top"><li><b>PUC_PND</b></li></td>
|
| 472 |
|
|
<td>: This bit is set to 1 when a PUC reset occured. It can be cleared by writing 1 to it.</td>
|
| 473 |
|
|
</tr>
|
| 474 |
|
|
<tr>
|
| 475 |
|
|
<td> </td><td valign="top"><li><b>HALT_RUN</b></li></td>
|
| 476 |
|
|
<td>: This read-only bit gives the current status of the CPU:
|
| 477 |
|
|
</td>
|
| 478 |
|
|
</tr>
|
| 479 |
|
|
<tr>
|
| 480 |
|
|
<td> </td><td> </td>
|
| 481 |
|
|
<td> 0 - CPU is running.
|
| 482 |
135 |
olivier.gi |
<br> 1 - CPU is stopped.
|
| 483 |
50 |
olivier.gi |
</td>
|
| 484 |
|
|
</tr>
|
| 485 |
135 |
olivier.gi |
</tbody></table>
|
| 486 |
50 |
olivier.gi |
|
| 487 |
|
|
<a name="2.3 Memory Access Registers"></a>
|
| 488 |
135 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 489 |
50 |
olivier.gi |
<h2>2.3 Memory Access Registers</h2>
|
| 490 |
|
|
|
| 491 |
|
|
The following four registers enable single and burst read/write access to both CPU-Registers and full memory address range.
|
| 492 |
135 |
olivier.gi |
<br>In order to perform an access, the following sequences are typically done:
|
| 493 |
50 |
olivier.gi |
<ul>
|
| 494 |
|
|
<li>single read access (MEM_CNT=0):</li>
|
| 495 |
|
|
<ol>
|
| 496 |
|
|
<li>set MEM_ADDR with the memory address (or register number) to be read</li>
|
| 497 |
|
|
<li>set MEM_CTL (in particular RD/WR=0 and START=1)</li>
|
| 498 |
|
|
<li>read MEM_DATA</li>
|
| 499 |
|
|
</ol>
|
| 500 |
|
|
<li>single write access (MEM_CNT=0):</li>
|
| 501 |
|
|
<ol>
|
| 502 |
|
|
<li>set MEM_ADDR with the memory address (or register number) to be written</li>
|
| 503 |
|
|
<li>set MEM_DATA with the data to be written</li>
|
| 504 |
|
|
<li>set MEM_CTL (in particular RD/WR=1 and START=1)</li>
|
| 505 |
|
|
</ol>
|
| 506 |
135 |
olivier.gi |
<li>burst read/write access (MEM_CNT≠0):</li>
|
| 507 |
50 |
olivier.gi |
<ul>
|
| 508 |
|
|
<li>burst access are optimized for the communication interface used (i.e. for the UART).
|
| 509 |
135 |
olivier.gi |
The burst sequence are therefore described in the corresponding section (<a href="#3.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">3.4 Read/Write burst implementation for the CPU Memory access</a>)</li>
|
| 510 |
50 |
olivier.gi |
</ul>
|
| 511 |
|
|
</ul>
|
| 512 |
|
|
<a name="2.3.1 MEM_CTL"></a>
|
| 513 |
135 |
olivier.gi |
<h3>2.3.1 MEM_CTL</h3>This 8 bit read-write register is used to control
|
| 514 |
|
|
the Memory and CPU-Register read/write access. After a POR, this
|
| 515 |
|
|
register is set to 0x00.
|
| 516 |
|
|
<br><br>
|
| 517 |
50 |
olivier.gi |
<table border="1">
|
| 518 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 519 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 520 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 521 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 522 |
50 |
olivier.gi |
</tr>
|
| 523 |
|
|
<tr align="center">
|
| 524 |
135 |
olivier.gi |
<td><small> 7</small></td><td><small> 6</small></td>
|
| 525 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 526 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 527 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 528 |
50 |
olivier.gi |
</tr>
|
| 529 |
|
|
<tr align="center">
|
| 530 |
135 |
olivier.gi |
<td><small>MEM_CTL</small></td>
|
| 531 |
|
|
<td><small>0x04</small></td>
|
| 532 |
50 |
olivier.gi |
<td colspan="4"><font size="-5">Reserved</font></td>
|
| 533 |
|
|
<td><font size="-5">B/W</font></td>
|
| 534 |
|
|
<td><font size="-5">MEM/REG</font></td>
|
| 535 |
|
|
<td><font size="-5">RD/WR</font></td>
|
| 536 |
|
|
<td><font size="-5">START</font></td>
|
| 537 |
|
|
</tr>
|
| 538 |
135 |
olivier.gi |
</tbody></table>
|
| 539 |
|
|
<br>
|
| 540 |
50 |
olivier.gi |
<table border="0">
|
| 541 |
135 |
olivier.gi |
<tbody><tr>
|
| 542 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>B/W</b></li></td>
|
| 543 |
|
|
<td>: 0 - 16 bit access.</td>
|
| 544 |
|
|
</tr>
|
| 545 |
|
|
<tr>
|
| 546 |
|
|
<td> </td><td> </td>
|
| 547 |
|
|
<td> 1 - 8 bit access (not valid for CPU-Registers).</td>
|
| 548 |
|
|
</tr>
|
| 549 |
|
|
<tr>
|
| 550 |
|
|
<td> </td><td valign="top"><li><b>MEM/REG</b></li></td>
|
| 551 |
|
|
<td>: 0 - Memory access.</td>
|
| 552 |
|
|
</tr>
|
| 553 |
|
|
<tr>
|
| 554 |
|
|
<td> </td><td> </td>
|
| 555 |
|
|
<td> 1 - CPU-Register access.</td>
|
| 556 |
|
|
</tr>
|
| 557 |
|
|
<tr>
|
| 558 |
|
|
<td> </td><td valign="top"><li><b>RD/WR</b></li></td>
|
| 559 |
|
|
<td>: 0 - Read access.</td>
|
| 560 |
|
|
</tr>
|
| 561 |
|
|
<tr>
|
| 562 |
|
|
<td> </td><td> </td>
|
| 563 |
|
|
<td> 1 - Write access.</td>
|
| 564 |
|
|
</tr>
|
| 565 |
|
|
<tr>
|
| 566 |
|
|
<td> </td><td valign="top"><li><b>START</b></li></td>
|
| 567 |
|
|
<td>: 0- Do nothing</td>
|
| 568 |
|
|
</tr>
|
| 569 |
|
|
<tr>
|
| 570 |
|
|
<td> </td><td> </td>
|
| 571 |
|
|
<td> 1 - Initiate memory transfer.</td>
|
| 572 |
|
|
</tr>
|
| 573 |
135 |
olivier.gi |
</tbody></table>
|
| 574 |
50 |
olivier.gi |
|
| 575 |
|
|
<a name="2.3.2 MEM_ADDR"></a>
|
| 576 |
135 |
olivier.gi |
<h3>2.3.2 MEM_ADDR</h3>This 16 bit read-write register specifies the
|
| 577 |
|
|
Memory or CPU-Register address to be used for the next read/write
|
| 578 |
|
|
transfer. After a POR, this register is set to 0x0000.
|
| 579 |
|
|
<br>
|
| 580 |
|
|
<strong>Note:</strong> in case of burst (i.e. MEM_CNT≠0), this register
|
| 581 |
|
|
specifies the first address of the burst transfer and will be
|
| 582 |
|
|
incremented automatically as the burst goes (by 1 for 8-bit access and
|
| 583 |
|
|
by 2 for 16-bit access).
|
| 584 |
|
|
<br><br>
|
| 585 |
50 |
olivier.gi |
<table border="1">
|
| 586 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 587 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 588 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 589 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 590 |
50 |
olivier.gi |
</tr>
|
| 591 |
|
|
<tr align="center">
|
| 592 |
135 |
olivier.gi |
<td><small>15</small></td><td><small>14</small></td>
|
| 593 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 594 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 595 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 596 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 597 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 598 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 599 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 600 |
50 |
olivier.gi |
</tr>
|
| 601 |
|
|
<tr align="center">
|
| 602 |
135 |
olivier.gi |
<td><small>MEM_ADDR</small></td>
|
| 603 |
|
|
<td><small>0x05</small></td>
|
| 604 |
50 |
olivier.gi |
<td colspan="16"><font size="-5">MEM_ADDR[15:0]</font></td>
|
| 605 |
|
|
</tr>
|
| 606 |
135 |
olivier.gi |
</tbody></table>
|
| 607 |
|
|
<br>
|
| 608 |
50 |
olivier.gi |
<table border="0">
|
| 609 |
135 |
olivier.gi |
<tbody><tr>
|
| 610 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>MEM_ADDR</b></li></td>
|
| 611 |
|
|
<td>: Memory or CPU-Register address to be used for the next read/write transfer.</td>
|
| 612 |
|
|
</tr>
|
| 613 |
135 |
olivier.gi |
</tbody></table>
|
| 614 |
50 |
olivier.gi |
|
| 615 |
|
|
<a name="2.3.3 MEM_DATA"></a>
|
| 616 |
135 |
olivier.gi |
<h3>2.3.3 MEM_DATA</h3>This 16 bit read-write register gives (wr)
|
| 617 |
|
|
or receive (rd) the Memory or CPU-Register data for the next
|
| 618 |
|
|
transfer. After a POR, this register is set to 0x0000.
|
| 619 |
|
|
<br><br>
|
| 620 |
50 |
olivier.gi |
<table border="1">
|
| 621 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 622 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 623 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 624 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 625 |
50 |
olivier.gi |
</tr>
|
| 626 |
|
|
<tr align="center">
|
| 627 |
135 |
olivier.gi |
<td><small>15</small></td><td><small>14</small></td>
|
| 628 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 629 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 630 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 631 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 632 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 633 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 634 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 635 |
50 |
olivier.gi |
</tr>
|
| 636 |
|
|
<tr align="center">
|
| 637 |
135 |
olivier.gi |
<td><small>MEM_DATA</small></td>
|
| 638 |
|
|
<td><small>0x06</small></td>
|
| 639 |
50 |
olivier.gi |
<td colspan="16"><font size="-5">MEM_DATA[15:0]</font></td>
|
| 640 |
|
|
</tr>
|
| 641 |
135 |
olivier.gi |
</tbody></table>
|
| 642 |
|
|
<br>
|
| 643 |
50 |
olivier.gi |
<table border="0">
|
| 644 |
135 |
olivier.gi |
<tbody><tr>
|
| 645 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>MEM_DATA</b></li></td>
|
| 646 |
|
|
<td>: if MEM_CTL.WR - data to be written during the next write transfer.</td>
|
| 647 |
|
|
</tr>
|
| 648 |
|
|
<tr>
|
| 649 |
|
|
<td> </td><td> </td>
|
| 650 |
|
|
<td> if MEM_CTL.RD - updated with the data from the read transfer</td>
|
| 651 |
|
|
</tr>
|
| 652 |
135 |
olivier.gi |
</tbody></table>
|
| 653 |
50 |
olivier.gi |
|
| 654 |
|
|
<a name="2.3.4 MEM_CNT"></a>
|
| 655 |
135 |
olivier.gi |
<h3>2.3.4 MEM_CNT</h3>This 16 bit read-write register controls the
|
| 656 |
|
|
burst access to the Memory or CPU-Registers. If set to 0, a single
|
| 657 |
|
|
access will occur, otherwise, a burst will be performed. The burst
|
| 658 |
|
|
being optimized for the communication interface, more details are given
|
| 659 |
|
|
<a href="#3.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">there</a>. After a POR, this register is set to 0x0000.
|
| 660 |
|
|
<br><br>
|
| 661 |
50 |
olivier.gi |
<table border="1">
|
| 662 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 663 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 664 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 665 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 666 |
50 |
olivier.gi |
</tr>
|
| 667 |
|
|
<tr align="center">
|
| 668 |
135 |
olivier.gi |
<td><small>15</small></td><td><small>14</small></td>
|
| 669 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 670 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 671 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 672 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 673 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 674 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 675 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 676 |
50 |
olivier.gi |
</tr>
|
| 677 |
|
|
<tr align="center">
|
| 678 |
135 |
olivier.gi |
<td><small>MEM_CNT</small></td>
|
| 679 |
|
|
<td><small>0x07</small></td>
|
| 680 |
50 |
olivier.gi |
<td colspan="16"><font size="-5">MEM_CNT[15:0]</font></td>
|
| 681 |
|
|
</tr>
|
| 682 |
135 |
olivier.gi |
</tbody></table>
|
| 683 |
|
|
<br>
|
| 684 |
50 |
olivier.gi |
<table border="0">
|
| 685 |
135 |
olivier.gi |
<tbody><tr>
|
| 686 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>MEM_CNT</b></li></td>
|
| 687 |
|
|
<td>: =0 - a single access will be performed with the next transfer.</td>
|
| 688 |
|
|
</tr>
|
| 689 |
|
|
<tr>
|
| 690 |
|
|
<td> </td><td> </td>
|
| 691 |
135 |
olivier.gi |
<td> ≠0 -
|
| 692 |
|
|
specifies the burst size for the next transfer (i.e number of data
|
| 693 |
|
|
access). This field will be automatically decremented as the burst goes.</td>
|
| 694 |
50 |
olivier.gi |
</tr>
|
| 695 |
135 |
olivier.gi |
</tbody></table>
|
| 696 |
50 |
olivier.gi |
|
| 697 |
|
|
<a name="2.4 Hardware Breakpoint Unit Registers"></a>
|
| 698 |
135 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 699 |
50 |
olivier.gi |
<h2>2.4 Hardware Breakpoint Unit Registers</h2>
|
| 700 |
135 |
olivier.gi |
Depending on the <a href="http://opencores.org/project,openmsp430,core#2.1.3%20Configuration">defines</a>
|
| 701 |
|
|
located in the "openmsp430_defines.v" file, up to four hardware
|
| 702 |
|
|
breakpoint units can be included in the design. These units can be
|
| 703 |
|
|
individually controlled with the following registers.
|
| 704 |
50 |
olivier.gi |
<a name="2.4.1 BRKx_CTL"></a>
|
| 705 |
|
|
<h3>2.4.1 BRKx_CTL</h3>
|
| 706 |
|
|
|
| 707 |
|
|
This 8 bit read-write register controls the hardware breakpoint unit x. After a POR, this register is set to 0x00.
|
| 708 |
135 |
olivier.gi |
<br><br>
|
| 709 |
50 |
olivier.gi |
<table border="1">
|
| 710 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 711 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 712 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 713 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 714 |
50 |
olivier.gi |
</tr>
|
| 715 |
|
|
<tr align="center">
|
| 716 |
135 |
olivier.gi |
<td><small> 7</small></td><td><small> 6</small></td>
|
| 717 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 718 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 719 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 720 |
50 |
olivier.gi |
</tr>
|
| 721 |
|
|
<tr align="center">
|
| 722 |
135 |
olivier.gi |
<td><small>BRKx_CTL</small></td>
|
| 723 |
|
|
<td><small>0x08, 0x0C, 0x10, 0x14</small></td>
|
| 724 |
50 |
olivier.gi |
<td colspan="3"><font size="-5">Reserved</font></td>
|
| 725 |
|
|
<td><font size="-5">RANGE_MODE</font></td>
|
| 726 |
|
|
<td><font size="-5">INST_EN</font></td>
|
| 727 |
|
|
<td><font size="-5">BREAK_EN</font></td>
|
| 728 |
|
|
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
|
| 729 |
|
|
</tr>
|
| 730 |
135 |
olivier.gi |
</tbody></table>
|
| 731 |
|
|
<br>
|
| 732 |
50 |
olivier.gi |
<table border="0">
|
| 733 |
135 |
olivier.gi |
<tbody><tr>
|
| 734 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>RANGE_MODE</b></li></td>
|
| 735 |
|
|
<td>: 0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
|
| 736 |
|
|
</tr>
|
| 737 |
|
|
<tr>
|
| 738 |
|
|
<td> </td><td> </td>
|
| 739 |
135 |
olivier.gi |
<td> 1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode)
|
| 740 |
|
|
<br><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
|
| 741 |
|
|
|
| 742 |
50 |
olivier.gi |
</tr>
|
| 743 |
|
|
<tr>
|
| 744 |
|
|
<td> </td><td valign="top"><li><b>INST_EN</b></li></td>
|
| 745 |
|
|
<td>: 0 - Checks are done on the execution unit (data flow).</td>
|
| 746 |
|
|
</tr>
|
| 747 |
|
|
<tr>
|
| 748 |
|
|
<td> </td><td> </td>
|
| 749 |
|
|
<td> 1 - Checks are done on the frontend (instruction flow).</td>
|
| 750 |
|
|
</tr>
|
| 751 |
|
|
|
| 752 |
|
|
<tr>
|
| 753 |
|
|
<td> </td><td valign="top"><li><b>BREAK_EN</b></li></td>
|
| 754 |
|
|
<td>: 0 - Watchpoint mode enable (don't stop on address match).</td>
|
| 755 |
|
|
</tr>
|
| 756 |
|
|
<tr>
|
| 757 |
|
|
<td> </td><td> </td>
|
| 758 |
|
|
<td> 1 - Breakpoint mode enable (stop on address match).</td>
|
| 759 |
|
|
</tr>
|
| 760 |
|
|
|
| 761 |
|
|
<tr>
|
| 762 |
|
|
<td> </td><td valign="top"><li><b>ACCESS_MODE</b></li></td>
|
| 763 |
|
|
<td>: 00 - Disabled</td>
|
| 764 |
|
|
</tr>
|
| 765 |
|
|
<tr>
|
| 766 |
|
|
<td> </td><td> </td>
|
| 767 |
|
|
<td> 01 - Detect read access.
|
| 768 |
135 |
olivier.gi |
<br> 10 - Detect write access.
|
| 769 |
|
|
<br> 11 - Detect read/write access
|
| 770 |
|
|
<br><b>Note</b>: '10' & '11' modes are not supported on the instruction flow</td>
|
| 771 |
50 |
olivier.gi |
</tr>
|
| 772 |
135 |
olivier.gi |
</tbody></table>
|
| 773 |
50 |
olivier.gi |
|
| 774 |
|
|
<a name="2.4.2 BRKx_STAT"></a>
|
| 775 |
135 |
olivier.gi |
<h3>2.4.2 BRKx_STAT</h3>This 8 bit read-write register gives the status
|
| 776 |
|
|
of the hardware breakpoint unit x. Each status bit can be cleared by
|
| 777 |
|
|
writing 1 to it. After a POR, this register is set to 0x00.
|
| 778 |
|
|
<br><br>
|
| 779 |
50 |
olivier.gi |
<table border="1">
|
| 780 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 781 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 782 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 783 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 784 |
50 |
olivier.gi |
</tr>
|
| 785 |
|
|
<tr align="center">
|
| 786 |
135 |
olivier.gi |
<td><small> 7</small></td><td><small> 6</small></td>
|
| 787 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 788 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 789 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 790 |
50 |
olivier.gi |
</tr>
|
| 791 |
|
|
<tr align="center">
|
| 792 |
135 |
olivier.gi |
<td><small>BRKx_STAT</small></td>
|
| 793 |
|
|
<td><small>0x09, 0x0D, 0x11, 0x15</small></td>
|
| 794 |
50 |
olivier.gi |
<td colspan="2"><font size="-5">Reserved</font></td>
|
| 795 |
|
|
<td><font size="-5">RANGE_WR</font></td>
|
| 796 |
|
|
<td><font size="-5">RANGE_RD</font></td>
|
| 797 |
|
|
<td><font size="-5">ADDR1_WR</font></td>
|
| 798 |
|
|
<td><font size="-5">ADDR1_RD</font></td>
|
| 799 |
|
|
<td><font size="-5">ADDR0_WR</font></td>
|
| 800 |
|
|
<td><font size="-5">ADDR0_RD</font></td>
|
| 801 |
|
|
</tr>
|
| 802 |
135 |
olivier.gi |
</tbody></table>
|
| 803 |
|
|
<br>
|
| 804 |
50 |
olivier.gi |
<table border="0">
|
| 805 |
135 |
olivier.gi |
<tbody><tr>
|
| 806 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>RANGE_WR</b></li></td>
|
| 807 |
135 |
olivier.gi |
<td>:
|
| 808 |
|
|
This bit is set whenever the CPU performs a write access within the
|
| 809 |
|
|
BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and
|
| 810 |
|
|
ACCESS_MODE[1]=1).</td>
|
| 811 |
50 |
olivier.gi |
</tr>
|
| 812 |
|
|
<tr>
|
| 813 |
|
|
<td> </td><td valign="top"><li><b>RANGE_RD</b></li></td>
|
| 814 |
135 |
olivier.gi |
<td>:
|
| 815 |
|
|
This bit is set whenever the CPU performs a read access within the
|
| 816 |
|
|
BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and
|
| 817 |
|
|
ACCESS_MODE[0]=1). <br><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
|
| 818 |
50 |
olivier.gi |
</tr>
|
| 819 |
|
|
<tr>
|
| 820 |
|
|
<td> </td><td valign="top"><li><b>ADDR1_WR</b></li></td>
|
| 821 |
135 |
olivier.gi |
<td>:
|
| 822 |
|
|
This bit is set whenever the CPU performs a write access at the
|
| 823 |
|
|
BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
|
| 824 |
50 |
olivier.gi |
</tr>
|
| 825 |
|
|
<tr>
|
| 826 |
|
|
<td> </td><td valign="top"><li><b>ADDR1_RD</b></li></td>
|
| 827 |
135 |
olivier.gi |
<td>:
|
| 828 |
|
|
This bit is set whenever the CPU performs a read access at the
|
| 829 |
|
|
BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).</td>
|
| 830 |
50 |
olivier.gi |
</tr>
|
| 831 |
|
|
<tr>
|
| 832 |
|
|
<td> </td><td valign="top"><li><b>ADDR0_WR</b></li></td>
|
| 833 |
135 |
olivier.gi |
<td>:
|
| 834 |
|
|
This bit is set whenever the CPU performs a write access at the
|
| 835 |
|
|
BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
|
| 836 |
50 |
olivier.gi |
</tr>
|
| 837 |
|
|
<tr>
|
| 838 |
|
|
<td> </td><td valign="top"><li><b>ADDR0_RD</b></li></td>
|
| 839 |
135 |
olivier.gi |
<td>:
|
| 840 |
|
|
This bit is set whenever the CPU performs a read access at the
|
| 841 |
|
|
BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).</td>
|
| 842 |
50 |
olivier.gi |
</tr>
|
| 843 |
135 |
olivier.gi |
</tbody></table>
|
| 844 |
50 |
olivier.gi |
|
| 845 |
|
|
<a name="2.4.3 BRKx_ADDR0"></a>
|
| 846 |
|
|
<h3>2.4.3 BRKx_ADDR0</h3>
|
| 847 |
135 |
olivier.gi |
This 16 bit read-write register holds the value which is compared
|
| 848 |
|
|
against the address value currently present on the program or data
|
| 849 |
|
|
address bus. After a POR, this register is set to 0x0000.
|
| 850 |
|
|
<br><br>
|
| 851 |
50 |
olivier.gi |
<table border="1">
|
| 852 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 853 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 854 |
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
| 855 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 856 |
50 |
olivier.gi |
</tr>
|
| 857 |
|
|
<tr align="center">
|
| 858 |
135 |
olivier.gi |
<td><small>15</small></td><td><small>14</small></td>
|
| 859 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 860 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 861 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 862 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 863 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 864 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 865 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 866 |
50 |
olivier.gi |
</tr>
|
| 867 |
|
|
<tr align="center">
|
| 868 |
135 |
olivier.gi |
<td><small>BRKx_ADDR0</small></td>
|
| 869 |
|
|
<td><small>0x0A, 0x0E, 0x12, 0x16</small></td>
|
| 870 |
50 |
olivier.gi |
<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
|
| 871 |
|
|
</tr>
|
| 872 |
135 |
olivier.gi |
</tbody></table>
|
| 873 |
|
|
<br>
|
| 874 |
50 |
olivier.gi |
<table border="0">
|
| 875 |
135 |
olivier.gi |
<tbody><tr>
|
| 876 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>BRK_ADDR0</b></li></td>
|
| 877 |
|
|
<td>: Value compared against the address value currently present on the program or data address bus.</td>
|
| 878 |
|
|
</tr>
|
| 879 |
135 |
olivier.gi |
</tbody></table>
|
| 880 |
50 |
olivier.gi |
|
| 881 |
|
|
<a name="2.4.4 BRKx_ADDR1"></a>
|
| 882 |
135 |
olivier.gi |
<h3>2.4.4 BRKx_ADDR1</h3>This 16 bit read-write register holds the
|
| 883 |
|
|
value which is compared against the address value currently present on
|
| 884 |
|
|
the program or data address bus. After a POR, this register is set to
|
| 885 |
|
|
0x0000.
|
| 886 |
|
|
<br><br>
|
| 887 |
50 |
olivier.gi |
<table border="1">
|
| 888 |
135 |
olivier.gi |
<tbody><tr align="center">
|
| 889 |
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
| 890 |
|
|
<td rowspan="2"><b><small>Addresses</small></b></td>
|
| 891 |
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
| 892 |
50 |
olivier.gi |
</tr>
|
| 893 |
|
|
<tr align="center">
|
| 894 |
135 |
olivier.gi |
<td><small>15</small></td><td><small>14</small></td>
|
| 895 |
|
|
<td><small>13</small></td><td><small>12</small></td>
|
| 896 |
|
|
<td><small>11</small></td><td><small>10</small></td>
|
| 897 |
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
| 898 |
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
| 899 |
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
| 900 |
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
| 901 |
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
| 902 |
50 |
olivier.gi |
</tr>
|
| 903 |
|
|
<tr align="center">
|
| 904 |
135 |
olivier.gi |
<td><small>BRKx_ADDR1</small></td>
|
| 905 |
|
|
<td><small>0x0B, 0x0F, 0x13, 0x17</small></td>
|
| 906 |
50 |
olivier.gi |
<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
|
| 907 |
|
|
</tr>
|
| 908 |
135 |
olivier.gi |
</tbody></table>
|
| 909 |
|
|
<br>
|
| 910 |
50 |
olivier.gi |
<table border="0">
|
| 911 |
135 |
olivier.gi |
<tbody><tr>
|
| 912 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>BRK_ADDR1</b></li></td>
|
| 913 |
|
|
<td>: Value compared against the address value currently present on the program or data address bus.</td>
|
| 914 |
|
|
</tr>
|
| 915 |
135 |
olivier.gi |
</tbody></table>
|
| 916 |
50 |
olivier.gi |
|
| 917 |
|
|
<a name="3. Debug Communication Interface: UART"></a>
|
| 918 |
135 |
olivier.gi |
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| 919 |
|
|
<h1>3. Debug Communication Interface: UART</h1>With its UART interface,
|
| 920 |
|
|
the openMSP430 debug unit can communicate with the host computer using
|
| 921 |
|
|
a simple RS232 cable (connected to the <a href="http://opencores.org/project,openmsp430,core#2.1.5%20Pinout">dbg_uart_txd</a> and <a href="http://opencores.org/project,openmsp430,core#2.1.5%20Pinout">dbg_uart_rxd</a> ports of the IP).<br>Typically, a <a href="http://www.google.com/search?q=usb+to+rs232+converter">USB to RS232</a> or <a href="http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm">USB to serial TTL</a>
|
| 922 |
|
|
cable will provide a reliable communication link between your host PC
|
| 923 |
|
|
and the openMSP430 (speed being typically limited by the cable length).
|
| 924 |
50 |
olivier.gi |
<a name="3.1 Serial communication protocol: 8N1"></a>
|
| 925 |
|
|
<h2>3.1 Serial communication protocol: 8N1</h2>
|
| 926 |
135 |
olivier.gi |
There are plenty tutorials on Internet regarding RS232 based protocols.
|
| 927 |
|
|
However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No
|
| 928 |
|
|
Parity, 1 Stop bit):<br>
|
| 929 |
|
|
<br>
|
| 930 |
|
|
<img src="usercontent,img,1247419201" alt="8N1 Serial Protocol" title="8N1 Serial Protocol">
|
| 931 |
|
|
<br>
|
| 932 |
|
|
As you can see in the above diagram, data transmission starts with a
|
| 933 |
|
|
Start bit, followed by the data bits (LSB sent first and MSB sent
|
| 934 |
|
|
last), and ends with a "Stop" bit.
|
| 935 |
50 |
olivier.gi |
<a name="3.2 Synchronization frame"></a>
|
| 936 |
135 |
olivier.gi |
<h2>3.2 Synchronization frame</h2>After a POR, the Serial Debug
|
| 937 |
|
|
Interface expects a synchronization frame from the host computer in
|
| 938 |
|
|
order to determine the communication speed (i.e. the baud rate).<br>
|
| 939 |
50 |
olivier.gi |
The synchronization frame looks as following:
|
| 940 |
135 |
olivier.gi |
<br>
|
| 941 |
|
|
<img src="usercontent,img,1247420610" alt="Debug Synchronization Frame" title="Debug Synchronization Frame">
|
| 942 |
|
|
<br>
|
| 943 |
|
|
As you can see, the host simply sends the 0x80 value. The openMSP430
|
| 944 |
|
|
will then measure the time between the falling and rising edge, divide
|
| 945 |
|
|
it by 8 and automatically deduce the baud rate it should use to
|
| 946 |
|
|
properly communicate with the host.
|
| 947 |
|
|
<br><br>
|
| 948 |
|
|
<b>Important note</b>: if you want to change the communication speed
|
| 949 |
|
|
between two debugging sessions, the Serial Debug Interface needs to go through a reset cycle (i.e. through the <span style="font-style: italic;">reset_n</span> or <span style="font-style: italic;">dbg_en</span> pins) and a new synchronization frame needs to be send.
|
| 950 |
|
|
<br>
|
| 951 |
50 |
olivier.gi |
<a name="3.3 Read/Write access to the debug registers"></a>
|
| 952 |
|
|
<h2>3.3 Read/Write access to the debug registers</h2>
|
| 953 |
135 |
olivier.gi |
In order to perform a read / write access to a debug register, the host needs to send a command frame to the openMSP430.<br>In
|
| 954 |
|
|
case of write access, this command frame will be followed by 1 or 2
|
| 955 |
|
|
data frames and in case of read access, the openMSP430 will send 1 or 2
|
| 956 |
|
|
data frames after receiving the command.
|
| 957 |
50 |
olivier.gi |
<a name="3.3.1 Command Frame"></a>
|
| 958 |
|
|
<h3>3.3.1 Command Frame</h3>
|
| 959 |
|
|
The command frame looks as following:
|
| 960 |
135 |
olivier.gi |
<br>
|
| 961 |
|
|
<img src="usercontent,img,1247427400" alt="Debug Command Frame" title="Debug Command Frame">
|
| 962 |
|
|
<br>
|
| 963 |
50 |
olivier.gi |
<table border="0">
|
| 964 |
135 |
olivier.gi |
<tbody><tr>
|
| 965 |
50 |
olivier.gi |
<td> </td><td valign="top"><li><b>WR</b></li></td>
|
| 966 |
|
|
<td>: Perform a Write access when set. Read otherwise.</td>
|
| 967 |
|
|
</tr>
|
| 968 |
|
|
<tr>
|
| 969 |
|
|
<td> </td><td valign="top"><li><b>B/W</b></li></td>
|
| 970 |
135 |
olivier.gi |
<td>: Perform a 8-bit data access when set (one data frame). 16-bit otherwise (two data frame).</td></tr><tr>
|
| 971 |
50 |
olivier.gi |
</tr>
|
| 972 |
|
|
<tr>
|
| 973 |
|
|
<td> </td><td valign="top"><li><b>Address</b></li></td>
|
| 974 |
135 |
olivier.gi |
<td>: Debug register address.</td></tr><tr>
|
| 975 |
50 |
olivier.gi |
</tr>
|
| 976 |
135 |
olivier.gi |
</tbody></table>
|
| 977 |
50 |
olivier.gi |
|
| 978 |
|
|
<a name="3.3.2 Write access"></a>
|
| 979 |
|
|
<h3>3.3.2 Write access</h3>
|
| 980 |
|
|
A write access transaction looks like this:
|
| 981 |
135 |
olivier.gi |
<br>
|
| 982 |
|
|
<img src="usercontent,img,1247428987" alt="Debug Write Transaction" title="Debug Write Transaction">
|
| 983 |
50 |
olivier.gi |
|
| 984 |
|
|
<a name="3.3.3 Read access"></a>
|
| 985 |
|
|
<h3>3.3.3 Read access</h3>
|
| 986 |
|
|
A read access transaction looks like this:
|
| 987 |
135 |
olivier.gi |
<br>
|
| 988 |
|
|
<img src="usercontent,img,1247429086" alt="Debug Read Transaction" title="Debug Read Transaction">
|
| 989 |
50 |
olivier.gi |
|
| 990 |
|
|
<a name="3.4 Read/Write burst implementation for the CPU Memory access"></a>
|
| 991 |
135 |
olivier.gi |
<h2>3.4 Read/Write burst implementation for the CPU Memory access</h2>In
|
| 992 |
|
|
order to optimize the data burst transactions for the UART, read/write
|
| 993 |
|
|
access are not done by reading or writing the MEM_DATA register.<br>
|
| 994 |
50 |
olivier.gi |
Instead, the data transfer starts immediately after the MEM_CTL.START bit has been set.
|
| 995 |
|
|
|
| 996 |
|
|
<a name="3.4.1 Write Burst access"></a>
|
| 997 |
|
|
<h3>3.4.1 Write Burst access</h3>
|
| 998 |
|
|
A write burst transaction looks like this:
|
| 999 |
135 |
olivier.gi |
<br>
|
| 1000 |
|
|
<img src="usercontent,img,1247430408" alt="Debug Write Burst Transaction" title="Debug Write Burst Transaction">
|
| 1001 |
50 |
olivier.gi |
|
| 1002 |
|
|
<a name="3.4.2 Read Burst access"></a>
|
| 1003 |
|
|
<h3>3.4.2 Read Burst access</h3>
|
| 1004 |
|
|
A read burst transaction looks like this:
|
| 1005 |
135 |
olivier.gi |
<br>
|
| 1006 |
|
|
<img src="usercontent,img,1247430449" alt="Debug Read Burst Transaction" title="Debug Read Burst Transaction">
|
| 1007 |
50 |
olivier.gi |
|
| 1008 |
135 |
olivier.gi |
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