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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html>
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<head>
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<title>openMSP430 Serial Debug Interface</title>
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</head>
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<body>
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<a name="TOC"></a>
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<h3>Table of content</h3>
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<ul>
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        <li><a href="#1. Introduction">                          1. Introduction</a></li>
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        <li><a href="#2. Debug Unit">                            2. Debug Unit</a>
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        <ul>
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      <li><a href="#2.1 Register Mapping">                  2.1 Register Mapping</a></li>
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      <li><a href="#2.2 CPU Control/Status Registers">      2.2 CPU Control/Status Registers</a></li>
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                <ul>
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           <li><a href="#2.2.1 CPU_ID">                       2.2.1 CPU_ID</a></li>
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        <li><a href="#2.2.2 CPU_CTL">                      2.2.2 CPU_CTL</a></li>
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        <li><a href="#2.2.3 CPU_STAT">                     2.2.3 CPU_STAT</a></li>
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                </ul>
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      <li><a href="#2.3 Memory Access Registers">           2.3 Memory Access Registers</a></li>
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                <ul>
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           <li><a href="#2.3.1 MEM_CTL">                      2.3.1 MEM_CTL</a></li>
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        <li><a href="#2.3.2 MEM_ADDR">                     2.3.2 MEM_ADDR</a></li>
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        <li><a href="#2.3.3 MEM_DATA">                     2.3.3 MEM_DATA</a></li>
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        <li><a href="#2.3.4 MEM_CNT">                      2.3.4 MEM_CNT</a></li>
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                </ul>
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      <li><a href="#2.4 Hardware Breakpoint Unit Registers">2.4 Hardware Breakpoint Unit Registers</a></li>
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                <ul>
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           <li><a href="#2.4.1 BRKx_CTL">                     2.4.1 BRKx_CTL</a></li>
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        <li><a href="#2.4.2 BRKx_STAT">                    2.4.2 BRKx_STAT</a></li>
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        <li><a href="#2.4.3 BRKx_ADDR0">                   2.4.3 BRKx_ADDR0</a></li>
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        <li><a href="#2.4.4 BRKx_ADDR1">                   2.4.4 BRKx_ADDR1</a></li>
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                </ul>
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        </ul>
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        </li>
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        <li><a href="#3. Debug Communication Interface: UART">   3. Debug Communication Interface: UART</a>
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                <ul>
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           <li><a href="#3.1 Serial communication protocol: 8N1">       3.1 Serial communication protocol: 8N1</a></li>
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        <li><a href="#3.2 Synchronization frame">                    3.2 Synchronization frame</a></li>
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        <li><a href="#3.3 Read/Write access to the debug registers"> 3.3 Read/Write access to the debug registers</a></li>
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                        <ul>
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                <li><a href="#3.3.1 Command Frame">                       3.3.1 Command Frame</a></li>
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                <li><a href="#3.3.2 Write access">                        3.3.2 Write access</a></li>
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                <li><a href="#3.3.3 Read access">                         3.3.3 Read access</a></li>
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                        </ul>
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        <li><a href="#3.4 Read/Write burst implementation for the CPU Memory access">3.4 Read/Write burst implementation for the CPU Memory access</a></li>
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                        <ul>
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                <li><a href="#3.4.1 Write Burst access">                  3.4.1 Write Burst access</a></li>
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                <li><a href="#3.4.2 Read Burst access">                   3.4.2 Read Burst access</a></li>
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                        </ul>
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                </ul>
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</ul>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The original MSP430 from TI provides a serial debug interface to give a simple path to software development. In that case, the communication with the host computer is typically build on a JTAG or Spy-Bi-Wire serial protocol. However, the global debug architecture from the MSP430 is unfortunately poorly documented on the web (and is also probably tightly linked with the internal core architecture).
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<br /><br />
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A custom module has therefore been implemented for the openMSP430. The communication with the host is done with a simple RS232 cable (8N1 serial protocol) and the debug unit provides all the required features for Nexus Class 3 debugging (beside trace), namely:
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<ul>
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        <li>CPU control (run, stop, step, reset).</li>
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        <li>Software & hardware breakpoint support.</li>
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        <li>Memory read/write on-the-fly (no need to halt execution).</li>
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        <li>CPU registers read/write on-the-fly (no need to halt execution).</li>
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</ul>
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67
<a name="2. Debug Unit"></a>
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<div style="text-align: right"><a href="#TOC">Top</a></div>
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<h1>2. Debug Unit</h1>
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71
<a name="2.1 Register Mapping"></a>
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<h2>2.1 Register Mapping</h2>
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The following table summarize the complete debug register set accessible through the debug communication interface:
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<br /><br />
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<table border="1">
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<tr align="center">
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<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
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<td rowspan="2" ><b><font size="-1">Address</font></b></td>
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<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
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</tr>
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<tr align="center">
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<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
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<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
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<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
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<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
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<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
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<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
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<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
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<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_LO</a></font></td>
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<td><font size="-1">0x00</font></td>
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<td colspan="8"><font size="-5">CPU_ID[7:0]</font></td>
96
<td colspan="4"><font size="-5">PMEM_AWIDTH</font></td>
97
<td colspan="4"><font size="-5">DMEM_AWIDTH</font></td>
98
</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_HI</a></font></td>
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<td><font size="-1">0x01</font></td>
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<td colspan="16"><font size="-5">CPU_ID[23:8]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.2.2 CPU_CTL">CPU_CTL</a></font></td>
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<td><font size="-1">0x02</font></td>
107
<td colspan="9"><font size="-5">Reserved</font></td>
108
<td><font size="-5">CPU_RST</font></td>
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<td><font size="-5">RST_BRK_EN</font></td>
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<td><font size="-5">FRZ_BRK_EN</font></td>
111
<td><font size="-5">SW_BRK_EN</font></td>
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<td><font size="-5">ISTEP</font></td>
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<td><font size="-5">RUN</font></td>
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<td><font size="-5">HALT</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.2.3 CPU_STAT">CPU_STAT</a></font></td>
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<td><font size="-1">0x03</font></td>
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<td colspan="8"><font size="-5">Reserved</font></td>
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<td><font size="-5">HWBRK3_PND</font></td>
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<td><font size="-5">HWBRK2_PND</font></td>
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<td><font size="-5">HWBRK1_PND</font></td>
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<td><font size="-5">HWBRK0_PND</font></td>
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<td><font size="-5">SWBRK_PND</font></td>
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<td><font size="-5">PUC_PND</font></td>
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<td><font size="-5">Res.</font></td>
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<td><font size="-5">HALT_RUN</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.3.1 MEM_CTL">MEM_CTL</a></font></td>
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<td><font size="-1">0x04</font></td>
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<td colspan="12"><font size="-5">Reserved</font></td>
133
<td><font size="-5">B/W</font></td>
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<td><font size="-5">MEM/REG</font></td>
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<td><font size="-5">RD/WR</font></td>
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<td><font size="-5">START</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.3.2 MEM_ADDR">MEM_ADDR</a></font></td>
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<td><font size="-1">0x05</font></td>
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<td colspan="16"><font size="-5">MEM_ADDR[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.3.3 MEM_DATA">MEM_DATA</a></font></td>
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<td><font size="-1">0x06</font></td>
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<td colspan="16"><font size="-5">MEM_DATA[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.3.4 MEM_CNT">MEM_CNT</a></font></td>
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<td><font size="-1">0x07</font></td>
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<td colspan="16"><font size="-5">MEM_CNT[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.1 BRKx_CTL">BRK0_CTL</a></font></td>
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<td><font size="-1">0x08</font></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
162
<tr align="center">
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<td><font size="-1"><a href="#2.4.2 BRKx_STAT">BRK0_STAT</a></font></td>
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<td><font size="-1">0x09</font></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.3 BRKx_ADDR0">BRK0_ADDR0</a></font></td>
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<td><font size="-1">0x0A</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.4 BRKx_ADDR1">BRK0_ADDR1</a></font></td>
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<td><font size="-1">0x0B</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.1 BRKx_CTL">BRK1_CTL</a></font></td>
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<td><font size="-1">0x0C</font></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
191
</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.2 BRKx_STAT">BRK1_STAT</a></font></td>
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<td><font size="-1">0x0D</font></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.3 BRKx_ADDR0">BRK1_ADDR0</a></font></td>
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<td><font size="-1">0x0E</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
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</tr>
208
<tr align="center">
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<td><font size="-1"><a href="#2.4.4 BRKx_ADDR1">BRK1_ADDR1</a></font></td>
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<td><font size="-1">0x0F</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.1 BRKx_CTL">BRK2_CTL</a></font></td>
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<td><font size="-1">0x10</font></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
218
<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.2 BRKx_STAT">BRK2_STAT</a></font></td>
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<td><font size="-1">0x11</font></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.3 BRKx_ADDR0">BRK2_ADDR0</a></font></td>
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<td><font size="-1">0x12</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.4 BRKx_ADDR1">BRK2_ADDR1</a></font></td>
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<td><font size="-1">0x13</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.1 BRKx_CTL">BRK3_CTL</a></font></td>
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<td><font size="-1">0x14</font></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
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<tr align="center">
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<td><font size="-1"><a href="#2.4.2 BRKx_STAT">BRK3_STAT</a></font></td>
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<td><font size="-1">0x15</font></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
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<td><font size="-5">ADDR1_WR</font></td>
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<td><font size="-5">ADDR1_RD</font></td>
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<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
262
</tr>
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<tr align="center">
264
<td><font size="-1"><a href="#2.4.3 BRKx_ADDR0">BRK3_ADDR0</a></font></td>
265
<td><font size="-1">0x16</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
267
</tr>
268
<tr align="center">
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<td><font size="-1"><a href="#2.4.4 BRKx_ADDR1">BRK3_ADDR1</a></font></td>
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<td><font size="-1">0x17</font></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
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</tr>
273
</table>
274
 
275
<a name="2.2 CPU Control/Status Registers"></a>
276
<div style="text-align: right"><a href="#TOC">Top</a></div>
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<h2>2.2 CPU Control/Status Registers</h2>
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279
<a name="2.2.1 CPU_ID"></a>
280
<h3>2.2.1 CPU_ID</h3>
281
This 32 bit read-only register holds the ID of the implemented openMSP430 as well as the program and data memory size information.
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<br /><br />
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<table border="1">
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<tr align="center">
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<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
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<td rowspan="2" ><b><font size="-1">Address</font></b></td>
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<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
288
</tr>
289
<tr align="center">
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<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
291
<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
292
<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
293
<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
294
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
295
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
296
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
297
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
298
</tr>
299
<tr align="center">
300
<td><font size="-1">CPU_ID_LO</font></td>
301
<td><font size="-1">0x00</font></td>
302
<td colspan="8"><font size="-5">CPU_ID[7:0]</font></td>
303
<td colspan="4"><font size="-5">PMEM_AWIDTH</font></td>
304
<td colspan="4"><font size="-5">DMEM_AWIDTH</font></td>
305
</tr>
306
<tr align="center">
307
<td><font size="-1">CPU_ID_HI</font></td>
308
<td><font size="-1">0x01</font></td>
309
<td colspan="16"><font size="-5">CPU_ID[23:7]</font></td>
310
</tr>
311
</table>
312
<br />
313
<table border="0">
314
<tr>
315
   <td>&nbsp;</td><td valign="top"><li><b>CPU_ID</b></li></td>
316
   <td>: Set by default to 0x4D5350 (ascii code for "MSP")</td>
317
</tr>
318
<tr>
319
   <td>&nbsp;</td><td valign="top"><li><b>PMEM_AWIDTH</b></li></td>
320
   <td>: Program memory address width for the current implementation. The ROM or RAM size is then equal to 2<sup><font size="-3">PMEM_AWIDTH</font></sup></td>
321
</tr>
322
<tr>
323
   <td>&nbsp;</td><td valign="top"><li><b>DMEM_AWIDTH</b></li></td>
324
   <td>: Data memory address width for the current implementation. The RAM size is then equal to 2<sup><font size="-3">DMEM_AWIDTH</font></sup></td>
325
</tr>
326
</table>
327
 
328
<a name="2.2.2 CPU_CTL"></a>
329
<h3>2.2.2 CPU_CTL</h3>
330
 
331
This 8 bit read-write register is used to control the CPU and to configure some basic debug features. After a POR, this register is set to 0x00.
332
<br /><br />
333
<table border="1">
334
<tr align="center">
335
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
336
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
337
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
338
</tr>
339
<tr align="center">
340
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
341
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
342
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
343
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
344
</tr>
345
<tr align="center">
346
<td><font size="-1">CPU_CTL</font></td>
347
<td><font size="-1">0x02</font></td>
348
<td><font size="-5">Res.</font></td>
349
<td><font size="-5">CPU_RST</font></td>
350
<td><font size="-5">RST_BRK_EN</font></td>
351
<td><font size="-5">FRZ_BRK_EN</font></td>
352
<td><font size="-5">SW_BRK_EN</font></td>
353
<td><font size="-5">ISTEP</font></td>
354
<td><font size="-5">RUN</font></td>
355
<td><font size="-5">HALT</font></td>
356
</tr>
357
</table>
358
<br />
359
<table border="0">
360
<tr>
361
   <td>&nbsp;</td><td valign="top"><li><b>CPU_RST</b></li></td>
362
   <td>: Setting this bit to 1 will activate the PUC reset. Setting it back to 0 will release it.</td>
363
</tr>
364
<tr>
365
   <td>&nbsp;</td><td valign="top"><li><b>RST_BRK_EN</b></li></td>
366
   <td>: If set to 1, the CPU will automatically break after a PUC occurrence.</td>
367
</tr>
368
<tr>
369
   <td>&nbsp;</td><td valign="top"><li><b>FRZ_BRK_EN</b></li></td>
370
   <td>: If set to 1, the timers and watchdog are frozen when the CPU is halted.</td>
371
</tr>
372
<tr>
373
   <td>&nbsp;</td><td valign="top"><li><b>SW_BRK_EN</b></li></td>
374
   <td>: Enables the software breakpoint detection.</td>
375
</tr>
376
<tr>
377
   <td>&nbsp;</td><td valign="top"><li><b>ISTEP</b><sup>1</sup></li></td>
378
   <td>: Writing 1 to this bit will perform a single instruction step if the CPU is halted.</td>
379
</tr>
380
<tr>
381
   <td>&nbsp;</td><td valign="top"><li><b>RUN</b><sup>1</sup></li></td>
382
   <td>: Writing 1 to this bit will get the CPU out of halt state.</td>
383
</tr>
384
<tr>
385
   <td>&nbsp;</td><td valign="top"><li><b>HALT</b><sup>1</sup></li></td>
386
   <td>: Writing 1 to this bit will put the CPU in halt state.</td>
387
</tr>
388
</table>
389
<br /><sup>1</sup>:this field is write-only and always reads back 0.
390
<br />
391
<a name="2.2.3 CPU_STAT"></a>
392
<h3>2.2.3 CPU_STAT</h3>
393
 
394
This 8 bit read-write register gives the global status of the debug interface. After a POR, this register is set to 0x00.
395
<br /><br />
396
<table border="1">
397
<tr align="center">
398
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
399
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
400
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
401
</tr>
402
<tr align="center">
403
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
404
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
405
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
406
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
407
</tr>
408
<tr align="center">
409
<td><font size="-1">CPU_STAT</font></td>
410
<td><font size="-1">0x03</font></td>
411
<td><font size="-5">HWBRK3_PND</font></td>
412
<td><font size="-5">HWBRK2_PND</font></td>
413
<td><font size="-5">HWBRK1_PND</font></td>
414
<td><font size="-5">HWBRK0_PND</font></td>
415
<td><font size="-5">SWBRK_PND</font></td>
416
<td><font size="-5">PUC_PND</font></td>
417
<td><font size="-5">Res.</font></td>
418
<td><font size="-5">HALT_RUN</font></td>
419
</tr>
420
</table>
421
<br />
422
<table border="0">
423
<tr>
424
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK3_PND</b></li></td>
425
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 3 status bit is set (i.e. BRK3_STAT&ne;0).</td>
426
</tr>
427
<tr>
428
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK2_PND</b></li></td>
429
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 2 status bit is set (i.e. BRK2_STAT&ne;0).</td>
430
</tr>
431
<tr>
432
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK1_PND</b></li></td>
433
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 1 status bit is set (i.e. BRK1_STAT&ne;0).</td>
434
</tr>
435
<tr>
436
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK0_PND</b></li></td>
437
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 0 status bit is set (i.e. BRK0_STAT&ne;0).</td>
438
</tr>
439
<tr>
440
   <td>&nbsp;</td><td valign="top"><li><b>SWBRK_PND</b></li></td>
441
   <td>: This bit is set to 1 when a software breakpoint occurred. It can be cleared by writing 1 to it.</td>
442
</tr>
443
<tr>
444
   <td>&nbsp;</td><td valign="top"><li><b>PUC_PND</b></li></td>
445
   <td>: This bit is set to 1 when a PUC reset occured. It can be cleared by writing 1 to it.</td>
446
</tr>
447
<tr>
448
   <td>&nbsp;</td><td valign="top"><li><b>HALT_RUN</b></li></td>
449
   <td>: This read-only bit gives the current status of the CPU:
450
   </td>
451
</tr>
452
<tr>
453
   <td>&nbsp;</td><td>&nbsp;</td>
454
   <td>&nbsp;&nbsp;&nbsp;0 - CPU is running.
455
         <br />&nbsp;&nbsp;&nbsp;1 - CPU is stopped.
456
   </td>
457
</tr>
458
</table>
459
 
460
<a name="2.3 Memory Access Registers"></a>
461
<div style="text-align: right"><a href="#TOC">Top</a></div>
462
<h2>2.3 Memory Access Registers</h2>
463
 
464
The following four registers enable single and burst read/write access to both CPU-Registers and full memory address range.
465
<br />In order to perform an access, the following sequences are typically done:
466
<ul>
467
   <li>single read access (MEM_CNT=0):</li>
468
        <ol>
469
        <li>set MEM_ADDR with the memory address (or register number) to be read</li>
470
                <li>set MEM_CTL (in particular RD/WR=0 and START=1)</li>
471
                <li>read MEM_DATA</li>
472
        </ol>
473
        <li>single write access (MEM_CNT=0):</li>
474
        <ol>
475
        <li>set MEM_ADDR with the memory address (or register number) to be written</li>
476
                <li>set MEM_DATA with the data to be written</li>
477
                <li>set MEM_CTL (in particular RD/WR=1 and START=1)</li>
478
        </ol>
479
   <li>burst read/write access (MEM_CNT&ne;0):</li>
480
        <ul>
481
        <li>burst access are optimized for the communication interface used (i.e. for the UART).
482
        The burst sequence are therefore described in the corresponding section (<a href="#3.4 Read/Write burst implementation for the CPU Memory access">3.4 Read/Write burst implementation for the CPU Memory access</a>)</li>
483
        </ul>
484
</ul>
485
<a name="2.3.1 MEM_CTL"></a>
486
<h3>2.3.1 MEM_CTL</h3>
487
 
488
This 8 bit read-write register is used to control the Memory and CPU-Register read/write access. After a POR, this register is set to 0x00.
489
<br /><br />
490
<table border="1">
491
<tr align="center">
492
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
493
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
494
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
495
</tr>
496
<tr align="center">
497
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
498
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
499
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
500
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
501
</tr>
502
<tr align="center">
503
<td><font size="-1">MEM_CTL</font></td>
504
<td><font size="-1">0x04</font></td>
505
<td colspan="4"><font size="-5">Reserved</font></td>
506
<td><font size="-5">B/W</font></td>
507
<td><font size="-5">MEM/REG</font></td>
508
<td><font size="-5">RD/WR</font></td>
509
<td><font size="-5">START</font></td>
510
</tr>
511
</table>
512
<br />
513
<table border="0">
514
<tr>
515
   <td>&nbsp;</td><td valign="top"><li><b>B/W</b></li></td>
516
   <td>: 0 - 16 bit access.</td>
517
</tr>
518
<tr>
519
   <td>&nbsp;</td><td>&nbsp;</td>
520
   <td>&nbsp;&nbsp;1 - &nbsp;&nbsp;8 bit access (not valid for CPU-Registers).</td>
521
</tr>
522
<tr>
523
   <td>&nbsp;</td><td valign="top"><li><b>MEM/REG</b></li></td>
524
   <td>: 0 - Memory access.</td>
525
</tr>
526
<tr>
527
   <td>&nbsp;</td><td>&nbsp;</td>
528
   <td>&nbsp;&nbsp;1 - CPU-Register access.</td>
529
</tr>
530
<tr>
531
   <td>&nbsp;</td><td valign="top"><li><b>RD/WR</b></li></td>
532
   <td>: 0 - Read access.</td>
533
</tr>
534
<tr>
535
   <td>&nbsp;</td><td>&nbsp;</td>
536
   <td>&nbsp;&nbsp;1 - Write access.</td>
537
</tr>
538
<tr>
539
   <td>&nbsp;</td><td valign="top"><li><b>START</b></li></td>
540
   <td>: 0- Do nothing</td>
541
</tr>
542
<tr>
543
   <td>&nbsp;</td><td>&nbsp;</td>
544
   <td>&nbsp;&nbsp;1 - Initiate memory transfer.</td>
545
</tr>
546
</table>
547
 
548
<a name="2.3.2 MEM_ADDR"></a>
549
<h3>2.3.2 MEM_ADDR</h3>
550
 
551
This 16 bit read-write register specifies the Memory or CPU-Register address to be used for the next read/write transfer. After a POR, this register is set to 0x0000.
552
<br />
553
<strong>Note:</strong> in case of burst (i.e. MEM_CNT&ne;0), this register specifies the first address of the burst transfer and will be incremented automatically as the burst goes (by 1 for 8-bit access and by 2 for 16-bit access).
554
<br /><br />
555
<table border="1">
556
<tr align="center">
557
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
558
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
559
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
560
</tr>
561
<tr align="center">
562
<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
563
<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
564
<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
565
<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
566
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
567
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
568
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
569
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
570
</tr>
571
<tr align="center">
572
<td><font size="-1">MEM_ADDR</font></td>
573
<td><font size="-1">0x05</font></td>
574
<td colspan="16"><font size="-5">MEM_ADDR[15:0]</font></td>
575
</tr>
576
</table>
577
<br />
578
<table border="0">
579
<tr>
580
   <td>&nbsp;</td><td valign="top"><li><b>MEM_ADDR</b></li></td>
581
   <td>: Memory or CPU-Register address to be used for the next read/write transfer.</td>
582
</tr>
583
</table>
584
 
585
<a name="2.3.3 MEM_DATA"></a>
586
<h3>2.3.3 MEM_DATA</h3>
587
 
588
This 16 bit read-write register specifies (wr) or receive (rd) the Memory or CPU-Register data for the the next transfer. After a POR, this register is set to 0x0000.
589
<br /><br />
590
<table border="1">
591
<tr align="center">
592
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
593
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
594
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
595
</tr>
596
<tr align="center">
597
<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
598
<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
599
<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
600
<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
601
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
602
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
603
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
604
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
605
</tr>
606
<tr align="center">
607
<td><font size="-1">MEM_DATA</font></td>
608
<td><font size="-1">0x06</font></td>
609
<td colspan="16"><font size="-5">MEM_DATA[15:0]</font></td>
610
</tr>
611
</table>
612
<br />
613
<table border="0">
614
<tr>
615
   <td>&nbsp;</td><td valign="top"><li><b>MEM_DATA</b></li></td>
616
   <td>: if MEM_CTL.WR - data to be written during the next write transfer.</td>
617
</tr>
618
<tr>
619
   <td>&nbsp;</td><td>&nbsp;</td>
620
   <td>&nbsp;&nbsp;if MEM_CTL.RD - updated with the data from the read transfer</td>
621
</tr>
622
</table>
623
 
624
<a name="2.3.4 MEM_CNT"></a>
625
<h3>2.3.4 MEM_CNT</h3>
626
 
627
This 16 bit read-write register controls the burst access to the Memory or CPU-Registers. If set to 0, a single access will occur, otherwise, a burst will be performed. The burst being optimized for the communication interface, more details are given <a href="#3.4 Read/Write burst implementation for the CPU Memory access">there</a>. After a POR, this register is set to 0x0000.
628
<br /><br />
629
<table border="1">
630
<tr align="center">
631
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
632
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
633
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
634
</tr>
635
<tr align="center">
636
<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
637
<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
638
<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
639
<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
640
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
641
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
642
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
643
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
644
</tr>
645
<tr align="center">
646
<td><font size="-1">MEM_CNT</font></td>
647
<td><font size="-1">0x07</font></td>
648
<td colspan="16"><font size="-5">MEM_CNT[15:0]</font></td>
649
</tr>
650
</table>
651
<br />
652
<table border="0">
653
<tr>
654
   <td>&nbsp;</td><td valign="top"><li><b>MEM_CNT</b></li></td>
655
   <td>: =0 - a single access will be performed with the next transfer.</td>
656
</tr>
657
<tr>
658
   <td>&nbsp;</td><td>&nbsp;</td>
659
   <td>&nbsp;&nbsp;&ne;0 - specifies the burst size for the next transfer (i.e number of data access). This field will be automatically decremented as the burst goes.</td>
660
</tr>
661
</table>
662
 
663
<a name="2.4 Hardware Breakpoint Unit Registers"></a>
664
<div style="text-align: right"><a href="#TOC">Top</a></div>
665
<h2>2.4 Hardware Breakpoint Unit Registers</h2>
666
Depending on the <a href="http://www.opencores.org/project/openmsp430/core#2.1.3 Configuration">defines</a> located in the "openmsp430_defines.v" file, up to four hardware breakpoint units can be included in the design. These units can be individually controlled with the following registers.
667
<a name="2.4.1 BRKx_CTL"></a>
668
<h3>2.4.1 BRKx_CTL</h3>
669
 
670
This 8 bit read-write register controls the hardware breakpoint unit x. After a POR, this register is set to 0x00.
671
<br /><br />
672
<table border="1">
673
<tr align="center">
674
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
675
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
676
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
677
</tr>
678
<tr align="center">
679
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
680
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
681
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
682
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
683
</tr>
684
<tr align="center">
685
<td><font size="-1">BRKx_CTL</font></td>
686
<td><font size="-1">0x08, 0x0C, 0x10, 0x14</font></td>
687
<td colspan="3"><font size="-5">Reserved</font></td>
688
<td><font size="-5">RANGE_MODE</font></td>
689
<td><font size="-5">INST_EN</font></td>
690
<td><font size="-5">BREAK_EN</font></td>
691
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
692
</tr>
693
</table>
694
<br />
695
<table border="0">
696
<tr>
697
   <td>&nbsp;</td><td valign="top"><li><b>RANGE_MODE</b></li></td>
698
   <td>:  0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
699
</tr>
700
<tr>
701
   <td>&nbsp;</td><td>&nbsp;</td>
702 58 olivier.gi
   <td>&nbsp;&nbsp;1 - Address match on BRK_ADDR0&rarr;BRK_ADDR1 range (range mode)
703
   <br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
704
</td>
705 50 olivier.gi
</tr>
706
<tr>
707
   <td>&nbsp;</td><td valign="top"><li><b>INST_EN</b></li></td>
708
   <td>: 0 - Checks are done on the execution unit (data flow).</td>
709
</tr>
710
<tr>
711
   <td>&nbsp;</td><td>&nbsp;</td>
712
   <td>&nbsp;&nbsp;1 - Checks are done on the frontend (instruction flow).</td>
713
</tr>
714
 
715
<tr>
716
   <td>&nbsp;</td><td valign="top"><li><b>BREAK_EN</b></li></td>
717
   <td>: 0 - Watchpoint mode enable (don't stop on address match).</td>
718
</tr>
719
<tr>
720
   <td>&nbsp;</td><td>&nbsp;</td>
721
   <td>&nbsp;&nbsp;1 - Breakpoint mode enable (stop on address match).</td>
722
</tr>
723
 
724
<tr>
725
   <td>&nbsp;</td><td valign="top"><li><b>ACCESS_MODE</b></li></td>
726
   <td>: 00 - Disabled</td>
727
</tr>
728
<tr>
729
   <td>&nbsp;</td><td>&nbsp;</td>
730
   <td>  &nbsp;&nbsp;01 - Detect read access.
731
   <br />&nbsp;&nbsp;10 - Detect write access.
732
   <br />&nbsp;&nbsp;11 - Detect read/write access
733
   <br /><b>Note</b>: '10' & '11' modes are not supported on the instruction flow</td>
734
</tr>
735
</table>
736
 
737
<a name="2.4.2 BRKx_STAT"></a>
738
<h3>2.4.2 BRKx_STAT</h3>
739
 
740
This 8 bit read-write register gives the status of the hardware breakpoint unit x. Each status bit can be cleared by writing 1 to it. After a POR, this register is set to 0x00.
741
<br /><br />
742
<table border="1">
743
<tr align="center">
744
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
745
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
746
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
747
</tr>
748
<tr align="center">
749
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
750
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
751
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
752
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
753
</tr>
754
<tr align="center">
755
<td><font size="-1">BRKx_STAT</font></td>
756
<td><font size="-1">0x09, 0x0D, 0x11, 0x15</font></td>
757
<td colspan="2"><font size="-5">Reserved</font></td>
758
<td><font size="-5">RANGE_WR</font></td>
759
<td><font size="-5">RANGE_RD</font></td>
760
<td><font size="-5">ADDR1_WR</font></td>
761
<td><font size="-5">ADDR1_RD</font></td>
762
<td><font size="-5">ADDR0_WR</font></td>
763
<td><font size="-5">ADDR0_RD</font></td>
764
</tr>
765
</table>
766
<br />
767
<table border="0">
768
<tr>
769
   <td>&nbsp;</td><td valign="top"><li><b>RANGE_WR</b></li></td>
770
   <td>: This bit is set whenever the CPU performs a write access within the BRKx_ADDR0&rarr;BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[1]=1).</td>
771
</tr>
772
<tr>
773
   <td>&nbsp;</td><td valign="top"><li><b>RANGE_RD</b></li></td>
774 58 olivier.gi
   <td>: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0&rarr;BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1).
775
   <br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
776 50 olivier.gi
</tr>
777
<tr>
778
   <td>&nbsp;</td><td valign="top"><li><b>ADDR1_WR</b></li></td>
779
   <td>: This bit is set whenever the CPU performs a write access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
780
</tr>
781
<tr>
782
   <td>&nbsp;</td><td valign="top"><li><b>ADDR1_RD</b></li></td>
783
   <td>: This bit is set whenever the CPU performs a read access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).</td>
784
</tr>
785
<tr>
786
   <td>&nbsp;</td><td valign="top"><li><b>ADDR0_WR</b></li></td>
787
   <td>: This bit is set whenever the CPU performs a write access at the BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
788
</tr>
789
<tr>
790
   <td>&nbsp;</td><td valign="top"><li><b>ADDR0_RD</b></li></td>
791
   <td>: This bit is set whenever the CPU performs a read access at the BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).</td>
792
</tr>
793
</table>
794
 
795
<a name="2.4.3 BRKx_ADDR0"></a>
796
<h3>2.4.3 BRKx_ADDR0</h3>
797
 
798
This 16 bit read-write register holds the value which is compared against the address value currently present on the program or data address bus. After a POR, this register is set to 0x0000.
799
<br /><br />
800
<table border="1">
801
<tr align="center">
802
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
803
<td rowspan="2" ><b><font size="-1">Address</font></b></td>
804
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
805
</tr>
806
<tr align="center">
807
<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
808
<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
809
<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
810
<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
811
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
812
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
813
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
814
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
815
</tr>
816
<tr align="center">
817
<td><font size="-1">BRKx_ADDR0</font></td>
818
<td><font size="-1">0x0A, 0x0E, 0x12, 0x16</font></td>
819
<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
820
</tr>
821
</table>
822
<br />
823
<table border="0">
824
<tr>
825
   <td>&nbsp;</td><td valign="top"><li><b>BRK_ADDR0</b></li></td>
826
   <td>: Value compared against the address value currently present on the program or data address bus.</td>
827
</tr>
828
</table>
829
 
830
<a name="2.4.4 BRKx_ADDR1"></a>
831
<h3>2.4.4 BRKx_ADDR1</h3>
832
 
833
This 16 bit read-write register holds the value which is compared against the address value currently present on the program or data address bus. After a POR, this register is set to 0x0000.
834
<br /><br />
835
<table border="1">
836
<tr align="center">
837
<td rowspan="2" ><b><font size="-1">Register Name</font></b></td>
838
<td rowspan="2" ><b><font size="-1">Addresses</font></b></td>
839
<td colspan="16"><b><font size="-1">Bit Field</font></b></td>
840
</tr>
841
<tr align="center">
842
<td><font size="-1">15</font></td><td><font size="-1">14</font></td>
843
<td><font size="-1">13</font></td><td><font size="-1">12</font></td>
844
<td><font size="-1">11</font></td><td><font size="-1">10</font></td>
845
<td><font size="-1"> 9</font></td><td><font size="-1"> 8</font></td>
846
<td><font size="-1"> 7</font></td><td><font size="-1"> 6</font></td>
847
<td><font size="-1"> 5</font></td><td><font size="-1"> 4</font></td>
848
<td><font size="-1"> 3</font></td><td><font size="-1"> 2</font></td>
849
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
850
</tr>
851
<tr align="center">
852
<td><font size="-1">BRKx_ADDR1</font></td>
853
<td><font size="-1">0x0B, 0x0F, 0x13, 0x17</font></td>
854
<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
855
</tr>
856
</table>
857
<br />
858
<table border="0">
859
<tr>
860
   <td>&nbsp;</td><td valign="top"><li><b>BRK_ADDR1</b></li></td>
861
   <td>: Value compared against the address value currently present on the program or data address bus.</td>
862
</tr>
863
</table>
864
 
865
<a name="3. Debug Communication Interface: UART"></a>
866
<div style="text-align: right"><a href="#TOC">Top</a></div>
867
<h1>3. Debug Communication Interface: UART</h1>
868
With its UART interface, the openMSP430 debug unit can communicate with the host computer using a simple RS232 cable (connected to the <a href="http://www.opencores.org/project/openmsp430/core#2.1.4 Pinout">dbg_uart_txd</a> and <a href="http://www.opencores.org/project/openmsp430/core#2.1.4 Pinout">dbg_uart_rxd</a> ports of the IP).<br />
869
Using an standard <a href="http://www.google.com/search?q=usb+to+rs232+converter">USB to RS232 adaptor</a>, the interface provides a reliable communication link up to 1,5Mbps.
870
 
871
<a name="3.1 Serial communication protocol: 8N1"></a>
872
<h2>3.1 Serial communication protocol: 8N1</h2>
873
There are plenty tutorials on Internet regarding RS232 based protocols. However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No Parity, 1 Stop bit):<br />
874
<br />
875
<img src="getimg.php?1247419201" alt="8N1 Serial Protocol" title="8N1 Serial Protocol" />
876
<br />
877
As you can see in the above diagram, data transmission starts with a Start bit, followed by the data bits (LSB sent first and MSB sent last), and ends with a "Stop" bit.
878
 
879
<a name="3.2 Synchronization frame"></a>
880
<h2>3.2 Synchronization frame</h2>
881
After a POR, the Serial Debug Interface expects a synchronization frame from the host computer in order to determine the communication speed (i.e. the baud rate).<br />
882
The synchronization frame looks as following:
883
<br />
884
<img src="getimg.php?1247420610" alt="Debug Synchronization Frame" title="Debug Synchronization Frame" />
885
<br />
886
As you can see, the host simply sends the 0x80 value. The openMSP430 will then measure the time between the falling and rising edge, divide it by 8 and automatically deduce the baud rate it should use to properly communicate with the host.
887
<br /><br />
888
<b>Important note</b>: if you want to change the communication speed between two debugging sessions, the openMSP430 needs to go over a POR cycle and a new synchronization frame needs to be send.
889
 
890
<a name="3.3 Read/Write access to the debug registers"></a>
891
<h2>3.3 Read/Write access to the debug registers</h2>
892
In order to perform a read / write access to a debug register, the host needs to send a command frame to the openMSP430.<br />
893
In case of write access, this command frame will be followed by 1 or 2 data frames and in case of read access, the openMSP430 will send 1 or 2 data frames after receiving the command.
894
 
895
<a name="3.3.1 Command Frame"></a>
896
<h3>3.3.1 Command Frame</h3>
897
The command frame looks as following:
898
<br />
899
<img src="getimg.php?1247427400" alt="Debug Command Frame" title="Debug Command Frame" />
900
<br />
901
<table border="0">
902
<tr>
903
   <td>&nbsp;</td><td valign="top"><li><b>WR</b></li></td>
904
   <td>: Perform a Write access when set. Read otherwise.</td>
905
</tr>
906
<tr>
907
   <td>&nbsp;</td><td valign="top"><li><b>B/W</b></li></td>
908
   <td>: Perform a 8-bit data access when set (one data frame). 16-bit otherwise (two data frame).<tr>
909
</tr>
910
<tr>
911
   <td>&nbsp;</td><td valign="top"><li><b>Address</b></li></td>
912
   <td>: Debug register address.<tr>
913
</tr>
914
</table>
915
 
916
<a name="3.3.2 Write access"></a>
917
<h3>3.3.2 Write access</h3>
918
A write access transaction looks like this:
919
<br />
920
<img src="getimg.php?1247428987" alt="Debug Write Transaction" title="Debug Write Transaction" />
921
 
922
<a name="3.3.3 Read access"></a>
923
<h3>3.3.3 Read access</h3>
924
A read access transaction looks like this:
925
<br />
926
<img src="getimg.php?1247429086" alt="Debug Read Transaction" title="Debug Read Transaction" />
927
 
928
<a name="3.4 Read/Write burst implementation for the CPU Memory access"></a>
929
<h2>3.4 Read/Write burst implementation for the CPU Memory access</h2>
930
In order to optimize the data burst transactions for the UART, read/write access are not done by reading or writing the MEM_DATA register.<br />
931
Instead, the data transfer starts immediately after the MEM_CTL.START bit has been set.
932
 
933
<a name="3.4.1 Write Burst access"></a>
934
<h3>3.4.1 Write Burst access</h3>
935
A write burst transaction looks like this:
936
<br />
937
<img src="getimg.php?1247430408" alt="Debug Write Burst Transaction" title="Debug Write Burst Transaction" />
938
 
939
<a name="3.4.2 Read Burst access"></a>
940
<h3>3.4.2 Read Burst access</h3>
941
A read burst transaction looks like this:
942
<br />
943
<img src="getimg.php?1247430449" alt="Debug Read Burst Transaction" title="Debug Read Burst Transaction" />
944
 
945
<div style="text-align: right"><a href="#TOC">Top</a></div>
946
</body>
947
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