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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 221

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: tb_openMSP430_fpga.v
// 
// *Module Description:
//                      openMSP430 FPGA testbench
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module  tb_openMSP430_fpga;
 
//
// Wire & Register definition
//------------------------------
 
// Clock
reg         [1:0] CLOCK_24;
reg         [1:0] CLOCK_27;
reg               CLOCK_50;
reg               EXT_CLOCK;
 
// Push Button
reg         [3:0] KEY;
 
// DPDT Switch
reg         [9:0] SW;
 
// 7-SEG Dispaly
wire        [6:0] HEX0;
wire        [6:0] HEX1;
wire        [6:0] HEX2;
wire        [6:0] HEX3;
 
// LED
wire        [7:0] LEDG;
wire        [9:0] LEDR;
 
// UART
wire              UART_TXD;
reg               UART_RXD;
 
// SDRAM Interface
wire       [15:0] DRAM_DQ;
wire       [11:0] DRAM_ADDR;
wire              DRAM_LDQM;
wire              DRAM_UDQM;
wire              DRAM_WE_N;
wire              DRAM_CAS_N;
wire              DRAM_RAS_N;
wire              DRAM_CS_N;
wire              DRAM_BA_0;
wire              DRAM_BA_1;
wire              DRAM_CLK;
wire              DRAM_CKE;
 
// Flash Interface
wire        [7:0] FL_DQ;
wire       [21:0] FL_ADDR;
wire              FL_WE_N;
wire              FL_RST_N;
wire              FL_OE_N;
wire              FL_CE_N;
 
// SRAM Interface
wire       [15:0] SRAM_DQ;
wire       [17:0] SRAM_ADDR;
wire              SRAM_UB_N;
wire              SRAM_LB_N;
wire              SRAM_WE_N;
wire              SRAM_CE_N;
wire              SRAM_OE_N;
 
// SD Card Interface
wire              SD_DAT;
wire              SD_DAT3;
wire              SD_CMD;
wire              SD_CLK;
 
// I2C
wire              I2C_SDAT;
wire              I2C_SCLK;
 
// PS2
reg               PS2_DAT;
reg               PS2_CLK;
 
// USB JTAG link
reg               TDI;
reg               TCK;
reg               TCS;
wire              TDO;
 
// VGA
wire              VGA_HS;
wire              VGA_VS;
wire        [3:0] VGA_R;
wire        [3:0] VGA_G;
wire        [3:0] VGA_B;
 
// Audio CODEC
wire              AUD_ADCLRCK;
reg               AUD_ADCDAT;
wire              AUD_DACLRCK;
wire              AUD_DACDAT;
wire              AUD_BCLK;
wire              AUD_XCK;
 
// GPIO
wire       [35:0] GPIO_0;
wire       [35:0] GPIO_1;
 
 
// Core debug signals
wire   [8*32-1:0] i_state;
wire   [8*32-1:0] e_state;
wire       [31:0] inst_cycle;
wire   [8*32-1:0] inst_full;
wire       [31:0] inst_number;
wire       [15:0] inst_pc;
wire   [8*32-1:0] inst_short;
 
// Testbench variables
integer           i;
integer           error;
reg               stimulus_done;
 
 
//
// Include files
//------------------------------
 
// CPU & Memory registers
`include "registers.v"
 
// Verilog stimulus
`include "stimulus.v"
 
//
// Initialize Program Memory
//------------------------------
 
initial
   begin
      // Read memory file
      #10 $readmemh("./pmem.mem", pmem);
  end
 
//
// Generate Clock & Reset
//------------------------------
initial
  begin
     CLOCK_24 = 2'b10;
     forever #20.8 CLOCK_24 = ~CLOCK_24; // 24 MHz
  end
initial
  begin
     CLOCK_27 = 2'b01;
     forever #18.5 CLOCK_27 = ~CLOCK_27; // 27 MHz
  end
initial
  begin
     CLOCK_50 = 1'b0;
     forever #10.0 CLOCK_50 = ~CLOCK_50; // 50 MHz
  end
 
initial
  begin
     KEY[3]        = 1'b1;
     #100 KEY[3]   = 1'b0;
     #600 KEY[3]   = 1'b1;
  end
 
//
// Global initialization
//------------------------------
initial
  begin
     error         = 0;
     stimulus_done = 1;
     EXT_CLOCK     = 1'b0;
     KEY[2:0]      = 3'b111;
     SW            = 10'h000;
     UART_RXD      = 1'b0;
     PS2_DAT       = 1'b0;
     PS2_CLK       = 1'b0;
     TDI           = 1'b0;
     TCK           = 1'b0;
     TCS           = 1'b0;
     AUD_ADCDAT    = 1'b0;
  end
 
//
// openMSP430 FPGA Instance
//----------------------------------
 
main dut (
 
    ////////////////////////////////    Clock Input          /////////////
    .CLOCK_24     (CLOCK_24),                                     //      24 MHz
    .CLOCK_27     (CLOCK_27),                                     //      27 MHz
    .CLOCK_50     (CLOCK_50),                                     //      50 MHz
    .EXT_CLOCK    (EXT_CLOCK),                                    //      External Clock
    ////////////////////////////////    Push Button          /////////////
    .KEY          (KEY),                                          //      Pushbutton[3:0]
    ////////////////////////////////    DPDT Switch          /////////////
    .SW           (SW),                                           //      Toggle Switch[9:0]
    ////////////////////////////////    7-SEG Dispaly        /////////////
    .HEX0         (HEX0),                                         //      Seven Segment Digit 0
    .HEX1         (HEX1),                                         //      Seven Segment Digit 1
    .HEX2         (HEX2),                                         //      Seven Segment Digit 2
    .HEX3         (HEX3),                                         //      Seven Segment Digit 3
    ////////////////////////////////    LED                  /////////////
    .LEDG         (LEDG),                                         //      LED Green[7:0]
    .LEDR         (LEDR),                                         //      LED Red[9:0]
    ////////////////////////////////    UART                 /////////////
    .UART_TXD     (UART_TXD),                                     //      UART Transmitter
    .UART_RXD     (UART_RXD),                                     //      UART Receiver
    ////////////////////////////////    SDRAM Interface      /////////////
    .DRAM_DQ      (DRAM_DQ),                                      //      SDRAM Data bus 16 Bits
    .DRAM_ADDR    (DRAM_ADDR),                                    //      SDRAM Address bus 12 Bits
    .DRAM_LDQM    (DRAM_LDQM),                                    //      SDRAM Low-byte Data Mask
    .DRAM_UDQM    (DRAM_UDQM),                                    //      SDRAM High-byte Data Mask
    .DRAM_WE_N    (DRAM_WE_N),                                    //      SDRAM Write Enable
    .DRAM_CAS_N   (DRAM_CAS_N),                                   //      SDRAM Column Address Strobe
    .DRAM_RAS_N   (DRAM_RAS_N),                                   //      SDRAM Row Address Strobe
    .DRAM_CS_N    (DRAM_CS_N),                                    //      SDRAM Chip Select
    .DRAM_BA_0    (DRAM_BA_0),                                    //      SDRAM Bank Address 0
    .DRAM_BA_1    (DRAM_BA_1),                                    //      SDRAM Bank Address 0
    .DRAM_CLK     (DRAM_CLK),                                     //      SDRAM Clock
    .DRAM_CKE     (DRAM_CKE),                                     //      SDRAM Clock Enable
    ////////////////////////////////    Flash Interface      /////////////
    .FL_DQ        (FL_DQ),                                        //      FLASH Data bus 8 Bits
    .FL_ADDR      (FL_ADDR),                                      //      FLASH Address bus 22 Bits
    .FL_WE_N      (FL_WE_N),                                      //      FLASH Write Enable
    .FL_RST_N     (FL_RST_N),                                     //      FLASH Reset
    .FL_OE_N      (FL_OE_N),                                      //      FLASH Output Enable
    .FL_CE_N      (FL_CE_N),                                      //      FLASH Chip Enable
    ////////////////////////////////    SRAM Interface       /////////////
    .SRAM_DQ      (SRAM_DQ),                                      //      SRAM Data bus 16 Bits
    .SRAM_ADDR    (SRAM_ADDR),                                    //      SRAM Address bus 18 Bits
    .SRAM_UB_N    (SRAM_UB_N),                                    //      SRAM High-byte Data Mask
    .SRAM_LB_N    (SRAM_LB_N),                                    //      SRAM Low-byte Data Mask
    .SRAM_WE_N    (SRAM_WE_N),                                    //      SRAM Write Enable
    .SRAM_CE_N    (SRAM_CE_N),                                    //      SRAM Chip Enable
    .SRAM_OE_N    (SRAM_OE_N),                                    //      SRAM Output Enable
    ////////////////////////////////    SD_Card Interface    /////////////
    .SD_DAT       (SD_DAT),                                       //      SD Card Data
    .SD_DAT3      (SD_DAT3),                                      //      SD Card Data 3
    .SD_CMD       (SD_CMD),                                       //      SD Card Command Signal
    .SD_CLK       (SD_CLK),                                       //      SD Card Clock
    ///////////////////////////////    USB JTAG link        /////////////
    .TDI          (TDI),                                          //      CPLD -> FPGA (data in)
    .TCK          (TCK),                                          //      CPLD -> FPGA (clk)
    .TCS          (TCS),                                          //      CPLD -> FPGA (CS)
    .TDO          (TDO),                                          //      FPGA -> CPLD (data out)
    ////////////////////////////////    I2C                  /////////////
    .I2C_SDAT     (I2C_SDAT),                                     //      I2C Data
    .I2C_SCLK     (I2C_SCLK),                                     //      I2C Clock
    ////////////////////////////////    PS2                  /////////////
    .PS2_DAT      (PS2_DAT),                                      //      PS2 Data
    .PS2_CLK      (PS2_CLK),                                      //      PS2 Clock
    ////////////////////////////////    VGA                  /////////////
    .VGA_HS       (VGA_HS),                                       //      VGA H_SYNC
    .VGA_VS       (VGA_VS),                                       //      VGA V_SYNC
    .VGA_R        (VGA_R),                                        //      VGA Red[3:0]
    .VGA_G        (VGA_G),                                        //      VGA Green[3:0]
    .VGA_B        (VGA_B),                                        //      VGA Blue[3:0]
    ////////////////////////////////    Audio CODEC          /////////////
    .AUD_ADCLRCK  (AUD_ADCLRCK),                                  //      Audio CODEC ADC LR Clock
    .AUD_ADCDAT   (AUD_ADCDAT),                                   //      Audio CODEC ADC Data
    .AUD_DACLRCK  (AUD_DACLRCK),                                  //      Audio CODEC DAC LR Clock
    .AUD_DACDAT   (AUD_DACDA),                                    //      Audio CODEC DAC Data
    .AUD_BCLK     (AUD_BCLK),                                     //      Audio CODEC Bit-Stream Clock
    .AUD_XCK      (AUD_XCK),                                      //      Audio CODEC Chip Clock
    ////////////////////////////////    GPIO                 /////////////
    .GPIO_0       (GPIO_0),                                       //      GPIO Connection 0
    .GPIO_1       (GPIO_1)                                        //      GPIO Connection 1
);
 
 
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
 
// OUTPUTs
    .e_state      (e_state),       // Execution state
    .i_state      (i_state),       // Instruction fetch state
    .inst_cycle   (inst_cycle),    // Cycle number within current instruction
    .inst_full    (inst_full),     // Currently executed instruction (full version)
    .inst_number  (inst_number),   // Instruction number since last system reset
    .inst_pc      (inst_pc),       // Instruction Program counter
    .inst_short   (inst_short),    // Currently executed instruction (short version)
 
// INPUTs
    .mclk         (mclk),          // Main system clock
    .puc_rst      (puc_rst)        // Main system reset
);
 
//
// Generate Waveform
//----------------------------------------
initial
  begin
   `ifdef VPD_FILE
     $vcdplusfile("tb_openMSP430_fpga.vpd");
     $vcdpluson();
   `else
     `ifdef TRN_FILE
        $recordfile ("tb_openMSP430_fpga.trn");
        $recordvars;
     `else
        $dumpfile("tb_openMSP430_fpga.vcd");
        $dumpvars(0, tb_openMSP430_fpga);
     `endif
   `endif
  end
 
//
// End of simulation
//----------------------------------------
 
initial // Timeout
  begin
     #1000000;
     $display(" ===============================================");
     $display("|               SIMULATION FAILED               |");
     $display("|              (simulation Timeout)             |");
     $display(" ===============================================");
     $finish;
  end
 
initial // Normal end of test
  begin
     @(inst_pc===16'hffff)
     $display(" ===============================================");
     if (error!=0)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (the verilog stimulus didn't complete)    |");
       end
     else
       begin
          $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end
 
 
//
// Tasks Definition
//------------------------------
 
   task tb_error;
      input [65*8:0] error_string;
      begin
         $display("ERROR: %s %t", error_string, $time);
         error = error+1;
      end
   endtask
 
 
endmodule

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 221

Line No.	Rev	Author	Line
1	29	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: tb_openMSP430_fpga.v`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 FPGA testbench`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev: 23 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $`
37			`//----------------------------------------------------------------------------`
38			`include "timescale.v"
39	104	olivier.gi	`ifdef OMSP_NO_INCLUDE
40			`else
41	29	olivier.gi	`include "openMSP430_defines.v"
42	104	olivier.gi	`endif
43	29	olivier.gi
44			`module tb_openMSP430_fpga;`
45
46			`//`
47			`// Wire & Register definition`
48			`//------------------------------`
49
50			`// Clock`
51			`reg [1:0] CLOCK_24;`
52			`reg [1:0] CLOCK_27;`
53			`reg CLOCK_50;`
54			`reg EXT_CLOCK;`
55
56			`// Push Button`
57			`reg [3:0] KEY;`
58
59			`// DPDT Switch`
60			`reg [9:0] SW;`
61
62			`// 7-SEG Dispaly`
63			`wire [6:0] HEX0;`
64			`wire [6:0] HEX1;`
65			`wire [6:0] HEX2;`
66			`wire [6:0] HEX3;`
67
68			`// LED`
69			`wire [7:0] LEDG;`
70			`wire [9:0] LEDR;`
71
72			`// UART`
73			`wire UART_TXD;`
74			`reg UART_RXD;`
75
76			`// SDRAM Interface`
77			`wire [15:0] DRAM_DQ;`
78			`wire [11:0] DRAM_ADDR;`
79			`wire DRAM_LDQM;`
80			`wire DRAM_UDQM;`
81			`wire DRAM_WE_N;`
82			`wire DRAM_CAS_N;`
83			`wire DRAM_RAS_N;`
84			`wire DRAM_CS_N;`
85			`wire DRAM_BA_0;`
86			`wire DRAM_BA_1;`
87			`wire DRAM_CLK;`
88			`wire DRAM_CKE;`
89
90			`// Flash Interface`
91			`wire [7:0] FL_DQ;`
92			`wire [21:0] FL_ADDR;`
93			`wire FL_WE_N;`
94			`wire FL_RST_N;`
95			`wire FL_OE_N;`
96			`wire FL_CE_N;`
97
98			`// SRAM Interface`
99			`wire [15:0] SRAM_DQ;`
100			`wire [17:0] SRAM_ADDR;`
101			`wire SRAM_UB_N;`
102			`wire SRAM_LB_N;`
103			`wire SRAM_WE_N;`
104			`wire SRAM_CE_N;`
105			`wire SRAM_OE_N;`
106
107			`// SD Card Interface`
108			`wire SD_DAT;`
109			`wire SD_DAT3;`
110			`wire SD_CMD;`
111			`wire SD_CLK;`
112
113			`// I2C`
114			`wire I2C_SDAT;`
115			`wire I2C_SCLK;`
116
117			`// PS2`
118			`reg PS2_DAT;`
119			`reg PS2_CLK;`
120
121			`// USB JTAG link`
122			`reg TDI;`
123			`reg TCK;`
124			`reg TCS;`
125			`wire TDO;`
126
127			`// VGA`
128			`wire VGA_HS;`
129			`wire VGA_VS;`
130			`wire [3:0] VGA_R;`
131			`wire [3:0] VGA_G;`
132			`wire [3:0] VGA_B;`
133
134			`// Audio CODEC`
135			`wire AUD_ADCLRCK;`
136			`reg AUD_ADCDAT;`
137			`wire AUD_DACLRCK;`
138			`wire AUD_DACDAT;`
139			`wire AUD_BCLK;`
140			`wire AUD_XCK;`
141
142			`// GPIO`
143			`wire [35:0] GPIO_0;`
144			`wire [35:0] GPIO_1;`
145
146
147			`// Core debug signals`
148			`wire [8*32-1:0] i_state;`
149			`wire [8*32-1:0] e_state;`
150			`wire [31:0] inst_cycle;`
151			`wire [8*32-1:0] inst_full;`
152			`wire [31:0] inst_number;`
153			`wire [15:0] inst_pc;`
154			`wire [8*32-1:0] inst_short;`
155
156			`// Testbench variables`
157			`integer i;`
158			`integer error;`
159			`reg stimulus_done;`
160
161
162			`//`
163			`// Include files`
164			`//------------------------------`
165
166			`// CPU & Memory registers`
167			`include "registers.v"
168
169			`// Verilog stimulus`
170			`include "stimulus.v"
171
172			`//`
173	39	olivier.gi	`// Initialize Program Memory`
174	29	olivier.gi	`//------------------------------`
175
176			`initial`
177			`begin`
178			`// Read memory file`
179	94	olivier.gi	`#10 $readmemh("./pmem.mem", pmem);`
180	29	olivier.gi	`end`
181
182			`//`
183			`// Generate Clock & Reset`
184			`//------------------------------`
185			`initial`
186			`begin`
187			`CLOCK_24 = 2'b10;`
188			`forever #20.8 CLOCK_24 = ~CLOCK_24; // 24 MHz`
189			`end`
190			`initial`
191			`begin`
192			`CLOCK_27 = 2'b01;`
193			`forever #18.5 CLOCK_27 = ~CLOCK_27; // 27 MHz`
194			`end`
195			`initial`
196			`begin`
197			`CLOCK_50 = 1'b0;`
198			`forever #10.0 CLOCK_50 = ~CLOCK_50; // 50 MHz`
199			`end`
200
201			`initial`
202			`begin`
203			`KEY[3] = 1'b1;`
204			`#100 KEY[3] = 1'b0;`
205			`#600 KEY[3] = 1'b1;`
206			`end`
207
208			`//`
209			`// Global initialization`
210			`//------------------------------`
211			`initial`
212			`begin`
213			`error = 0;`
214			`stimulus_done = 1;`
215			`EXT_CLOCK = 1'b0;`
216			`KEY[2:0] = 3'b111;`
217			`SW = 10'h000;`
218			`UART_RXD = 1'b0;`
219			`PS2_DAT = 1'b0;`
220			`PS2_CLK = 1'b0;`
221			`TDI = 1'b0;`
222			`TCK = 1'b0;`
223			`TCS = 1'b0;`
224			`AUD_ADCDAT = 1'b0;`
225			`end`
226
227			`//`
228			`// openMSP430 FPGA Instance`
229			`//----------------------------------`
230
231			`main dut (`
232
233			`//////////////////////////////// Clock Input /////////////`
234			`.CLOCK_24 (CLOCK_24), // 24 MHz`
235			`.CLOCK_27 (CLOCK_27), // 27 MHz`
236			`.CLOCK_50 (CLOCK_50), // 50 MHz`
237			`.EXT_CLOCK (EXT_CLOCK), // External Clock`
238			`//////////////////////////////// Push Button /////////////`
239			`.KEY (KEY), // Pushbutton[3:0]`
240			`//////////////////////////////// DPDT Switch /////////////`
241			`.SW (SW), // Toggle Switch[9:0]`
242			`//////////////////////////////// 7-SEG Dispaly /////////////`
243			`.HEX0 (HEX0), // Seven Segment Digit 0`
244			`.HEX1 (HEX1), // Seven Segment Digit 1`
245			`.HEX2 (HEX2), // Seven Segment Digit 2`
246			`.HEX3 (HEX3), // Seven Segment Digit 3`
247			`//////////////////////////////// LED /////////////`
248			`.LEDG (LEDG), // LED Green[7:0]`
249			`.LEDR (LEDR), // LED Red[9:0]`
250			`//////////////////////////////// UART /////////////`
251			`.UART_TXD (UART_TXD), // UART Transmitter`
252			`.UART_RXD (UART_RXD), // UART Receiver`
253			`//////////////////////////////// SDRAM Interface /////////////`
254			`.DRAM_DQ (DRAM_DQ), // SDRAM Data bus 16 Bits`
255			`.DRAM_ADDR (DRAM_ADDR), // SDRAM Address bus 12 Bits`
256			`.DRAM_LDQM (DRAM_LDQM), // SDRAM Low-byte Data Mask`
257			`.DRAM_UDQM (DRAM_UDQM), // SDRAM High-byte Data Mask`
258			`.DRAM_WE_N (DRAM_WE_N), // SDRAM Write Enable`
259			`.DRAM_CAS_N (DRAM_CAS_N), // SDRAM Column Address Strobe`
260			`.DRAM_RAS_N (DRAM_RAS_N), // SDRAM Row Address Strobe`
261			`.DRAM_CS_N (DRAM_CS_N), // SDRAM Chip Select`
262			`.DRAM_BA_0 (DRAM_BA_0), // SDRAM Bank Address 0`
263			`.DRAM_BA_1 (DRAM_BA_1), // SDRAM Bank Address 0`
264			`.DRAM_CLK (DRAM_CLK), // SDRAM Clock`
265			`.DRAM_CKE (DRAM_CKE), // SDRAM Clock Enable`
266			`//////////////////////////////// Flash Interface /////////////`
267			`.FL_DQ (FL_DQ), // FLASH Data bus 8 Bits`
268			`.FL_ADDR (FL_ADDR), // FLASH Address bus 22 Bits`
269			`.FL_WE_N (FL_WE_N), // FLASH Write Enable`
270			`.FL_RST_N (FL_RST_N), // FLASH Reset`
271			`.FL_OE_N (FL_OE_N), // FLASH Output Enable`
272			`.FL_CE_N (FL_CE_N), // FLASH Chip Enable`
273			`//////////////////////////////// SRAM Interface /////////////`
274			`.SRAM_DQ (SRAM_DQ), // SRAM Data bus 16 Bits`
275			`.SRAM_ADDR (SRAM_ADDR), // SRAM Address bus 18 Bits`
276			`.SRAM_UB_N (SRAM_UB_N), // SRAM High-byte Data Mask`
277			`.SRAM_LB_N (SRAM_LB_N), // SRAM Low-byte Data Mask`
278			`.SRAM_WE_N (SRAM_WE_N), // SRAM Write Enable`
279			`.SRAM_CE_N (SRAM_CE_N), // SRAM Chip Enable`
280			`.SRAM_OE_N (SRAM_OE_N), // SRAM Output Enable`
281			`//////////////////////////////// SD_Card Interface /////////////`
282			`.SD_DAT (SD_DAT), // SD Card Data`
283			`.SD_DAT3 (SD_DAT3), // SD Card Data 3`
284			`.SD_CMD (SD_CMD), // SD Card Command Signal`
285			`.SD_CLK (SD_CLK), // SD Card Clock`
286			`/////////////////////////////// USB JTAG link /////////////`
287			`.TDI (TDI), // CPLD -> FPGA (data in)`
288			`.TCK (TCK), // CPLD -> FPGA (clk)`
289			`.TCS (TCS), // CPLD -> FPGA (CS)`
290			`.TDO (TDO), // FPGA -> CPLD (data out)`
291			`//////////////////////////////// I2C /////////////`
292			`.I2C_SDAT (I2C_SDAT), // I2C Data`
293			`.I2C_SCLK (I2C_SCLK), // I2C Clock`
294			`//////////////////////////////// PS2 /////////////`
295			`.PS2_DAT (PS2_DAT), // PS2 Data`
296			`.PS2_CLK (PS2_CLK), // PS2 Clock`
297			`//////////////////////////////// VGA /////////////`
298			`.VGA_HS (VGA_HS), // VGA H_SYNC`
299			`.VGA_VS (VGA_VS), // VGA V_SYNC`
300			`.VGA_R (VGA_R), // VGA Red[3:0]`
301			`.VGA_G (VGA_G), // VGA Green[3:0]`
302			`.VGA_B (VGA_B), // VGA Blue[3:0]`
303			`//////////////////////////////// Audio CODEC /////////////`
304			`.AUD_ADCLRCK (AUD_ADCLRCK), // Audio CODEC ADC LR Clock`
305			`.AUD_ADCDAT (AUD_ADCDAT), // Audio CODEC ADC Data`
306			`.AUD_DACLRCK (AUD_DACLRCK), // Audio CODEC DAC LR Clock`
307			`.AUD_DACDAT (AUD_DACDA), // Audio CODEC DAC Data`
308			`.AUD_BCLK (AUD_BCLK), // Audio CODEC Bit-Stream Clock`
309			`.AUD_XCK (AUD_XCK), // Audio CODEC Chip Clock`
310			`//////////////////////////////// GPIO /////////////`
311			`.GPIO_0 (GPIO_0), // GPIO Connection 0`
312			`.GPIO_1 (GPIO_1) // GPIO Connection 1`
313			`);`
314
315
316			`//`
317			`// Debug utility signals`
318			`//----------------------------------------`
319			`msp_debug msp_debug_0 (`
320
321			`// OUTPUTs`
322			`.e_state (e_state), // Execution state`
323			`.i_state (i_state), // Instruction fetch state`
324			`.inst_cycle (inst_cycle), // Cycle number within current instruction`
325			`.inst_full (inst_full), // Currently executed instruction (full version)`
326			`.inst_number (inst_number), // Instruction number since last system reset`
327			`.inst_pc (inst_pc), // Instruction Program counter`
328			`.inst_short (inst_short), // Currently executed instruction (short version)`
329
330			`// INPUTs`
331			`.mclk (mclk), // Main system clock`
332	111	olivier.gi	`.puc_rst (puc_rst) // Main system reset`
333	29	olivier.gi	`);`
334
335			`//`
336			`// Generate Waveform`
337			`//----------------------------------------`
338			`initial`
339			`begin`
340			`ifdef VPD_FILE
341			`$vcdplusfile("tb_openMSP430_fpga.vpd");`
342			`$vcdpluson();`
343			`else
344	98	olivier.gi	`ifdef TRN_FILE
345			`$recordfile ("tb_openMSP430_fpga.trn");`
346			`$recordvars;`
347			`else
348			`$dumpfile("tb_openMSP430_fpga.vcd");`
349			`$dumpvars(0, tb_openMSP430_fpga);`
350			`endif
351	29	olivier.gi	`endif
352			`end`
353
354			`//`
355			`// End of simulation`
356			`//----------------------------------------`
357
358			`initial // Timeout`
359			`begin`
360	143	olivier.gi	`#1000000;`
361	29	olivier.gi	`$display(" ===============================================");`
362			`$display("\| SIMULATION FAILED \|");`
363			`$display("\| (simulation Timeout) \|");`
364			`$display(" ===============================================");`
365			`$finish;`
366			`end`
367
368			`initial // Normal end of test`
369			`begin`
370			`@(inst_pc===16'hffff)`
371			`$display(" ===============================================");`
372			`if (error!=0)`
373			`begin`
374			`$display("\| SIMULATION FAILED \|");`
375			`$display("\| (some verilog stimulus checks failed) \|");`
376			`end`
377			`else if (~stimulus_done)`
378			`begin`
379			`$display("\| SIMULATION FAILED \|");`
380			`$display("\| (the verilog stimulus didn't complete) \|");`
381			`end`
382			`else`
383			`begin`
384			`$display("\| SIMULATION PASSED \|");`
385			`end`
386			`$display(" ===============================================");`
387			`$finish;`
388			`end`
389
390
391			`//`
392			`// Tasks Definition`
393			`//------------------------------`
394
395			`task tb_error;`
396			`input [65*8:0] error_string;`
397			`begin`
398			`$display("ERROR: %s %t", error_string, $time);`
399			`error = error+1;`
400			`end`
401			`endtask`
402
403
404			`endmodule`