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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [registers.v] - Blame information for rev 179

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Line No. Rev Author Line
1 80 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: registers.v
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//
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// *Module Description:
28 136 olivier.gi 
//                      Direct connections to internal registers & memory.
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//
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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// CPU registers
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//======================
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wire       [15:0] r0    = dut.openMSP430_0.execution_unit_0.register_file_0.r0;
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wire       [15:0] r1    = dut.openMSP430_0.execution_unit_0.register_file_0.r1;
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wire       [15:0] r2    = dut.openMSP430_0.execution_unit_0.register_file_0.r2;
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wire       [15:0] r3    = dut.openMSP430_0.execution_unit_0.register_file_0.r3;
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wire       [15:0] r4    = dut.openMSP430_0.execution_unit_0.register_file_0.r4;
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wire       [15:0] r5    = dut.openMSP430_0.execution_unit_0.register_file_0.r5;
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wire       [15:0] r6    = dut.openMSP430_0.execution_unit_0.register_file_0.r6;
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wire       [15:0] r7    = dut.openMSP430_0.execution_unit_0.register_file_0.r7;
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wire       [15:0] r8    = dut.openMSP430_0.execution_unit_0.register_file_0.r8;
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wire       [15:0] r9    = dut.openMSP430_0.execution_unit_0.register_file_0.r9;
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wire       [15:0] r10   = dut.openMSP430_0.execution_unit_0.register_file_0.r10;
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wire       [15:0] r11   = dut.openMSP430_0.execution_unit_0.register_file_0.r11;
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wire       [15:0] r12   = dut.openMSP430_0.execution_unit_0.register_file_0.r12;
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wire       [15:0] r13   = dut.openMSP430_0.execution_unit_0.register_file_0.r13;
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wire       [15:0] r14   = dut.openMSP430_0.execution_unit_0.register_file_0.r14;
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wire       [15:0] r15   = dut.openMSP430_0.execution_unit_0.register_file_0.r15;
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60 
 
61 
// Data Memory cells
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//======================
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64 
wire       [15:0] mem200 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[0],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[0]};
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wire       [15:0] mem202 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[1],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[1]};
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wire       [15:0] mem204 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[2],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[2]};
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wire       [15:0] mem206 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[3],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[3]};
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wire       [15:0] mem208 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[4],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[4]};
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wire       [15:0] mem20A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[5],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[5]};
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wire       [15:0] mem20C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[6],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[6]};
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wire       [15:0] mem20E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[7],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[7]};
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wire       [15:0] mem210 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[8],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[8]};
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wire       [15:0] mem212 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[9],  dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[9]};
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wire       [15:0] mem214 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[10], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[10]};
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wire       [15:0] mem216 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[11], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[11]};
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wire       [15:0] mem218 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[12], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[12]};
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wire       [15:0] mem21A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[13], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[13]};
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wire       [15:0] mem21C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[14], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[14]};
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wire       [15:0] mem21E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[15], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[15]};
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wire       [15:0] mem220 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[16], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[16]};
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wire       [15:0] mem222 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[17], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[17]};
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wire       [15:0] mem224 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[18], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[18]};
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wire       [15:0] mem226 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[19], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[19]};
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wire       [15:0] mem228 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[20], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[20]};
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wire       [15:0] mem22A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[21], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[21]};
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wire       [15:0] mem22C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[22], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[22]};
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wire       [15:0] mem22E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[23], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[23]};
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wire       [15:0] mem230 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[24], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[24]};
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wire       [15:0] mem232 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[25], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[25]};
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wire       [15:0] mem234 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[26], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[26]};
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wire       [15:0] mem236 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[27], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[27]};
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wire       [15:0] mem238 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[28], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[28]};
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wire       [15:0] mem23A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[29], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[29]};
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wire       [15:0] mem23C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[30], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[30]};
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wire       [15:0] mem23E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[31], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[31]};
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wire       [15:0] mem240 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[32], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[32]};
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wire       [15:0] mem242 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[33], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[33]};
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wire       [15:0] mem244 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[34], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[34]};
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wire       [15:0] mem246 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[35], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[35]};
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wire       [15:0] mem248 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[36], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[36]};
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wire       [15:0] mem24A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[37], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[37]};
102 
wire       [15:0] mem24C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[38], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[38]};
103 
wire       [15:0] mem24E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[39], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[39]};
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wire       [15:0] mem250 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[40], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[40]};
105 
wire       [15:0] mem252 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[41], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[41]};
106 
wire       [15:0] mem254 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[42], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[42]};
107 
wire       [15:0] mem256 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[43], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[43]};
108 
wire       [15:0] mem258 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[44], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[44]};
109 
wire       [15:0] mem25A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[45], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[45]};
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wire       [15:0] mem25C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[46], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[46]};
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wire       [15:0] mem25E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[47], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[47]};
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wire       [15:0] mem260 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[48], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[48]};
113 
wire       [15:0] mem262 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[49], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[49]};
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wire       [15:0] mem264 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[50], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[50]};
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wire       [15:0] mem266 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[51], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[51]};
116 
wire       [15:0] mem268 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[52], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[52]};
117 
wire       [15:0] mem26A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[53], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[53]};
118 
wire       [15:0] mem26C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[54], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[54]};
119 
wire       [15:0] mem26E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[55], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[55]};
120 
wire       [15:0] mem270 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[56], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[56]};
121 
wire       [15:0] mem272 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[57], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[57]};
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wire       [15:0] mem274 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[58], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[58]};
123 
wire       [15:0] mem276 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[59], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[59]};
124 
wire       [15:0] mem278 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[60], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[60]};
125 
wire       [15:0] mem27A = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[61], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[61]};
126 
wire       [15:0] mem27C = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[62], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[62]};
127 
wire       [15:0] mem27E = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[63], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[63]};
128 
wire       [15:0] mem280 = {dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[64], dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[64]};
129 
 
130 
 
131 
// Program Memory cells
132 
//======================
133 143 olivier.gi 
reg   [15:0] pmem [0:2047];
134 80 olivier.gi 
 
135 
// Interrupt vectors
136 
wire  [15:0] irq_vect_15 = pmem[(1<<(`PMEM_MSB+1))-1];  // RESET Vector
137 
wire  [15:0] irq_vect_14 = pmem[(1<<(`PMEM_MSB+1))-2];  // NMI
138 
wire  [15:0] irq_vect_13 = pmem[(1<<(`PMEM_MSB+1))-3];  // IRQ 13
139 
wire  [15:0] irq_vect_12 = pmem[(1<<(`PMEM_MSB+1))-4];  // IRQ 12
140 
wire  [15:0] irq_vect_11 = pmem[(1<<(`PMEM_MSB+1))-5];  // IRQ 11
141 
wire  [15:0] irq_vect_10 = pmem[(1<<(`PMEM_MSB+1))-6];  // IRQ 10
142 
wire  [15:0] irq_vect_09 = pmem[(1<<(`PMEM_MSB+1))-7];  // IRQ  9
143 
wire  [15:0] irq_vect_08 = pmem[(1<<(`PMEM_MSB+1))-8];  // IRQ  8
144 
wire  [15:0] irq_vect_07 = pmem[(1<<(`PMEM_MSB+1))-9];  // IRQ  7
145 
wire  [15:0] irq_vect_06 = pmem[(1<<(`PMEM_MSB+1))-10]; // IRQ  6
146 
wire  [15:0] irq_vect_05 = pmem[(1<<(`PMEM_MSB+1))-11]; // IRQ  5
147 
wire  [15:0] irq_vect_04 = pmem[(1<<(`PMEM_MSB+1))-12]; // IRQ  4
148 
wire  [15:0] irq_vect_03 = pmem[(1<<(`PMEM_MSB+1))-13]; // IRQ  3
149 
wire  [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ  2
150 
wire  [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ  1
151 
wire  [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ  0
152 
 
153 
 
154 136 olivier.gi 
// Interrupt detection
155 
wire              nmi_detect  = dut.openMSP430_0.frontend_0.nmi_pnd;
156 
wire              irq_detect  = dut.openMSP430_0.frontend_0.irq_detect;
157 
 
158 
// Debug interface
159 
wire              dbg_en      = dut.openMSP430_0.dbg_en;
160 
wire              dbg_clk     = dut.openMSP430_0.clock_module_0.dbg_clk;
161 
wire              dbg_rst     = dut.openMSP430_0.clock_module_0.dbg_rst;
162 
 
163 
 
164 80 olivier.gi 
// CPU internals
165 
//======================
166 
 
167 111 olivier.gi 
wire mclk     = dut.openMSP430_0.mclk;
168 
wire puc_rst  = dut.openMSP430_0.puc_rst;

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