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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 136

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1 80 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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// 
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// *File Name: tb_openMSP430_fpga.v
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// 
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// *Module Description:
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//                      openMSP430 FPGA testbench
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`else
41 80 olivier.gi
`include "openMSP430_defines.v"
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`endif
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module  tb_openMSP430_fpga;
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//
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// Wire & Register definition
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//------------------------------
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// Clock & Reset
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reg               oscclk;
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reg               porst_n;
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reg               pbrst_n;
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// Slide Switches
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reg         [9:0] switch;
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// LEDs
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wire        [9:0] led;
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// UART
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wire              dbg_uart_rxd;
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wire              dbg_uart_txd;
64 136 olivier.gi
reg               dbg_uart_rxd_sel;
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reg               dbg_uart_rxd_dly;
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reg               dbg_uart_rxd_pre;
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reg               dbg_uart_rxd_meta;
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reg        [15:0] dbg_uart_buf;
69 136 olivier.gi
reg               dbg_uart_rx_busy;
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reg               dbg_uart_tx_busy;
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// Core debug signals
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wire   [8*32-1:0] i_state;
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wire   [8*32-1:0] e_state;
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wire       [31:0] inst_cycle;
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wire   [8*32-1:0] inst_full;
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wire       [31:0] inst_number;
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wire       [15:0] inst_pc;
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wire   [8*32-1:0] inst_short;
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// Testbench variables
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integer           i;
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integer           error;
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reg               stimulus_done;
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wire       [11:0] vout_x;
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wire       [11:0] vout_y;
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//
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// Include files
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//------------------------------
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92
// CPU & Memory registers
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`include "registers.v"
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// Debug interface tasks
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`include "dbg_uart_tasks.v"
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98 80 olivier.gi
// Verilog stimulus
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`include "stimulus.v"
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101
//
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// Initialize Program Memory
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//------------------------------
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105
initial
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   begin
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      // Read memory file
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      #10 $readmemh("./pmem.mem", pmem);
109 80 olivier.gi
 
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      // Update Actel memory banks
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      for (i=0; i<512; i=i+1)
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        begin
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           dut.dmem_hi.dmem_128B_R0C0.MEM_512_9[i] = {1'b0, 8'h00};
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           dut.dmem_lo.dmem_128B_R0C0.MEM_512_9[i] = {1'b0, 8'h00};
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           dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[i] = {1'b0, pmem[i*4+3][9:8],   pmem[i*4+2][9:8],   pmem[i*4+1][9:8],   pmem[i*4+0][9:8]};
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           dut.pmem_hi.pmem_2kB_R0C1.MEM_512_9[i] = {1'b0, pmem[i*4+3][11:10], pmem[i*4+2][11:10], pmem[i*4+1][11:10], pmem[i*4+0][11:10]};
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           dut.pmem_hi.pmem_2kB_R0C2.MEM_512_9[i] = {1'b0, pmem[i*4+3][13:12], pmem[i*4+2][13:12], pmem[i*4+1][13:12], pmem[i*4+0][13:12]};
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           dut.pmem_hi.pmem_2kB_R0C3.MEM_512_9[i] = {1'b0, pmem[i*4+3][15:14], pmem[i*4+2][15:14], pmem[i*4+1][15:14], pmem[i*4+0][15:14]};
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           dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[i] = {1'b0, pmem[i*4+3][1:0],   pmem[i*4+2][1:0],   pmem[i*4+1][1:0],   pmem[i*4+0][1:0]};
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           dut.pmem_lo.pmem_2kB_R0C1.MEM_512_9[i] = {1'b0, pmem[i*4+3][3:2],   pmem[i*4+2][3:2],   pmem[i*4+1][3:2],   pmem[i*4+0][3:2]};
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           dut.pmem_lo.pmem_2kB_R0C2.MEM_512_9[i] = {1'b0, pmem[i*4+3][5:4],   pmem[i*4+2][5:4],   pmem[i*4+1][5:4],   pmem[i*4+0][5:4]};
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           dut.pmem_lo.pmem_2kB_R0C3.MEM_512_9[i] = {1'b0, pmem[i*4+3][7:6],   pmem[i*4+2][7:6],   pmem[i*4+1][7:6],   pmem[i*4+0][7:6]};
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        end
126
  end
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128
//
129
// Generate Clock & Reset
130
//------------------------------
131
initial
132
  begin
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     oscclk = 1'b0;
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     forever #10.4 oscclk <= ~oscclk; // 48 MHz
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  end
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initial
138
  begin
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     porst_n       = 1'b1;
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     pbrst_n       = 1'b1;
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     #100;
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     porst_n       = 1'b0;
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     pbrst_n       = 1'b0;
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     #600;
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     porst_n       = 1'b1;
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     pbrst_n       = 1'b1;
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  end
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149
//
150
// Global initialization
151
//------------------------------
152
initial
153
  begin
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     error            = 0;
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     stimulus_done    = 1;
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     switch           = 10'h000;
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     dbg_uart_rxd_sel = 1'b0;
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     dbg_uart_rxd_dly = 1'b1;
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     dbg_uart_rxd_pre = 1'b1;
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     dbg_uart_rxd_meta= 1'b0;
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     dbg_uart_rx_busy = 1'b0;
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     dbg_uart_tx_busy = 1'b0;
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  end
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165
//
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// openMSP430 FPGA Instance
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//----------------------------------
168
 
169
openMSP430_fpga dut (
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171
// OUTPUTs
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    .din_x        (din_x),          // SPI Serial Data
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    .din_y        (din_y),          // SPI Serial Data
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    .led          (led),            // Board LEDs
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    .sclk_x       (sclk_x),         // SPI Serial Clock
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    .sclk_y       (sclk_y),         // SPI Serial Clock
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    .sync_n_x     (sync_n_x),       // SPI Frame synchronization signal (low active)
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    .sync_n_y     (sync_n_y),       // SPI Frame synchronization signal (low active)
179 107 olivier.gi
    .uart_tx      (dbg_uart_txd),   // Board UART TX pin
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// INPUTs
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    .oscclk       (oscclk),         // Board Oscillator (?? MHz)
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    .porst_n      (porst_n),        // Board Power-On reset (active low)
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    .pbrst_n      (pbrst_n),        // Board Push-Button reset (active low)
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    .uart_rx      (dbg_uart_rxd),   // Board UART RX pin
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    .switch       (switch)          // Board Switches
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);
188
 
189
 
190
//
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// 12 BIT DACs
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//----------------------------------------
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DAC121S101 DAC121S101_x (
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// OUTPUTs
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    .vout         (vout_x),        // Peripheral data output
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// INPUTs
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    .din          (din_x),         // SPI Serial Data
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    .sclk         (sclk_x),        // SPI Serial Clock
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    .sync_n       (sync_n_x)       // SPI Frame synchronization signal (low active)
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);
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DAC121S101 DAC121S101_y (
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// OUTPUTs
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    .vout         (vout_y),        // Peripheral data output
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// INPUTs
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    .din          (din_y),         // SPI Serial Data
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    .sclk         (sclk_y),        // SPI Serial Clock
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    .sync_n       (sync_n_y)       // SPI Frame synchronization signal (low active)
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);
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//
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// Debug utility signals
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//----------------------------------------
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msp_debug msp_debug_0 (
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// OUTPUTs
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    .e_state      (e_state),       // Execution state
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    .i_state      (i_state),       // Instruction fetch state
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    .inst_cycle   (inst_cycle),    // Cycle number within current instruction
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    .inst_full    (inst_full),     // Currently executed instruction (full version)
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    .inst_number  (inst_number),   // Instruction number since last system reset
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    .inst_pc      (inst_pc),       // Instruction Program counter
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    .inst_short   (inst_short),    // Currently executed instruction (short version)
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// INPUTs
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    .mclk         (mclk),          // Main system clock
233 111 olivier.gi
    .puc_rst      (puc_rst)        // Main system reset
234 80 olivier.gi
);
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//
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// Generate Waveform
238
//----------------------------------------
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initial
240
  begin
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   `ifdef VPD_FILE
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     $vcdplusfile("tb_openMSP430_fpga.vpd");
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     $vcdpluson();
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   `else
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     `ifdef TRN_FILE
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        $recordfile ("tb_openMSP430_fpga.trn");
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        $recordvars;
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     `else
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        $dumpfile("tb_openMSP430_fpga.vcd");
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        $dumpvars(0, tb_openMSP430_fpga);
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     `endif
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   `endif
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  end
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//
256
// End of simulation
257
//----------------------------------------
258
 
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initial // Timeout
260
  begin
261
     #500000;
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     $display(" ===============================================");
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     $display("|               SIMULATION FAILED               |");
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     $display("|              (simulation Timeout)             |");
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     $display(" ===============================================");
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     $finish;
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  end
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initial // Normal end of test
270
  begin
271
     @(inst_pc===16'hffff)
272
     $display(" ===============================================");
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     if (error!=0)
274
       begin
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          $display("|               SIMULATION FAILED               |");
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          $display("|     (some verilog stimulus checks failed)     |");
277
       end
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     else if (~stimulus_done)
279
       begin
280
          $display("|               SIMULATION FAILED               |");
281
          $display("|     (the verilog stimulus didn't complete)    |");
282
       end
283
     else
284
       begin
285
          $display("|               SIMULATION PASSED               |");
286
       end
287
     $display(" ===============================================");
288
     $finish;
289
  end
290
 
291
 
292
//
293
// Tasks Definition
294
//------------------------------
295
 
296
   task tb_error;
297
      input [65*8:0] error_string;
298
      begin
299
         $display("ERROR: %s %t", error_string, $time);
300
         error = error+1;
301
      end
302
   endtask
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304
 
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endmodule

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