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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openMSP430_fpga.v] - Blame information for rev 143

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1 80 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
// 
25
// *File Name: openMSP430_fpga.v
26
// 
27
// *Module Description:
28
//                      openMSP430 FPGA Top-level
29
//                      (targeting an Actel ProASIC3L).
30
//
31
// *Author(s):
32
//              - Olivier Girard,    olgirard@gmail.com
33
//
34
//----------------------------------------------------------------------------
35
// $Rev: 37 $
36
// $LastChangedBy: olivier.girard $
37
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
38
//----------------------------------------------------------------------------
39
`include "openMSP430_defines.v"
40
 
41
module openMSP430_fpga (
42
 
43
// OUTPUTs
44
    din_x,                        // SPI Serial Data
45
    din_y,                        // SPI Serial Data
46
    led,                          // Board LEDs
47
    sclk_x,                       // SPI Serial Clock
48
    sclk_y,                       // SPI Serial Clock
49
    sync_n_x,                     // SPI Frame synchronization signal (low active)
50
    sync_n_y,                     // SPI Frame synchronization signal (low active)
51
    uart_tx,                      // Board UART TX pin
52
 
53
// INPUTs
54
    oscclk,                       // Board Oscillator (?? MHz)
55
    porst_n,                      // Board Power-On reset (active low)
56
    pbrst_n,                      // Board Push-Button reset (active low)
57
    uart_rx,                      // Board UART RX pin
58
    switch                        // Board Switches
59
);
60
 
61
// OUTPUTs
62
//=========
63
output              din_x;        // SPI Serial Data
64
output              din_y;        // SPI Serial Data
65
output        [9:0] led;          // Board LEDs
66
output              sclk_x;       // SPI Serial Clock
67
output              sclk_y;       // SPI Serial Clock
68
output              sync_n_x;     // SPI Frame synchronization signal (low active)
69
output              sync_n_y;     // SPI Frame synchronization signal (low active)
70
output              uart_tx;      // Board UART TX pin
71
 
72
// INPUTs
73
//=========
74
input               oscclk;       // Board Oscillator (?? MHz)
75
input               porst_n;      // Board Power-On reset (active low)
76
input               pbrst_n;      // Board Push-Button reset (active low)
77
input               uart_rx;      // Board UART RX pin
78
input         [9:0] switch;       // Board Switches
79
 
80
 
81
//=============================================================================
82
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
83
//=============================================================================
84
 
85
wire  [`DMEM_MSB:0] dmem_addr;
86
wire                dmem_cen;
87
wire         [15:0] dmem_din;
88
wire          [1:0] dmem_wen;
89
wire         [15:0] dmem_dout;
90
 
91
wire  [`PMEM_MSB:0] pmem_addr;
92
wire                pmem_cen;
93
wire         [15:0] pmem_din;
94
wire          [1:0] pmem_wen;
95
wire         [15:0] pmem_dout;
96
 
97 111 olivier.gi
wire         [13:0] per_addr;
98 80 olivier.gi
wire         [15:0] per_din;
99
wire                per_en;
100 107 olivier.gi
wire          [1:0] per_we;
101 80 olivier.gi
wire         [15:0] per_dout;
102
 
103
wire         [13:0] irq_acc;
104
wire         [13:0] irq_bus;
105
wire                lfxt_clk;
106
wire                nmi;
107
wire                reset_n;
108
 
109
wire                dco_clk;
110
wire                mclk;
111 111 olivier.gi
wire                puc_rst;
112 80 olivier.gi
 
113
wire          [7:0] p1_din;
114
wire          [7:0] p1_dout;
115
wire          [7:0] p1_dout_en;
116
wire          [7:0] p1_sel;
117
wire         [15:0] per_dout_dio;
118
 
119
wire         [15:0] per_dout_tA;
120
 
121
wire          [3:0] cntrl1;
122
wire          [3:0] cntrl2;
123
wire         [15:0] per_dout_dac_x;
124
wire         [15:0] per_dout_dac_y;
125
 
126
 
127
//=============================================================================
128
// 2)  PLL & CLOCK GENERATION
129
//=============================================================================
130
 
131
// Input clock buffer
132
PLLINT clk_in0 (.A(oscclk), .Y(oscclk_buf));
133
 
134
 
135
parameter  FCLKA  = 48.0;
136 81 olivier.gi
parameter  M      = 7'd6;
137
parameter  N      = 7'd9;
138
parameter  U      = 5'd2;
139 80 olivier.gi
parameter  V      = 5'd1;
140
parameter  W      = 5'd1;
141
 
142 81 olivier.gi
parameter  FVCO   = FCLKA*M/N;  //  32 MHz
143 80 olivier.gi
parameter  FGLA   = FVCO/U;     //  16 MHz
144 81 olivier.gi
parameter  FGLB   = FVCO/V;     //  32 MHz
145
parameter  FGLC   = FVCO/W;     //  32 MHz
146 80 olivier.gi
 
147
wire [4:0] oadiv  = U-5'h01;
148
wire [4:0] obdiv  = V-5'h01;
149
wire [4:0] ocdiv  = W-5'h01;
150
wire [6:0] findiv = N-7'h01;
151
wire [6:0] fbdiv  = M-7'h01;
152
 
153
PLL #(.VCOFREQUENCY(FVCO))  pll_0 (
154
 
155
// PLL Inputs
156
    .CLKA         (oscclk_buf),   // Reference Clock Input
157
    .EXTFB        (1'b0),         // External Feedback
158
    .POWERDOWN    (1'b1),         // Power-Down (active low)
159
 
160
// PLL Outputs
161
    .GLA          (dco_clk),      // Primary output
162
    .LOCK         (lock),         // PLL Lock Indicator
163
    .GLB          (glb),          // Secondary 1 output
164
    .YB           (yb),           // Core 1 output
165
    .GLC          (glc),          // Secondary 2 output
166
    .YC           (yc),           // Core 2 output
167
 
168
// GLA Configuration
169
    .OADIV0       (oadiv[0]),     // Primary output divider (divider is oadiv+1)
170
    .OADIV1       (oadiv[1]),
171
    .OADIV2       (oadiv[2]),
172
    .OADIV3       (oadiv[3]),
173
    .OADIV4       (oadiv[4]),
174
 
175
    .OAMUX0       (1'b0),         // Primary output select (selects from the VCO's four phases)
176
    .OAMUX1       (1'b0),
177
    .OAMUX2       (1'b1),
178
 
179
    .DLYGLA0      (1'b0),         // Primary output delay
180
    .DLYGLA1      (1'b0),
181
    .DLYGLA2      (1'b0),
182
    .DLYGLA3      (1'b0),
183
    .DLYGLA4      (1'b0),
184
 
185
// GLB/YB configuration
186
    .OBDIV0       (obdiv[0]),     // Secondary 1 output divider (divider is obdiv+1)
187
    .OBDIV1       (obdiv[1]),
188
    .OBDIV2       (obdiv[2]),
189
    .OBDIV3       (obdiv[3]),
190
    .OBDIV4       (obdiv[4]),
191
 
192
    .OBMUX0       (1'b1),         // Secondary 1 output select (selects from the VCO's four phases)
193
    .OBMUX1       (1'b0),
194
    .OBMUX2       (1'b1),
195
 
196
    .DLYYB0       (1'b0),         // Secondary 1 YB output delay
197
    .DLYYB1       (1'b0),
198
    .DLYYB2       (1'b0),
199
    .DLYYB3       (1'b0),
200
    .DLYYB4       (1'b0),
201
 
202
    .DLYGLB0      (1'b0),         // Secondary 1 GLB output delay
203
    .DLYGLB1      (1'b0),
204
    .DLYGLB2      (1'b0),
205
    .DLYGLB3      (1'b0),
206
    .DLYGLB4      (1'b0),
207
 
208
// GLC/YC configuration
209
    .OCDIV0       (ocdiv[0]),     // Secondary 2 output divider (divider is ocdiv+1)
210
    .OCDIV1       (ocdiv[1]),
211
    .OCDIV2       (ocdiv[2]),
212
    .OCDIV3       (ocdiv[3]),
213
    .OCDIV4       (ocdiv[4]),
214
 
215
    .OCMUX0       (1'b0),         // Secondary 2 output select (selects from the VCO's four phases)
216
    .OCMUX1       (1'b0),
217
    .OCMUX2       (1'b1),
218
 
219
    .DLYYC0       (1'b0),         // Secondary 2 YC output delay
220
    .DLYYC1       (1'b0),
221
    .DLYYC2       (1'b0),
222
    .DLYYC3       (1'b0),
223
    .DLYYC4       (1'b0),
224
 
225
    .DLYGLC0      (1'b0),         // Secondary 2 GLC output delay
226
    .DLYGLC1      (1'b0),
227
    .DLYGLC2      (1'b0),
228
    .DLYGLC3      (1'b0),
229
    .DLYGLC4      (1'b0),
230
 
231
// PLL Core configuration
232
    .FINDIV0      (findiv[0]),    // Input clock divider (divider is findiv+1)
233
    .FINDIV1      (findiv[1]),
234
    .FINDIV2      (findiv[2]),
235
    .FINDIV3      (findiv[3]),
236
    .FINDIV4      (findiv[4]),
237
    .FINDIV5      (findiv[5]),
238
    .FINDIV6      (findiv[6]),
239
 
240
    .FBDIV0       (fbdiv[0]),     // Feedback clock divider (divider is fbdiv+1)
241
    .FBDIV1       (fbdiv[1]),
242
    .FBDIV2       (fbdiv[2]),
243
    .FBDIV3       (fbdiv[3]),
244
    .FBDIV4       (fbdiv[4]),
245
    .FBDIV5       (fbdiv[5]),
246
    .FBDIV6       (fbdiv[6]),
247
 
248
    .FBDLY0       (1'b0),         // Feedback Delay
249
    .FBDLY1       (1'b0),
250
    .FBDLY2       (1'b0),
251
    .FBDLY3       (1'b0),
252
    .FBDLY4       (1'b0),
253
 
254
    .FBSEL0       (1'b1),         // Primary feedback delay select (0:no dly; 1:prog dly element; 2:external feedback)
255
    .FBSEL1       (1'b0),
256
 
257
    .XDLYSEL      (1'b0),         // System Delay Select (0: no dly; 1:inserts system dly)
258
 
259 81 olivier.gi
    .VCOSEL0      (1'b1),         // PLL lock acquisition time (0: Fast with high tracking jitter; 1: Slow with low tracking jitter)
260
 
261
    .VCOSEL1      (1'b1),         // VCO gear control (see table below)
262
    .VCOSEL2      (1'b0)
263 80 olivier.gi
);
264
 
265 81 olivier.gi
//-------------+--------------------------------------------------------------+
266
//             |                           VCOSEL[2:1]                        |
267
//             |---------------+---------------+--------------+---------------|
268
//             |       00      |       01      |       10     |       11      |
269
//  VOLTAGE    |---------------+---------------+--------------+---------------|
270
//             |   Min.  Max.  |   Min.  Max.  |   Min.  Max. |   Min.  Max.  |
271
//             |  (MHz) (MHz)  |  (MHz) (MHz)  |  (MHz) (MHz) |  (MHz) (MHz)  |
272
//-------------+---------------+---------------+--------------+---------------|
273
// IGLOO and IGLOO PLUS                                                       |
274
//-------------+---------------+---------------+--------------+---------------|
275 82 olivier.gi
// 1.2 V +- 5% |   24    35    |   30     70   |   60    140  |   135   160   |
276
// 1.5 V +- 5% |   24    43.75 |   30     87.5 |   60    175  |   135   250   |
277 81 olivier.gi
//-------------+---------------+---------------+--------------+---------------|
278
// ProASIC3L, RT ProASIC3, and Military ProASIC3/L                            |
279
//-------------+---------------+---------------+--------------+---------------|
280 82 olivier.gi
// 1.2 V +- 5% |   24    35    |    30    70   |   60    140  |   135   250   |
281
// 1.5 V +- 5% |   24    43.75 |    30    70   |   60    175  |   135   350   |
282 81 olivier.gi
//-------------+---------------+---------------+--------------+---------------|
283
// ProASIC3 and Fusion                                                        |
284
//-------------+---------------+---------------+--------------+---------------|
285 82 olivier.gi
// 1.5 V +- 5% |   24    43.75 |    33.75 87.5 |  67.5   175  |   135   350   |
286 81 olivier.gi
//-------------+---------------+---------------+--------------+---------------+
287
 
288 80 olivier.gi
 
289
//=============================================================================
290
// 3)  PROGRAM AND DATA MEMORIES
291
//=============================================================================
292
 
293 111 olivier.gi
dmem_128B dmem_hi (.WD(dmem_din[15:8]), .RD(dmem_dout[15:8]), .WEN(dmem_wen[1] | dmem_cen), .REN(~dmem_wen[1] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
294
dmem_128B dmem_lo (.WD(dmem_din[7:0]),  .RD(dmem_dout[7:0]),  .WEN(dmem_wen[0] | dmem_cen), .REN(~dmem_wen[0] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
295 80 olivier.gi
 
296 111 olivier.gi
pmem_2kB  pmem_hi (.WD(pmem_din[15:8]), .RD(pmem_dout[15:8]), .WEN(pmem_wen[1] | pmem_cen), .REN(~pmem_wen[1] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
297
pmem_2kB  pmem_lo (.WD(pmem_din[7:0]),  .RD(pmem_dout[7:0]),  .WEN(pmem_wen[0] | pmem_cen), .REN(~pmem_wen[0] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
298 80 olivier.gi
 
299
 
300
//=============================================================================
301
// 4)  OPENMSP430
302
//=============================================================================
303
 
304
openMSP430 openMSP430_0 (
305
 
306
// OUTPUTs
307 136 olivier.gi
    .aclk         (),             // ASIC ONLY: ACLK
308
    .aclk_en      (aclk_en),      // FPGA ONLY: ACLK enable
309 80 olivier.gi
    .dbg_freeze   (dbg_freeze),   // Freeze peripherals
310
    .dbg_uart_txd (uart_tx),      // Debug interface: UART TXD
311 136 olivier.gi
    .dco_enable   (),             // ASIC ONLY: Fast oscillator enable
312
    .dco_wkup     (),             // ASIC ONLY: Fast oscillator wake-up (asynchronous)
313 80 olivier.gi
    .dmem_addr    (dmem_addr),    // Data Memory address
314
    .dmem_cen     (dmem_cen),     // Data Memory chip enable (low active)
315
    .dmem_din     (dmem_din),     // Data Memory data input
316
    .dmem_wen     (dmem_wen),     // Data Memory write enable (low active)
317
    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)
318 136 olivier.gi
    .lfxt_enable  (),             // ASIC ONLY: Low frequency oscillator enable
319
    .lfxt_wkup    (),             // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
320 80 olivier.gi
    .mclk         (mclk),         // Main system clock
321
    .per_addr     (per_addr),     // Peripheral address
322
    .per_din      (per_din),      // Peripheral data input
323 107 olivier.gi
    .per_we       (per_we),       // Peripheral write enable (high active)
324 80 olivier.gi
    .per_en       (per_en),       // Peripheral enable (high active)
325
    .pmem_addr    (pmem_addr),    // Program Memory address
326
    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)
327
    .pmem_din     (pmem_din),     // Program Memory data input (optional)
328
    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)
329 111 olivier.gi
    .puc_rst      (puc_rst),      // Main system reset
330 136 olivier.gi
    .smclk        (),             // ASIC ONLY: SMCLK
331
    .smclk_en     (smclk_en),     // FPGA ONLY: SMCLK enable
332 80 olivier.gi
 
333
// INPUTs
334 136 olivier.gi
    .cpu_en       (1'b1),         // Enable CPU code execution (asynchronous and non-glitchy)
335
    .dbg_en       (1'b1),         // Debug interface enable (asynchronous and non-glitchy)
336
    .dbg_uart_rxd (uart_rx),      // Debug interface: UART RXD (asynchronous)
337 80 olivier.gi
    .dco_clk      (dco_clk),      // Fast oscillator (fast clock)
338
    .dmem_dout    (dmem_dout),    // Data Memory data output
339
    .irq          (irq_bus),      // Maskable interrupts
340
    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)
341
    .nmi          (nmi),          // Non-maskable interrupt (asynchronous)
342
    .per_dout     (per_dout),     // Peripheral data output
343
    .pmem_dout    (pmem_dout),    // Program Memory data output
344 136 olivier.gi
    .reset_n      (reset_n),      // Reset Pin (low active, asynchronous and non-glitchy)
345
    .scan_enable  (1'b0),         // ASIC ONLY: Scan enable (active during scan shifting)
346
    .scan_mode    (1'b0),         // ASIC ONLY: Scan mode
347
    .wkup         (1'b0)          // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
348 80 olivier.gi
);
349
 
350
 
351
//=============================================================================
352
// 5)  OPENMSP430 PERIPHERALS
353
//=============================================================================
354
 
355
//
356
// SPI Interface for the 12 bit DACs
357
//-----------------------------------
358
 
359
dac_spi_if #(1, 9'h190) dac_spi_if_x (
360
 
361
// OUTPUTs
362
    .cntrl1       (cntrl1),         // Control value 1
363
    .cntrl2       (cntrl2),         // Control value 2
364
    .din          (din_x),          // SPI Serial Data
365
    .per_dout     (per_dout_dac_x), // Peripheral data output
366
    .sclk         (sclk_x),         // SPI Serial Clock
367
    .sync_n       (sync_n_x),       // SPI Frame synchronization signal (low active)
368
 
369
// INPUTs
370
    .mclk         (mclk),           // Main system clock
371
    .per_addr     (per_addr),       // Peripheral address
372
    .per_din      (per_din),        // Peripheral data input
373
    .per_en       (per_en),         // Peripheral enable (high active)
374 107 olivier.gi
    .per_we       (per_we),         // Peripheral write enable (high active)
375 111 olivier.gi
    .puc_rst      (puc_rst)         // Main system reset
376 80 olivier.gi
);
377
 
378
dac_spi_if #(1, 9'h1A0) dac_spi_if_y (
379
 
380
// OUTPUTs
381
    .cntrl1       (),               // Control value 1
382
    .cntrl2       (),               // Control value 2
383
    .din          (din_y),          // SPI Serial Data
384
    .per_dout     (per_dout_dac_y), // Peripheral data output
385
    .sclk         (sclk_y),         // SPI Serial Clock
386
    .sync_n       (sync_n_y),       // SPI Frame synchronization signal (low active)
387
 
388
// INPUTs
389
    .mclk         (mclk),           // Main system clock
390
    .per_addr     (per_addr),       // Peripheral address
391
    .per_din      (per_din),        // Peripheral data input
392
    .per_en       (per_en),         // Peripheral enable (high active)
393 107 olivier.gi
    .per_we       (per_we),         // Peripheral write enable (high active)
394 111 olivier.gi
    .puc_rst      (puc_rst)         // Main system reset
395 80 olivier.gi
);
396
 
397
//
398
// Digital I/O
399
//-------------------------------
400
 
401
omsp_gpio #(.P1_EN(1),
402
            .P2_EN(0),
403
            .P3_EN(0),
404
            .P4_EN(0),
405
            .P5_EN(0),
406
            .P6_EN(0)) gpio_0 (
407
 
408
// OUTPUTs
409
    .irq_port1    (irq_port1),     // Port 1 interrupt
410
    .irq_port2    (),              // Port 2 interrupt
411
    .p1_dout      (p1_dout),       // Port 1 data output
412
    .p1_dout_en   (p1_dout_en),    // Port 1 data output enable
413
    .p1_sel       (p1_sel),        // Port 1 function select
414
    .p2_dout      (),              // Port 2 data output
415
    .p2_dout_en   (),              // Port 2 data output enable
416
    .p2_sel       (),              // Port 2 function select
417
    .p3_dout      (),              // Port 3 data output
418
    .p3_dout_en   (),              // Port 3 data output enable
419
    .p3_sel       (),              // Port 3 function select
420
    .p4_dout      (),              // Port 4 data output
421
    .p4_dout_en   (),              // Port 4 data output enable
422
    .p4_sel       (),              // Port 4 function select
423
    .p5_dout      (),              // Port 5 data output
424
    .p5_dout_en   (),              // Port 5 data output enable
425
    .p5_sel       (),              // Port 5 function select
426
    .p6_dout      (),              // Port 6 data output
427
    .p6_dout_en   (),              // Port 6 data output enable
428
    .p6_sel       (),              // Port 6 function select
429
    .per_dout     (per_dout_dio),  // Peripheral data output
430
 
431
// INPUTs
432
    .mclk         (mclk),          // Main system clock
433
    .p1_din       (p1_din),        // Port 1 data input
434
    .p2_din       (8'h00),         // Port 2 data input
435
    .p3_din       (8'h00),         // Port 3 data input
436
    .p4_din       (8'h00),         // Port 4 data input
437
    .p5_din       (8'h00),         // Port 5 data input
438
    .p6_din       (8'h00),         // Port 6 data input
439
    .per_addr     (per_addr),      // Peripheral address
440
    .per_din      (per_din),       // Peripheral data input
441
    .per_en       (per_en),        // Peripheral enable (high active)
442 107 olivier.gi
    .per_we       (per_we),        // Peripheral write enable (high active)
443 111 olivier.gi
    .puc_rst      (puc_rst)        // Main system reset
444 80 olivier.gi
);
445
 
446
//
447
// Timer A
448
//----------------------------------------------
449
 
450
omsp_timerA timerA_0 (
451
 
452
// OUTPUTs
453
    .irq_ta0      (irq_ta0),       // Timer A interrupt: TACCR0
454
    .irq_ta1      (irq_ta1),       // Timer A interrupt: TAIV, TACCR1, TACCR2
455
    .per_dout     (per_dout_tA),   // Peripheral data output
456
    .ta_out0      (ta_out0),       // Timer A output 0
457
    .ta_out0_en   (ta_out0_en),    // Timer A output 0 enable
458
    .ta_out1      (ta_out1),       // Timer A output 1
459
    .ta_out1_en   (ta_out1_en),    // Timer A output 1 enable
460
    .ta_out2      (ta_out2),       // Timer A output 2
461
    .ta_out2_en   (ta_out2_en),    // Timer A output 2 enable
462
 
463
// INPUTs
464
    .aclk_en      (aclk_en),       // ACLK enable (from CPU)
465
    .dbg_freeze   (dbg_freeze),    // Freeze Timer A counter
466
    .inclk        (1'b0),          // INCLK external timer clock (SLOW)
467
    .irq_ta0_acc  (irq_acc[9]),    // Interrupt request TACCR0 accepted
468
    .mclk         (mclk),          // Main system clock
469
    .per_addr     (per_addr),      // Peripheral address
470
    .per_din      (per_din),       // Peripheral data input
471
    .per_en       (per_en),        // Peripheral enable (high active)
472 107 olivier.gi
    .per_we       (per_we),        // Peripheral write enable (high active)
473 111 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
474 80 olivier.gi
    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)
475
    .ta_cci0a     (1'b0),          // Timer A capture 0 input A
476
    .ta_cci0b     (1'b0),          // Timer A capture 0 input B
477
    .ta_cci1a     (1'b0),          // Timer A capture 1 input A
478
    .ta_cci1b     (1'b0),          // Timer A capture 1 input B
479
    .ta_cci2a     (1'b0),          // Timer A capture 2 input A
480
    .ta_cci2b     (1'b0),          // Timer A capture 2 input B
481
    .taclk        (1'b0)           // TACLK external timer clock (SLOW)
482
);
483
 
484
//
485
// Combine peripheral data buses
486
//-------------------------------
487
 
488
assign per_dout = per_dout_dio   |
489
                  per_dout_tA    |
490
                  per_dout_dac_x |
491
                  per_dout_dac_y;
492
 
493
//
494
// Assign interrupts
495
//-------------------------------
496
 
497
assign nmi        =  1'b0;
498
assign irq_bus    = {1'b0,         // Vector 13  (0xFFFA)
499
                     1'b0,         // Vector 12  (0xFFF8)
500
                     1'b0,         // Vector 11  (0xFFF6)
501
                     1'b0,         // Vector 10  (0xFFF4) - Watchdog -
502
                     irq_ta0,      // Vector  9  (0xFFF2)
503
                     irq_ta1,      // Vector  8  (0xFFF0)
504
                     1'b0,         // Vector  7  (0xFFEE)
505
                     1'b0,         // Vector  6  (0xFFEC)
506
                     1'b0,         // Vector  5  (0xFFEA)
507
                     1'b0,         // Vector  4  (0xFFE8)
508
                     1'b0,         // Vector  3  (0xFFE6)
509
                     irq_port1,    // Vector  2  (0xFFE4)
510
                     1'b0,         // Vector  1  (0xFFE2)
511
                     1'b0};        // Vector  0  (0xFFE0)
512
 
513
//
514
// Diverse
515
//-------------------------------
516
 
517
assign  reset_n =  (porst_n & pbrst_n);
518
 
519
assign  p1_din  =  8'h00;
520
 
521 82 olivier.gi
assign  led     =  {cntrl1, p1_dout[0], p1_dout[0], cntrl2};
522 80 olivier.gi
 
523
 
524
endmodule // openMSP430_fpga
525
 

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