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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_fpga.v
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//
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// *Module Description:
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// openMSP430 FPGA Top-level
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// (targeting an Actel ProASIC3L).
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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`include "openMSP430_defines.v"
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module openMSP430_fpga (
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// OUTPUTs
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din_x, // SPI Serial Data
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din_y, // SPI Serial Data
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led, // Board LEDs
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sclk_x, // SPI Serial Clock
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sclk_y, // SPI Serial Clock
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sync_n_x, // SPI Frame synchronization signal (low active)
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sync_n_y, // SPI Frame synchronization signal (low active)
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uart_tx, // Board UART TX pin
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// INPUTs
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oscclk, // Board Oscillator (?? MHz)
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porst_n, // Board Power-On reset (active low)
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pbrst_n, // Board Push-Button reset (active low)
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uart_rx, // Board UART RX pin
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switch // Board Switches
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);
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// OUTPUTs
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//=========
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output din_x; // SPI Serial Data
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output din_y; // SPI Serial Data
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output [9:0] led; // Board LEDs
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output sclk_x; // SPI Serial Clock
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output sclk_y; // SPI Serial Clock
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output sync_n_x; // SPI Frame synchronization signal (low active)
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output sync_n_y; // SPI Frame synchronization signal (low active)
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output uart_tx; // Board UART TX pin
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// INPUTs
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//=========
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input oscclk; // Board Oscillator (?? MHz)
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input porst_n; // Board Power-On reset (active low)
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input pbrst_n; // Board Push-Button reset (active low)
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input uart_rx; // Board UART RX pin
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input [9:0] switch; // Board Switches
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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wire [`DMEM_MSB:0] dmem_addr;
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wire dmem_cen;
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wire [15:0] dmem_din;
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wire [1:0] dmem_wen;
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wire [15:0] dmem_dout;
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wire [`PMEM_MSB:0] pmem_addr;
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wire pmem_cen;
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wire [15:0] pmem_din;
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wire [1:0] pmem_wen;
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wire [15:0] pmem_dout;
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wire [13:0] per_addr;
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wire [15:0] per_din;
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wire per_en;
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wire [1:0] per_we;
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wire [15:0] per_dout;
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wire [13:0] irq_acc;
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wire [13:0] irq_bus;
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wire lfxt_clk;
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wire nmi;
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wire reset_n;
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wire dco_clk;
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wire mclk;
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wire puc_rst;
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wire [7:0] p1_din;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout_en;
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wire [7:0] p1_sel;
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wire [15:0] per_dout_dio;
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wire [15:0] per_dout_tA;
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wire [3:0] cntrl1;
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wire [3:0] cntrl2;
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wire [15:0] per_dout_dac_x;
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wire [15:0] per_dout_dac_y;
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//=============================================================================
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// 2) PLL & CLOCK GENERATION
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//=============================================================================
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// Input clock buffer
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PLLINT clk_in0 (.A(oscclk), .Y(oscclk_buf));
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parameter FCLKA = 48.0;
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parameter M = 7'd6;
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parameter N = 7'd9;
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parameter U = 5'd2;
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parameter V = 5'd1;
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parameter W = 5'd1;
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parameter FVCO = FCLKA*M/N; // 32 MHz
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parameter FGLA = FVCO/U; // 16 MHz
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parameter FGLB = FVCO/V; // 32 MHz
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parameter FGLC = FVCO/W; // 32 MHz
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wire [4:0] oadiv = U-5'h01;
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wire [4:0] obdiv = V-5'h01;
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wire [4:0] ocdiv = W-5'h01;
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wire [6:0] findiv = N-7'h01;
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wire [6:0] fbdiv = M-7'h01;
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PLL #(.VCOFREQUENCY(FVCO)) pll_0 (
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// PLL Inputs
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.CLKA (oscclk_buf), // Reference Clock Input
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.EXTFB (1'b0), // External Feedback
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.POWERDOWN (1'b1), // Power-Down (active low)
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// PLL Outputs
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.GLA (dco_clk), // Primary output
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.LOCK (lock), // PLL Lock Indicator
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.GLB (glb), // Secondary 1 output
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.YB (yb), // Core 1 output
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.GLC (glc), // Secondary 2 output
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.YC (yc), // Core 2 output
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// GLA Configuration
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.OADIV0 (oadiv[0]), // Primary output divider (divider is oadiv+1)
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.OADIV1 (oadiv[1]),
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.OADIV2 (oadiv[2]),
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.OADIV3 (oadiv[3]),
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.OADIV4 (oadiv[4]),
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.OAMUX0 (1'b0), // Primary output select (selects from the VCO's four phases)
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.OAMUX1 (1'b0),
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.OAMUX2 (1'b1),
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.DLYGLA0 (1'b0), // Primary output delay
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.DLYGLA1 (1'b0),
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.DLYGLA2 (1'b0),
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.DLYGLA3 (1'b0),
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.DLYGLA4 (1'b0),
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// GLB/YB configuration
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.OBDIV0 (obdiv[0]), // Secondary 1 output divider (divider is obdiv+1)
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.OBDIV1 (obdiv[1]),
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.OBDIV2 (obdiv[2]),
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.OBDIV3 (obdiv[3]),
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.OBDIV4 (obdiv[4]),
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.OBMUX0 (1'b1), // Secondary 1 output select (selects from the VCO's four phases)
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.OBMUX1 (1'b0),
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.OBMUX2 (1'b1),
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.DLYYB0 (1'b0), // Secondary 1 YB output delay
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.DLYYB1 (1'b0),
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.DLYYB2 (1'b0),
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.DLYYB3 (1'b0),
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.DLYYB4 (1'b0),
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.DLYGLB0 (1'b0), // Secondary 1 GLB output delay
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.DLYGLB1 (1'b0),
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.DLYGLB2 (1'b0),
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.DLYGLB3 (1'b0),
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.DLYGLB4 (1'b0),
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// GLC/YC configuration
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.OCDIV0 (ocdiv[0]), // Secondary 2 output divider (divider is ocdiv+1)
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.OCDIV1 (ocdiv[1]),
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.OCDIV2 (ocdiv[2]),
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.OCDIV3 (ocdiv[3]),
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.OCDIV4 (ocdiv[4]),
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.OCMUX0 (1'b0), // Secondary 2 output select (selects from the VCO's four phases)
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.OCMUX1 (1'b0),
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.OCMUX2 (1'b1),
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.DLYYC0 (1'b0), // Secondary 2 YC output delay
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.DLYYC1 (1'b0),
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.DLYYC2 (1'b0),
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.DLYYC3 (1'b0),
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.DLYYC4 (1'b0),
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.DLYGLC0 (1'b0), // Secondary 2 GLC output delay
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.DLYGLC1 (1'b0),
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.DLYGLC2 (1'b0),
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.DLYGLC3 (1'b0),
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.DLYGLC4 (1'b0),
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// PLL Core configuration
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.FINDIV0 (findiv[0]), // Input clock divider (divider is findiv+1)
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.FINDIV1 (findiv[1]),
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.FINDIV2 (findiv[2]),
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.FINDIV3 (findiv[3]),
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.FINDIV4 (findiv[4]),
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.FINDIV5 (findiv[5]),
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.FINDIV6 (findiv[6]),
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.FBDIV0 (fbdiv[0]), // Feedback clock divider (divider is fbdiv+1)
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.FBDIV1 (fbdiv[1]),
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.FBDIV2 (fbdiv[2]),
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.FBDIV3 (fbdiv[3]),
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.FBDIV4 (fbdiv[4]),
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.FBDIV5 (fbdiv[5]),
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.FBDIV6 (fbdiv[6]),
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.FBDLY0 (1'b0), // Feedback Delay
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.FBDLY1 (1'b0),
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.FBDLY2 (1'b0),
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.FBDLY3 (1'b0),
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.FBDLY4 (1'b0),
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.FBSEL0 (1'b1), // Primary feedback delay select (0:no dly; 1:prog dly element; 2:external feedback)
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.FBSEL1 (1'b0),
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.XDLYSEL (1'b0), // System Delay Select (0: no dly; 1:inserts system dly)
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.VCOSEL0 (1'b1), // PLL lock acquisition time (0: Fast with high tracking jitter; 1: Slow with low tracking jitter)
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.VCOSEL1 (1'b1), // VCO gear control (see table below)
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.VCOSEL2 (1'b0)
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);
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//-------------+--------------------------------------------------------------+
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// | VCOSEL[2:1] |
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// |---------------+---------------+--------------+---------------|
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// | 00 | 01 | 10 | 11 |
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// VOLTAGE |---------------+---------------+--------------+---------------|
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// | Min. Max. | Min. Max. | Min. Max. | Min. Max. |
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// | (MHz) (MHz) | (MHz) (MHz) | (MHz) (MHz) | (MHz) (MHz) |
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//-------------+---------------+---------------+--------------+---------------|
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// IGLOO and IGLOO PLUS |
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//-------------+---------------+---------------+--------------+---------------|
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// 1.2 V +- 5% | 24 35 | 30 70 | 60 140 | 135 160 |
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// 1.5 V +- 5% | 24 43.75 | 30 87.5 | 60 175 | 135 250 |
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//-------------+---------------+---------------+--------------+---------------|
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// ProASIC3L, RT ProASIC3, and Military ProASIC3/L |
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//-------------+---------------+---------------+--------------+---------------|
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// 1.2 V +- 5% | 24 35 | 30 70 | 60 140 | 135 250 |
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// 1.5 V +- 5% | 24 43.75 | 30 70 | 60 175 | 135 350 |
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//-------------+---------------+---------------+--------------+---------------|
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// ProASIC3 and Fusion |
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//-------------+---------------+---------------+--------------+---------------|
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// 1.5 V +- 5% | 24 43.75 | 33.75 87.5 | 67.5 175 | 135 350 |
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//-------------+---------------+---------------+--------------+---------------+
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//=============================================================================
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// 3) PROGRAM AND DATA MEMORIES
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//=============================================================================
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dmem_128B dmem_hi (.WD(dmem_din[15:8]), .RD(dmem_dout[15:8]), .WEN(dmem_wen[1] | dmem_cen), .REN(~dmem_wen[1] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
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dmem_128B dmem_lo (.WD(dmem_din[7:0]), .RD(dmem_dout[7:0]), .WEN(dmem_wen[0] | dmem_cen), .REN(~dmem_wen[0] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
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pmem_2kB pmem_hi (.WD(pmem_din[15:8]), .RD(pmem_dout[15:8]), .WEN(pmem_wen[1] | pmem_cen), .REN(~pmem_wen[1] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
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pmem_2kB pmem_lo (.WD(pmem_din[7:0]), .RD(pmem_dout[7:0]), .WEN(pmem_wen[0] | pmem_cen), .REN(~pmem_wen[0] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
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//=============================================================================
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// 4) OPENMSP430
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//=============================================================================
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openMSP430 openMSP430_0 (
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// OUTPUTs
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.aclk (), // ASIC ONLY: ACLK
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_uart_txd (uart_tx), // Debug interface: UART TXD
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.dco_enable (), // ASIC ONLY: Fast oscillator enable
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.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
315 |
|
|
.dmem_din (dmem_din), // Data Memory data input
|
316 |
|
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
317 |
|
|
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
|
318 |
136 |
olivier.gi |
.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
|
319 |
|
|
.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
320 |
80 |
olivier.gi |
.mclk (mclk), // Main system clock
|
321 |
|
|
.per_addr (per_addr), // Peripheral address
|
322 |
|
|
.per_din (per_din), // Peripheral data input
|
323 |
107 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
324 |
80 |
olivier.gi |
.per_en (per_en), // Peripheral enable (high active)
|
325 |
|
|
.pmem_addr (pmem_addr), // Program Memory address
|
326 |
|
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
327 |
|
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
328 |
|
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
329 |
111 |
olivier.gi |
.puc_rst (puc_rst), // Main system reset
|
330 |
136 |
olivier.gi |
.smclk (), // ASIC ONLY: SMCLK
|
331 |
|
|
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
|
332 |
80 |
olivier.gi |
|
333 |
|
|
// INPUTs
|
334 |
136 |
olivier.gi |
.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
|
335 |
|
|
.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
|
336 |
|
|
.dbg_uart_rxd (uart_rx), // Debug interface: UART RXD (asynchronous)
|
337 |
80 |
olivier.gi |
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
338 |
|
|
.dmem_dout (dmem_dout), // Data Memory data output
|
339 |
|
|
.irq (irq_bus), // Maskable interrupts
|
340 |
|
|
.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
|
341 |
|
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
342 |
|
|
.per_dout (per_dout), // Peripheral data output
|
343 |
|
|
.pmem_dout (pmem_dout), // Program Memory data output
|
344 |
136 |
olivier.gi |
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
|
345 |
|
|
.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
|
346 |
|
|
.scan_mode (1'b0), // ASIC ONLY: Scan mode
|
347 |
|
|
.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
|
348 |
80 |
olivier.gi |
);
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
//=============================================================================
|
352 |
|
|
// 5) OPENMSP430 PERIPHERALS
|
353 |
|
|
//=============================================================================
|
354 |
|
|
|
355 |
|
|
//
|
356 |
|
|
// SPI Interface for the 12 bit DACs
|
357 |
|
|
//-----------------------------------
|
358 |
|
|
|
359 |
|
|
dac_spi_if #(1, 9'h190) dac_spi_if_x (
|
360 |
|
|
|
361 |
|
|
// OUTPUTs
|
362 |
|
|
.cntrl1 (cntrl1), // Control value 1
|
363 |
|
|
.cntrl2 (cntrl2), // Control value 2
|
364 |
|
|
.din (din_x), // SPI Serial Data
|
365 |
|
|
.per_dout (per_dout_dac_x), // Peripheral data output
|
366 |
|
|
.sclk (sclk_x), // SPI Serial Clock
|
367 |
|
|
.sync_n (sync_n_x), // SPI Frame synchronization signal (low active)
|
368 |
|
|
|
369 |
|
|
// INPUTs
|
370 |
|
|
.mclk (mclk), // Main system clock
|
371 |
|
|
.per_addr (per_addr), // Peripheral address
|
372 |
|
|
.per_din (per_din), // Peripheral data input
|
373 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
374 |
107 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
375 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
376 |
80 |
olivier.gi |
);
|
377 |
|
|
|
378 |
|
|
dac_spi_if #(1, 9'h1A0) dac_spi_if_y (
|
379 |
|
|
|
380 |
|
|
// OUTPUTs
|
381 |
|
|
.cntrl1 (), // Control value 1
|
382 |
|
|
.cntrl2 (), // Control value 2
|
383 |
|
|
.din (din_y), // SPI Serial Data
|
384 |
|
|
.per_dout (per_dout_dac_y), // Peripheral data output
|
385 |
|
|
.sclk (sclk_y), // SPI Serial Clock
|
386 |
|
|
.sync_n (sync_n_y), // SPI Frame synchronization signal (low active)
|
387 |
|
|
|
388 |
|
|
// INPUTs
|
389 |
|
|
.mclk (mclk), // Main system clock
|
390 |
|
|
.per_addr (per_addr), // Peripheral address
|
391 |
|
|
.per_din (per_din), // Peripheral data input
|
392 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
393 |
107 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
394 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
395 |
80 |
olivier.gi |
);
|
396 |
|
|
|
397 |
|
|
//
|
398 |
|
|
// Digital I/O
|
399 |
|
|
//-------------------------------
|
400 |
|
|
|
401 |
|
|
omsp_gpio #(.P1_EN(1),
|
402 |
|
|
.P2_EN(0),
|
403 |
|
|
.P3_EN(0),
|
404 |
|
|
.P4_EN(0),
|
405 |
|
|
.P5_EN(0),
|
406 |
|
|
.P6_EN(0)) gpio_0 (
|
407 |
|
|
|
408 |
|
|
// OUTPUTs
|
409 |
|
|
.irq_port1 (irq_port1), // Port 1 interrupt
|
410 |
|
|
.irq_port2 (), // Port 2 interrupt
|
411 |
|
|
.p1_dout (p1_dout), // Port 1 data output
|
412 |
|
|
.p1_dout_en (p1_dout_en), // Port 1 data output enable
|
413 |
|
|
.p1_sel (p1_sel), // Port 1 function select
|
414 |
|
|
.p2_dout (), // Port 2 data output
|
415 |
|
|
.p2_dout_en (), // Port 2 data output enable
|
416 |
|
|
.p2_sel (), // Port 2 function select
|
417 |
|
|
.p3_dout (), // Port 3 data output
|
418 |
|
|
.p3_dout_en (), // Port 3 data output enable
|
419 |
|
|
.p3_sel (), // Port 3 function select
|
420 |
|
|
.p4_dout (), // Port 4 data output
|
421 |
|
|
.p4_dout_en (), // Port 4 data output enable
|
422 |
|
|
.p4_sel (), // Port 4 function select
|
423 |
|
|
.p5_dout (), // Port 5 data output
|
424 |
|
|
.p5_dout_en (), // Port 5 data output enable
|
425 |
|
|
.p5_sel (), // Port 5 function select
|
426 |
|
|
.p6_dout (), // Port 6 data output
|
427 |
|
|
.p6_dout_en (), // Port 6 data output enable
|
428 |
|
|
.p6_sel (), // Port 6 function select
|
429 |
|
|
.per_dout (per_dout_dio), // Peripheral data output
|
430 |
|
|
|
431 |
|
|
// INPUTs
|
432 |
|
|
.mclk (mclk), // Main system clock
|
433 |
|
|
.p1_din (p1_din), // Port 1 data input
|
434 |
|
|
.p2_din (8'h00), // Port 2 data input
|
435 |
|
|
.p3_din (8'h00), // Port 3 data input
|
436 |
|
|
.p4_din (8'h00), // Port 4 data input
|
437 |
|
|
.p5_din (8'h00), // Port 5 data input
|
438 |
|
|
.p6_din (8'h00), // Port 6 data input
|
439 |
|
|
.per_addr (per_addr), // Peripheral address
|
440 |
|
|
.per_din (per_din), // Peripheral data input
|
441 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
442 |
107 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
443 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
444 |
80 |
olivier.gi |
);
|
445 |
|
|
|
446 |
|
|
//
|
447 |
|
|
// Timer A
|
448 |
|
|
//----------------------------------------------
|
449 |
|
|
|
450 |
|
|
omsp_timerA timerA_0 (
|
451 |
|
|
|
452 |
|
|
// OUTPUTs
|
453 |
|
|
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
|
454 |
|
|
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
|
455 |
|
|
.per_dout (per_dout_tA), // Peripheral data output
|
456 |
|
|
.ta_out0 (ta_out0), // Timer A output 0
|
457 |
|
|
.ta_out0_en (ta_out0_en), // Timer A output 0 enable
|
458 |
|
|
.ta_out1 (ta_out1), // Timer A output 1
|
459 |
|
|
.ta_out1_en (ta_out1_en), // Timer A output 1 enable
|
460 |
|
|
.ta_out2 (ta_out2), // Timer A output 2
|
461 |
|
|
.ta_out2_en (ta_out2_en), // Timer A output 2 enable
|
462 |
|
|
|
463 |
|
|
// INPUTs
|
464 |
|
|
.aclk_en (aclk_en), // ACLK enable (from CPU)
|
465 |
|
|
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
|
466 |
|
|
.inclk (1'b0), // INCLK external timer clock (SLOW)
|
467 |
|
|
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
|
468 |
|
|
.mclk (mclk), // Main system clock
|
469 |
|
|
.per_addr (per_addr), // Peripheral address
|
470 |
|
|
.per_din (per_din), // Peripheral data input
|
471 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
472 |
107 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
473 |
111 |
olivier.gi |
.puc_rst (puc_rst), // Main system reset
|
474 |
80 |
olivier.gi |
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
475 |
|
|
.ta_cci0a (1'b0), // Timer A capture 0 input A
|
476 |
|
|
.ta_cci0b (1'b0), // Timer A capture 0 input B
|
477 |
|
|
.ta_cci1a (1'b0), // Timer A capture 1 input A
|
478 |
|
|
.ta_cci1b (1'b0), // Timer A capture 1 input B
|
479 |
|
|
.ta_cci2a (1'b0), // Timer A capture 2 input A
|
480 |
|
|
.ta_cci2b (1'b0), // Timer A capture 2 input B
|
481 |
|
|
.taclk (1'b0) // TACLK external timer clock (SLOW)
|
482 |
|
|
);
|
483 |
|
|
|
484 |
|
|
//
|
485 |
|
|
// Combine peripheral data buses
|
486 |
|
|
//-------------------------------
|
487 |
|
|
|
488 |
|
|
assign per_dout = per_dout_dio |
|
489 |
|
|
per_dout_tA |
|
490 |
|
|
per_dout_dac_x |
|
491 |
|
|
per_dout_dac_y;
|
492 |
|
|
|
493 |
|
|
//
|
494 |
|
|
// Assign interrupts
|
495 |
|
|
//-------------------------------
|
496 |
|
|
|
497 |
|
|
assign nmi = 1'b0;
|
498 |
|
|
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
|
499 |
|
|
1'b0, // Vector 12 (0xFFF8)
|
500 |
|
|
1'b0, // Vector 11 (0xFFF6)
|
501 |
|
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
502 |
|
|
irq_ta0, // Vector 9 (0xFFF2)
|
503 |
|
|
irq_ta1, // Vector 8 (0xFFF0)
|
504 |
|
|
1'b0, // Vector 7 (0xFFEE)
|
505 |
|
|
1'b0, // Vector 6 (0xFFEC)
|
506 |
|
|
1'b0, // Vector 5 (0xFFEA)
|
507 |
|
|
1'b0, // Vector 4 (0xFFE8)
|
508 |
|
|
1'b0, // Vector 3 (0xFFE6)
|
509 |
|
|
irq_port1, // Vector 2 (0xFFE4)
|
510 |
|
|
1'b0, // Vector 1 (0xFFE2)
|
511 |
|
|
1'b0}; // Vector 0 (0xFFE0)
|
512 |
|
|
|
513 |
|
|
//
|
514 |
|
|
// Diverse
|
515 |
|
|
//-------------------------------
|
516 |
|
|
|
517 |
|
|
assign reset_n = (porst_n & pbrst_n);
|
518 |
|
|
|
519 |
|
|
assign p1_din = 8'h00;
|
520 |
|
|
|
521 |
82 |
olivier.gi |
assign led = {cntrl1, p1_dout[0], p1_dout[0], cntrl2};
|
522 |
80 |
olivier.gi |
|
523 |
|
|
|
524 |
|
|
endmodule // openMSP430_fpga
|
525 |
|
|
|