OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_hwbrk.v] - Blame information for rev 218

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 80 olivier.gi
//----------------------------------------------------------------------------
2 136 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 80 olivier.gi
//
4 136 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15 80 olivier.gi
//
16 136 olivier.gi
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27 80 olivier.gi
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_dbg_hwbrk.v
31 202 olivier.gi
//
32 80 olivier.gi
// *Module Description:
33
//                       Hardware Breakpoint / Watchpoint module
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39 202 olivier.gi
// $Rev$
40
// $LastChangedBy$
41
// $LastChangedDate$
42 80 olivier.gi
//----------------------------------------------------------------------------
43 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
44
`else
45 80 olivier.gi
`include "openMSP430_defines.v"
46 104 olivier.gi
`endif
47 80 olivier.gi
 
48
module  omsp_dbg_hwbrk (
49
 
50
// OUTPUTs
51
    brk_halt,                // Hardware breakpoint command
52
    brk_pnd,                 // Hardware break/watch-point pending
53
    brk_dout,                // Hardware break/watch-point register data input
54 202 olivier.gi
 
55 80 olivier.gi
// INPUTs
56
    brk_reg_rd,              // Hardware break/watch-point register read select
57
    brk_reg_wr,              // Hardware break/watch-point register write select
58 107 olivier.gi
    dbg_clk,                 // Debug unit clock
59 80 olivier.gi
    dbg_din,                 // Debug register data input
60 107 olivier.gi
    dbg_rst,                 // Debug unit reset
61 176 olivier.gi
    decode_noirq,            // Frontend decode instruction
62 80 olivier.gi
    eu_mab,                  // Execution-Unit Memory address bus
63
    eu_mb_en,                // Execution-Unit Memory bus enable
64
    eu_mb_wr,                // Execution-Unit Memory bus write transfer
65 107 olivier.gi
    pc                       // Program counter
66 80 olivier.gi
);
67
 
68
// OUTPUTs
69
//=========
70
output         brk_halt;     // Hardware breakpoint command
71
output         brk_pnd;      // Hardware break/watch-point pending
72
output  [15:0] brk_dout;     // Hardware break/watch-point register data input
73
 
74
// INPUTs
75
//=========
76
input    [3:0] brk_reg_rd;   // Hardware break/watch-point register read select
77
input    [3:0] brk_reg_wr;   // Hardware break/watch-point register write select
78 107 olivier.gi
input          dbg_clk;      // Debug unit clock
79 80 olivier.gi
input   [15:0] dbg_din;      // Debug register data input
80 107 olivier.gi
input          dbg_rst;      // Debug unit reset
81 176 olivier.gi
input          decode_noirq; // Frontend decode instruction
82 80 olivier.gi
input   [15:0] eu_mab;       // Execution-Unit Memory address bus
83
input          eu_mb_en;     // Execution-Unit Memory bus enable
84
input    [1:0] eu_mb_wr;     // Execution-Unit Memory bus write transfer
85
input   [15:0] pc;           // Program counter
86
 
87
 
88
//=============================================================================
89
// 1)  WIRE & PARAMETER DECLARATION
90
//=============================================================================
91
 
92
wire      range_wr_set;
93
wire      range_rd_set;
94
wire      addr1_wr_set;
95
wire      addr1_rd_set;
96
wire      addr0_wr_set;
97
wire      addr0_rd_set;
98
 
99 202 olivier.gi
 
100 80 olivier.gi
parameter BRK_CTL   = 0,
101
          BRK_STAT  = 1,
102
          BRK_ADDR0 = 2,
103
          BRK_ADDR1 = 3;
104
 
105 202 olivier.gi
 
106 80 olivier.gi
//=============================================================================
107
// 2)  CONFIGURATION REGISTERS
108
//=============================================================================
109
 
110
// BRK_CTL Register
111
//-----------------------------------------------------------------------------
112
//       7   6   5        4            3          2            1  0
113
//        Reserved    RANGE_MODE    INST_EN    BREAK_EN    ACCESS_MODE
114
//
115
// ACCESS_MODE: - 00 : Disabled
116
//              - 01 : Detect read access
117
//              - 10 : Detect write access
118
//              - 11 : Detect read/write access
119
//              NOTE: '10' & '11' modes are not supported on the instruction flow
120
//
121
// BREAK_EN:    -  0 : Watchmode enable
122
//              -  1 : Break enable
123
//
124
// INST_EN:     -  0 : Checks are done on the execution unit (data flow)
125
//              -  1 : Checks are done on the frontend (instruction flow)
126
//
127
// RANGE_MODE:  -  0 : Address match on BRK_ADDR0 or BRK_ADDR1
128
//              -  1 : Address match on BRK_ADDR0->BRK_ADDR1 range
129
//
130
//-----------------------------------------------------------------------------
131
reg   [4:0] brk_ctl;
132
 
133
wire        brk_ctl_wr = brk_reg_wr[BRK_CTL];
134 202 olivier.gi
 
135 107 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
136
  if (dbg_rst)         brk_ctl <=  5'h00;
137 80 olivier.gi
  else if (brk_ctl_wr) brk_ctl <=  {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
138
 
139
wire  [7:0] brk_ctl_full = {3'b000, brk_ctl};
140
 
141 202 olivier.gi
 
142 80 olivier.gi
// BRK_STAT Register
143
//-----------------------------------------------------------------------------
144
//     7    6       5         4         3         2         1         0
145
//    Reserved  RANGE_WR  RANGE_RD  ADDR1_WR  ADDR1_RD  ADDR0_WR  ADDR0_RD
146
//-----------------------------------------------------------------------------
147
reg   [5:0] brk_stat;
148
 
149
wire        brk_stat_wr  = brk_reg_wr[BRK_STAT];
150
wire  [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
151
                            range_rd_set & `HWBRK_RANGE,
152
                            addr1_wr_set, addr1_rd_set,
153
                            addr0_wr_set, addr0_rd_set};
154
wire  [5:0] brk_stat_clr = ~dbg_din[5:0];
155
 
156 107 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
157
  if (dbg_rst)          brk_stat <=  6'h00;
158 80 olivier.gi
  else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
159
  else                  brk_stat <=  (brk_stat                 | brk_stat_set);
160
 
161
wire  [7:0] brk_stat_full = {2'b00, brk_stat};
162
wire        brk_pnd       = |brk_stat;
163
 
164
 
165
// BRK_ADDR0 Register
166
//-----------------------------------------------------------------------------
167
reg  [15:0] brk_addr0;
168
 
169
wire        brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
170 202 olivier.gi
 
171 107 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
172
  if (dbg_rst)           brk_addr0 <=  16'h0000;
173 80 olivier.gi
  else if (brk_addr0_wr) brk_addr0 <=  dbg_din;
174
 
175 202 olivier.gi
 
176 80 olivier.gi
// BRK_ADDR1/DATA0 Register
177
//-----------------------------------------------------------------------------
178
reg  [15:0] brk_addr1;
179
 
180
wire        brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
181 202 olivier.gi
 
182 107 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
183
  if (dbg_rst)           brk_addr1 <=  16'h0000;
184 80 olivier.gi
  else if (brk_addr1_wr) brk_addr1 <=  dbg_din;
185
 
186 202 olivier.gi
 
187 80 olivier.gi
//============================================================================
188
// 3) DATA OUTPUT GENERATION
189
//============================================================================
190
 
191
wire [15:0] brk_ctl_rd   = {8'h00, brk_ctl_full}  & {16{brk_reg_rd[BRK_CTL]}};
192
wire [15:0] brk_stat_rd  = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
193
wire [15:0] brk_addr0_rd = brk_addr0              & {16{brk_reg_rd[BRK_ADDR0]}};
194
wire [15:0] brk_addr1_rd = brk_addr1              & {16{brk_reg_rd[BRK_ADDR1]}};
195
 
196
wire [15:0] brk_dout = brk_ctl_rd   |
197
                       brk_stat_rd  |
198
                       brk_addr0_rd |
199
                       brk_addr1_rd;
200
 
201 202 olivier.gi
 
202 80 olivier.gi
//============================================================================
203
// 4) BREAKPOINT / WATCHPOINT GENERATION
204
//============================================================================
205
 
206
// Comparators
207
//---------------------------
208
// Note: here the comparison logic is instanciated several times in order
209
//       to improve the timings, at the cost of a bit more area.
210 202 olivier.gi
 
211 80 olivier.gi
wire        equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
212
wire        equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
213 202 olivier.gi
wire        equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
214 80 olivier.gi
                          brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
215
 
216
 
217 176 olivier.gi
wire        equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
218
wire        equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
219
wire        equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
220 80 olivier.gi
                          brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
221
 
222
 
223
// Detect accesses
224
//---------------------------
225
 
226
// Detect Instruction read access
227
wire i_addr0_rd =  equ_i_addr0 &  brk_ctl[`BRK_I_EN];
228
wire i_addr1_rd =  equ_i_addr1 &  brk_ctl[`BRK_I_EN];
229
wire i_range_rd =  equ_i_range &  brk_ctl[`BRK_I_EN];
230
 
231
// Detect Execution-Unit write access
232
wire d_addr0_wr =  equ_d_addr0 & ~brk_ctl[`BRK_I_EN] &  |eu_mb_wr;
233
wire d_addr1_wr =  equ_d_addr1 & ~brk_ctl[`BRK_I_EN] &  |eu_mb_wr;
234
wire d_range_wr =  equ_d_range & ~brk_ctl[`BRK_I_EN] &  |eu_mb_wr;
235
 
236
// Detect DATA read access
237 176 olivier.gi
wire d_addr0_rd =  equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
238
wire d_addr1_rd =  equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
239
wire d_range_rd =  equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
240 202 olivier.gi
 
241 80 olivier.gi
// Set flags
242
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd  | i_addr0_rd);
243
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] &  d_addr0_wr;
244
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd  | i_addr1_rd);
245
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] &  d_addr1_wr;
246
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd  | i_range_rd);
247
assign range_wr_set = brk_ctl[`BRK_MODE_WR] &  d_range_wr;
248
 
249 202 olivier.gi
 
250 80 olivier.gi
// Break CPU
251
assign brk_halt     = brk_ctl[`BRK_EN] & |brk_stat_set;
252 202 olivier.gi
 
253
 
254 80 olivier.gi
endmodule // omsp_dbg_hwbrk
255
 
256 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
257
`else
258 80 olivier.gi
`include "openMSP430_undefines.v"
259 104 olivier.gi
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.