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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_execution_unit.v] - Blame information for rev 136

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1 80 olivier.gi
//----------------------------------------------------------------------------
2 128 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 80 olivier.gi
//
4 128 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15 80 olivier.gi
//
16 128 olivier.gi
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27 80 olivier.gi
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_execution_unit.v
31
// 
32
// *Module Description:
33
//                       openMSP430 Execution unit
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39 136 olivier.gi
// $Rev: 128 $
40 80 olivier.gi
// $LastChangedBy: olivier.girard $
41 136 olivier.gi
// $LastChangedDate: 2011-12-16 22:05:46 +0100 (Fri, 16 Dec 2011) $
42 80 olivier.gi
//----------------------------------------------------------------------------
43 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
44
`else
45 80 olivier.gi
`include "openMSP430_defines.v"
46 104 olivier.gi
`endif
47 80 olivier.gi
 
48
module  omsp_execution_unit (
49
 
50
// OUTPUTs
51
    cpuoff,                        // Turns off the CPU
52
    dbg_reg_din,                   // Debug unit CPU register data input
53
    gie,                           // General interrupt enable
54
    mab,                           // Memory address bus
55
    mb_en,                         // Memory bus enable
56
    mb_wr,                         // Memory bus write transfer
57
    mdb_out,                       // Memory data bus output
58
    oscoff,                        // Turns off LFXT1 clock input
59
    pc_sw,                         // Program counter software value
60
    pc_sw_wr,                      // Program counter software write
61 136 olivier.gi
    scg0,                          // System clock generator 1. Turns off the DCO
62 80 olivier.gi
    scg1,                          // System clock generator 1. Turns off the SMCLK
63
 
64
// INPUTs
65
    dbg_halt_st,                   // Halt/Run status from CPU
66
    dbg_mem_dout,                  // Debug unit data output
67
    dbg_reg_wr,                    // Debug unit CPU register write
68
    e_state,                       // Execution state
69
    exec_done,                     // Execution completed
70
    inst_ad,                       // Decoded Inst: destination addressing mode
71
    inst_as,                       // Decoded Inst: source addressing mode
72
    inst_alu,                      // ALU control signals
73
    inst_bw,                       // Decoded Inst: byte width
74
    inst_dest,                     // Decoded Inst: destination (one hot)
75
    inst_dext,                     // Decoded Inst: destination extended instruction word
76
    inst_irq_rst,                  // Decoded Inst: reset interrupt
77
    inst_jmp,                      // Decoded Inst: Conditional jump
78 105 olivier.gi
    inst_mov,                      // Decoded Inst: mov instruction
79 80 olivier.gi
    inst_sext,                     // Decoded Inst: source extended instruction word
80
    inst_so,                       // Decoded Inst: Single-operand arithmetic
81
    inst_src,                      // Decoded Inst: source (one hot)
82
    inst_type,                     // Decoded Instruction type
83
    mclk,                          // Main system clock
84
    mdb_in,                        // Memory data bus input
85
    pc,                            // Program counter
86
    pc_nxt,                        // Next PC value (for CALL & IRQ)
87 136 olivier.gi
    puc_rst,                       // Main system reset
88
    scan_enable                    // Scan enable (active during scan shifting)
89 80 olivier.gi
);
90
 
91
// OUTPUTs
92
//=========
93
output              cpuoff;        // Turns off the CPU
94
output       [15:0] dbg_reg_din;   // Debug unit CPU register data input
95
output              gie;           // General interrupt enable
96
output       [15:0] mab;           // Memory address bus
97
output              mb_en;         // Memory bus enable
98
output        [1:0] mb_wr;         // Memory bus write transfer
99
output       [15:0] mdb_out;       // Memory data bus output
100
output              oscoff;        // Turns off LFXT1 clock input
101
output       [15:0] pc_sw;         // Program counter software value
102
output              pc_sw_wr;      // Program counter software write
103 136 olivier.gi
output              scg0;          // System clock generator 1. Turns off the DCO
104 80 olivier.gi
output              scg1;          // System clock generator 1. Turns off the SMCLK
105
 
106
// INPUTs
107
//=========
108
input               dbg_halt_st;   // Halt/Run status from CPU
109
input        [15:0] dbg_mem_dout;  // Debug unit data output
110
input               dbg_reg_wr;    // Debug unit CPU register write
111
input         [3:0] e_state;       // Execution state
112
input               exec_done;     // Execution completed
113
input         [7:0] inst_ad;       // Decoded Inst: destination addressing mode
114
input         [7:0] inst_as;       // Decoded Inst: source addressing mode
115
input        [11:0] inst_alu;      // ALU control signals
116
input               inst_bw;       // Decoded Inst: byte width
117
input        [15:0] inst_dest;     // Decoded Inst: destination (one hot)
118
input        [15:0] inst_dext;     // Decoded Inst: destination extended instruction word
119
input               inst_irq_rst;  // Decoded Inst: reset interrupt
120
input         [7:0] inst_jmp;      // Decoded Inst: Conditional jump
121 105 olivier.gi
input               inst_mov;      // Decoded Inst: mov instruction
122 80 olivier.gi
input        [15:0] inst_sext;     // Decoded Inst: source extended instruction word
123
input         [7:0] inst_so;       // Decoded Inst: Single-operand arithmetic
124
input        [15:0] inst_src;      // Decoded Inst: source (one hot)
125
input         [2:0] inst_type;     // Decoded Instruction type
126
input               mclk;          // Main system clock
127
input        [15:0] mdb_in;        // Memory data bus input
128
input        [15:0] pc;            // Program counter
129
input        [15:0] pc_nxt;        // Next PC value (for CALL & IRQ)
130 111 olivier.gi
input               puc_rst;       // Main system reset
131 136 olivier.gi
input               scan_enable;   // Scan enable (active during scan shifting)
132 80 olivier.gi
 
133
 
134
//=============================================================================
135
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
136
//=============================================================================
137
 
138
wire         [15:0] alu_out;
139
wire         [15:0] alu_out_add;
140
wire          [3:0] alu_stat;
141
wire          [3:0] alu_stat_wr;
142
wire         [15:0] op_dst;
143
wire         [15:0] op_src;
144
wire         [15:0] reg_dest;
145
wire         [15:0] reg_src;
146
wire         [15:0] mdb_in_bw;
147
wire         [15:0] mdb_in_val;
148
wire          [3:0] status;
149
 
150
 
151
//=============================================================================
152
// 2)  REGISTER FILE
153
//=============================================================================
154
 
155
wire reg_dest_wr  = ((e_state==`E_EXEC) & (
156
                     (inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR])  |
157
                     (inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) |
158
                      inst_type[`INST_JMP])) | dbg_reg_wr;
159
 
160
wire reg_sp_wr    = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) |
161 128 olivier.gi
                     ((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) &  ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) |
162
                     ((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) &  inst_as[`IDX])) |
163
                     ((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) &  ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])));
164 80 olivier.gi
 
165
wire reg_sr_wr    =  (e_state==`E_DST_RD) & inst_so[`RETI];
166
 
167
wire reg_sr_clr   =  (e_state==`E_IRQ_2);
168
 
169
wire reg_pc_call  = ((e_state==`E_EXEC)   & inst_so[`CALL]) |
170
                    ((e_state==`E_DST_WR) & inst_so[`RETI]);
171
 
172
wire reg_incr     =  (exec_done          & inst_as[`INDIR_I]) |
173
                    ((e_state==`E_SRC_RD) & inst_so[`RETI])    |
174
                    ((e_state==`E_EXEC)   & inst_so[`RETI]);
175
 
176
assign dbg_reg_din = reg_dest;
177
 
178
 
179
omsp_register_file register_file_0 (
180
 
181
// OUTPUTs
182
    .cpuoff       (cpuoff),       // Turns off the CPU
183
    .gie          (gie),          // General interrupt enable
184
    .oscoff       (oscoff),       // Turns off LFXT1 clock input
185
    .pc_sw        (pc_sw),        // Program counter software value
186
    .pc_sw_wr     (pc_sw_wr),     // Program counter software write
187
    .reg_dest     (reg_dest),     // Selected register destination content
188
    .reg_src      (reg_src),      // Selected register source content
189 136 olivier.gi
    .scg0         (scg0),         // System clock generator 1. Turns off the DCO
190 80 olivier.gi
    .scg1         (scg1),         // System clock generator 1. Turns off the SMCLK
191
    .status       (status),       // R2 Status {V,N,Z,C}
192
 
193
// INPUTs
194
    .alu_stat     (alu_stat),     // ALU Status {V,N,Z,C}
195
    .alu_stat_wr  (alu_stat_wr),  // ALU Status write {V,N,Z,C}
196
    .inst_bw      (inst_bw),      // Decoded Inst: byte width
197
    .inst_dest    (inst_dest),    // Register destination selection
198
    .inst_src     (inst_src),     // Register source selection
199
    .mclk         (mclk),         // Main system clock
200
    .pc           (pc),           // Program counter
201 111 olivier.gi
    .puc_rst      (puc_rst),      // Main system reset
202 80 olivier.gi
    .reg_dest_val (alu_out),      // Selected register destination value
203
    .reg_dest_wr  (reg_dest_wr),  // Write selected register destination
204
    .reg_pc_call  (reg_pc_call),  // Trigger PC update for a CALL instruction
205
    .reg_sp_val   (alu_out_add),  // Stack Pointer next value
206
    .reg_sp_wr    (reg_sp_wr),    // Stack Pointer write
207
    .reg_sr_clr   (reg_sr_clr),   // Status register clear for interrupts
208
    .reg_sr_wr    (reg_sr_wr),    // Status Register update for RETI instruction
209 136 olivier.gi
    .reg_incr     (reg_incr),     // Increment source register
210
    .scan_enable  (scan_enable)   // Scan enable (active during scan shifting)
211 80 olivier.gi
);
212
 
213
 
214
//=============================================================================
215
// 3)  SOURCE OPERAND MUXING
216
//=============================================================================
217
// inst_as[`DIR]    : Register direct.   -> Source is in register
218
// inst_as[`IDX]    : Register indexed.  -> Source is in memory, address is register+offset
219
// inst_as[`INDIR]  : Register indirect.
220
// inst_as[`INDIR_I]: Register indirect autoincrement.
221
// inst_as[`SYMB]   : Symbolic (operand is in memory at address PC+x).
222
// inst_as[`IMM]    : Immediate (operand is next word in the instruction stream).
223
// inst_as[`ABS]    : Absolute (operand is in memory at address x).
224
// inst_as[`CONST]  : Constant.
225
 
226
wire src_reg_src_sel    =  (e_state==`E_IRQ_0)                    |
227
                           (e_state==`E_IRQ_2)                    |
228
                          ((e_state==`E_SRC_RD) & ~inst_as[`ABS]) |
229
                          ((e_state==`E_SRC_WR) & ~inst_as[`ABS]) |
230
                          ((e_state==`E_EXEC)   &  inst_as[`DIR] & ~inst_type[`INST_JMP]);
231
 
232
wire src_reg_dest_sel   =  (e_state==`E_IRQ_1)                    |
233
                           (e_state==`E_IRQ_3)                    |
234 104 olivier.gi
                          ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) |
235 128 olivier.gi
                          ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]);
236 80 olivier.gi
 
237
wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) &  inst_so[`RETI])                     |
238
                          ((e_state==`E_EXEC)   & (inst_as[`INDIR] | inst_as[`INDIR_I] |
239
                                                   inst_as[`IDX]   | inst_as[`SYMB]    |
240
                                                   inst_as[`ABS]));
241
 
242
wire src_inst_dext_sel =  ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) |
243
                          ((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL]   |
244
                                                    inst_so[`RETI]));
245
 
246
wire src_inst_sext_sel =  ((e_state==`E_EXEC)   &  (inst_type[`INST_JMP] | inst_as[`IMM] |
247
                                                    inst_as[`CONST]      | inst_so[`RETI]));
248
 
249
 
250
assign op_src = src_reg_src_sel     ?  reg_src    :
251
                src_reg_dest_sel    ?  reg_dest   :
252
                src_mdb_in_val_sel  ?  mdb_in_val :
253
                src_inst_dext_sel   ?  inst_dext  :
254
                src_inst_sext_sel   ?  inst_sext  : 16'h0000;
255
 
256
 
257
//=============================================================================
258
// 4)  DESTINATION OPERAND MUXING
259
//=============================================================================
260
// inst_ad[`DIR]    : Register direct.
261
// inst_ad[`IDX]    : Register indexed.
262
// inst_ad[`SYMB]   : Symbolic (operand is in memory at address PC+x).
263
// inst_ad[`ABS]    : Absolute (operand is in memory at address x).
264
 
265
 
266
wire dst_inst_sext_sel  = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] |
267
                                                   inst_as[`ABS]))                |
268
                          ((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] |
269
                                                   inst_as[`ABS]));
270
 
271
wire dst_mdb_in_bw_sel  = ((e_state==`E_DST_WR) &   inst_so[`RETI]) |
272
                          ((e_state==`E_EXEC)   & ~(inst_ad[`DIR] | inst_type[`INST_JMP] |
273
                                                    inst_type[`INST_SO]) & ~inst_so[`RETI]);
274
 
275
wire dst_fffe_sel       =  (e_state==`E_IRQ_0)  |
276
                           (e_state==`E_IRQ_1)  |
277
                           (e_state==`E_IRQ_3)  |
278 104 olivier.gi
                          ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) |
279 128 olivier.gi
                          ((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) |
280
                          ((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]);
281 80 olivier.gi
 
282
wire dst_reg_dest_sel   = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) |
283
                          ((e_state==`E_DST_WR) &  ~inst_ad[`ABS]) |
284
                          ((e_state==`E_EXEC)   &  (inst_ad[`DIR] | inst_type[`INST_JMP] |
285
                                                    inst_type[`INST_SO]) & ~inst_so[`RETI]);
286
 
287
 
288
assign op_dst = dbg_halt_st        ? dbg_mem_dout  :
289
                dst_inst_sext_sel  ? inst_sext     :
290
                dst_mdb_in_bw_sel  ? mdb_in_bw     :
291
                dst_reg_dest_sel   ? reg_dest      :
292
                dst_fffe_sel       ? 16'hfffe      : 16'h0000;
293
 
294
 
295
//=============================================================================
296
// 5)  ALU
297
//=============================================================================
298
 
299
wire exec_cycle = (e_state==`E_EXEC);
300
 
301
omsp_alu alu_0 (
302
 
303
// OUTPUTs
304
    .alu_out      (alu_out),      // ALU output value
305
    .alu_out_add  (alu_out_add),  // ALU adder output value
306
    .alu_stat     (alu_stat),     // ALU Status {V,N,Z,C}
307
    .alu_stat_wr  (alu_stat_wr),  // ALU Status write {V,N,Z,C}
308
 
309
// INPUTs
310
    .dbg_halt_st  (dbg_halt_st),  // Halt/Run status from CPU
311
    .exec_cycle   (exec_cycle),   // Instruction execution cycle
312
    .inst_alu     (inst_alu),     // ALU control signals
313
    .inst_bw      (inst_bw),      // Decoded Inst: byte width
314
    .inst_jmp     (inst_jmp),     // Decoded Inst: Conditional jump
315
    .inst_so      (inst_so),      // Single-operand arithmetic
316
    .op_dst       (op_dst),       // Destination operand
317
    .op_src       (op_src),       // Source operand
318
    .status       (status)        // R2 Status {V,N,Z,C}
319
);
320
 
321
 
322
//=============================================================================
323
// 6)  MEMORY INTERFACE
324
//=============================================================================
325
 
326
// Detect memory read/write access
327 105 olivier.gi
assign      mb_en     = ((e_state==`E_IRQ_1)  & ~inst_irq_rst)        |
328
                        ((e_state==`E_IRQ_3)  & ~inst_irq_rst)        |
329
                        ((e_state==`E_SRC_RD) & ~inst_as[`IMM])       |
330
                         (e_state==`E_SRC_WR)                         |
331
                        ((e_state==`E_EXEC)   &  inst_so[`RETI])      |
332
                        ((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
333
                                              & ~inst_mov)            |
334 80 olivier.gi
                         (e_state==`E_DST_WR);
335
 
336
wire  [1:0] mb_wr_msk =  inst_alu[`EXEC_NO_WR]  ? 2'b00 :
337
                        ~inst_bw                ? 2'b11 :
338
                         alu_out_add[0]         ? 2'b10 : 2'b01;
339
assign      mb_wr     = ({2{(e_state==`E_IRQ_1)}}  |
340
                         {2{(e_state==`E_IRQ_3)}}  |
341
                         {2{(e_state==`E_DST_WR)}} |
342
                         {2{(e_state==`E_SRC_WR)}}) & mb_wr_msk;
343
 
344
// Memory address bus
345
assign      mab       = alu_out_add[15:0];
346
 
347
// Memory data bus output
348
reg  [15:0] mdb_out_nxt;
349 136 olivier.gi
 
350
`ifdef CLOCK_GATING
351
wire        mdb_out_nxt_en  = (e_state==`E_DST_RD) |
352
                              (((e_state==`E_EXEC) & ~inst_so[`CALL]) |
353
                                (e_state==`E_IRQ_0) | (e_state==`E_IRQ_2));
354
wire        mclk_mdb_out_nxt;
355
omsp_clock_gate clock_gate_mdb_out_nxt (.gclk(mclk_mdb_out_nxt),
356
                                        .clk (mclk), .enable(mdb_out_nxt_en), .scan_enable(scan_enable));
357
`else
358
wire        mclk_mdb_out_nxt = mclk;
359
`endif
360
 
361
always @(posedge mclk_mdb_out_nxt or posedge puc_rst)
362 111 olivier.gi
  if (puc_rst)                                        mdb_out_nxt <= 16'h0000;
363 80 olivier.gi
  else if (e_state==`E_DST_RD)                        mdb_out_nxt <= pc_nxt;
364 136 olivier.gi
`ifdef CLOCK_GATING
365
  else                                                mdb_out_nxt <= alu_out;
366
`else
367 80 olivier.gi
  else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
368
           (e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
369 136 olivier.gi
`endif
370 80 olivier.gi
 
371
assign      mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
372
 
373
// Format memory data bus input depending on BW
374
reg        mab_lsb;
375 111 olivier.gi
always @(posedge mclk or posedge puc_rst)
376
  if (puc_rst)    mab_lsb <= 1'b0;
377 80 olivier.gi
  else if (mb_en) mab_lsb <= alu_out_add[0];
378
 
379
assign mdb_in_bw  = ~inst_bw ? mdb_in :
380
                     mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
381
 
382
// Memory data bus input buffer (buffer after a source read)
383
reg         mdb_in_buf_en;
384 111 olivier.gi
always @(posedge mclk or posedge puc_rst)
385
  if (puc_rst)  mdb_in_buf_en <= 1'b0;
386
  else          mdb_in_buf_en <= (e_state==`E_SRC_RD);
387 80 olivier.gi
 
388
reg         mdb_in_buf_valid;
389 111 olivier.gi
always @(posedge mclk or posedge puc_rst)
390
  if (puc_rst)               mdb_in_buf_valid <= 1'b0;
391 80 olivier.gi
  else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
392
  else if (mdb_in_buf_en)    mdb_in_buf_valid <= 1'b1;
393
 
394
reg  [15:0] mdb_in_buf;
395 136 olivier.gi
 
396
`ifdef CLOCK_GATING
397
wire        mclk_mdb_in_buf;
398
omsp_clock_gate clock_gate_mdb_in_buf (.gclk(mclk_mdb_in_buf),
399
                                       .clk (mclk), .enable(mdb_in_buf_en), .scan_enable(scan_enable));
400
`else
401
wire        mclk_mdb_in_buf = mclk;
402
`endif
403
 
404
always @(posedge mclk_mdb_in_buf or posedge puc_rst)
405 111 olivier.gi
  if (puc_rst)            mdb_in_buf <= 16'h0000;
406 136 olivier.gi
`ifdef CLOCK_GATING
407
  else                    mdb_in_buf <= mdb_in_bw;
408
`else
409 80 olivier.gi
  else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
410 136 olivier.gi
`endif
411 80 olivier.gi
 
412
assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
413
 
414
 
415
endmodule // omsp_execution_unit
416
 
417 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
418
`else
419 80 olivier.gi
`include "openMSP430_undefines.v"
420 104 olivier.gi
`endif

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