OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_wakeup_cell.v] - Blame information for rev 153

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 136 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
4
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15
//
16
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_wakeup_cell.v
31
// 
32
// *Module Description:
33
//                       Generic Wakeup cell
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev: 103 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
42
//----------------------------------------------------------------------------
43
 
44
module  omsp_wakeup_cell (
45
 
46
// OUTPUTs
47
    wkup_out,                  // Wakup signal (asynchronous)
48
 
49
// INPUTs
50
    scan_clk,                  // Scan clock
51
    scan_mode,                 // Scan mode
52
    scan_rst,                  // Scan reset
53
    wkup_clear,                // Glitch free wakeup event clear
54
    wkup_event                 // Glitch free asynchronous wakeup event
55
);
56
 
57
// OUTPUTs
58
//=========
59
output         wkup_out;       // Wakup signal (asynchronous)
60
 
61
// INPUTs
62
//=========
63
input          scan_clk;       // Scan clock
64
input          scan_mode;      // Scan mode
65
input          scan_rst;       // Scan reset
66
input          wkup_clear;     // Glitch free wakeup event clear
67
input          wkup_event;     // Glitch free asynchronous wakeup event
68
 
69
 
70
//=============================================================================
71
// 1)  AND GATE
72
//=============================================================================
73
 
74
// Scan stuff for the ASIC mode
75
`ifdef ASIC
76
   wire wkup_rst;
77
   omsp_scan_mux scan_mux_rst (
78
                               .scan_mode    (scan_mode),
79
                               .data_in_scan (scan_rst),
80
                               .data_in_func (wkup_clear),
81
                               .data_out     (wkup_rst)
82
   );
83
 
84
   wire wkup_clk;
85
   omsp_scan_mux scan_mux_clk (
86
                               .scan_mode    (scan_mode),
87
                               .data_in_scan (scan_clk),
88
                               .data_in_func (wkup_event),
89
                               .data_out     (wkup_clk)
90
   );
91
 
92
`else
93
   wire wkup_rst  =  wkup_clear;
94
   wire wkup_clk  =  wkup_event;
95
`endif
96
 
97
// Wakeup capture
98
reg    wkup_out;
99
always @(posedge wkup_clk or posedge wkup_rst)
100
  if (wkup_rst) wkup_out <= 1'b0;
101
  else          wkup_out <= 1'b1;
102
 
103
 
104
endmodule // omsp_wakeup_cell
105
 
106
 
107
 
108
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.