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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Blame information for rev 143

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Line No. Rev Author Line
1 80 olivier.gi
//----------------------------------------------------------------------------
2 136 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 80 olivier.gi
//
4 136 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15 80 olivier.gi
//
16 136 olivier.gi
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27 80 olivier.gi
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: openMSP430.v
31
// 
32
// *Module Description:
33
//                       openMSP430 Top level file
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39 111 olivier.gi
// $Rev: 103 $
40 80 olivier.gi
// $LastChangedBy: olivier.girard $
41 111 olivier.gi
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
42 80 olivier.gi
//----------------------------------------------------------------------------
43 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
44
`else
45 80 olivier.gi
`include "openMSP430_defines.v"
46 104 olivier.gi
`endif
47 80 olivier.gi
 
48
module  openMSP430 (
49
 
50
// OUTPUTs
51 136 olivier.gi
    aclk,                          // ASIC ONLY: ACLK
52
    aclk_en,                       // FPGA ONLY: ACLK enable
53 80 olivier.gi
    dbg_freeze,                    // Freeze peripherals
54
    dbg_uart_txd,                  // Debug interface: UART TXD
55 136 olivier.gi
    dco_enable,                    // ASIC ONLY: Fast oscillator enable
56
    dco_wkup,                      // ASIC ONLY: Fast oscillator wake-up (asynchronous)
57 80 olivier.gi
    dmem_addr,                     // Data Memory address
58
    dmem_cen,                      // Data Memory chip enable (low active)
59
    dmem_din,                      // Data Memory data input
60
    dmem_wen,                      // Data Memory write enable (low active)
61
    irq_acc,                       // Interrupt request accepted (one-hot signal)
62 136 olivier.gi
    lfxt_enable,                   // ASIC ONLY: Low frequency oscillator enable
63
    lfxt_wkup,                     // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
64 80 olivier.gi
    mclk,                          // Main system clock
65
    per_addr,                      // Peripheral address
66
    per_din,                       // Peripheral data input
67 107 olivier.gi
    per_we,                        // Peripheral write enable (high active)
68 80 olivier.gi
    per_en,                        // Peripheral enable (high active)
69
    pmem_addr,                     // Program Memory address
70
    pmem_cen,                      // Program Memory chip enable (low active)
71
    pmem_din,                      // Program Memory data input (optional)
72
    pmem_wen,                      // Program Memory write enable (low active) (optional)
73 111 olivier.gi
    puc_rst,                       // Main system reset
74 136 olivier.gi
    smclk,                         // ASIC ONLY: SMCLK
75
    smclk_en,                      // FPGA ONLY: SMCLK enable
76 80 olivier.gi
 
77
// INPUTs
78 136 olivier.gi
    cpu_en,                        // Enable CPU code execution (asynchronous and non-glitchy)
79
    dbg_en,                        // Debug interface enable (asynchronous and non-glitchy)
80 107 olivier.gi
    dbg_uart_rxd,                  // Debug interface: UART RXD (asynchronous)
81 80 olivier.gi
    dco_clk,                       // Fast oscillator (fast clock)
82
    dmem_dout,                     // Data Memory data output
83
    irq,                           // Maskable interrupts
84
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
85
    nmi,                           // Non-maskable interrupt (asynchronous)
86
    per_dout,                      // Peripheral data output
87
    pmem_dout,                     // Program Memory data output
88 136 olivier.gi
    reset_n,                       // Reset Pin (low active, asynchronous and non-glitchy)
89
    scan_enable,                   // ASIC ONLY: Scan enable (active during scan shifting)
90
    scan_mode,                     // ASIC ONLY: Scan mode
91
    wkup                           // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
92 80 olivier.gi
);
93
 
94
// OUTPUTs
95
//=========
96 136 olivier.gi
output               aclk;         // ASIC ONLY: ACLK
97
output               aclk_en;      // FPGA ONLY: ACLK enable
98 80 olivier.gi
output               dbg_freeze;   // Freeze peripherals
99
output               dbg_uart_txd; // Debug interface: UART TXD
100 136 olivier.gi
output               dco_enable;   // ASIC ONLY: Fast oscillator enable
101
output               dco_wkup;     // ASIC ONLY: Fast oscillator wake-up (asynchronous)
102 80 olivier.gi
output [`DMEM_MSB:0] dmem_addr;    // Data Memory address
103
output               dmem_cen;     // Data Memory chip enable (low active)
104
output        [15:0] dmem_din;     // Data Memory data input
105
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
106
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
107 136 olivier.gi
output               lfxt_enable;  // ASIC ONLY: Low frequency oscillator enable
108
output               lfxt_wkup;    // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
109 80 olivier.gi
output               mclk;         // Main system clock
110 111 olivier.gi
output        [13:0] per_addr;     // Peripheral address
111 80 olivier.gi
output        [15:0] per_din;      // Peripheral data input
112 107 olivier.gi
output         [1:0] per_we;       // Peripheral write enable (high active)
113 80 olivier.gi
output               per_en;       // Peripheral enable (high active)
114
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
115
output               pmem_cen;     // Program Memory chip enable (low active)
116
output        [15:0] pmem_din;     // Program Memory data input (optional)
117
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
118 111 olivier.gi
output               puc_rst;      // Main system reset
119 136 olivier.gi
output               smclk;        // ASIC ONLY: SMCLK
120
output               smclk_en;     // FPGA ONLY: SMCLK enable
121 80 olivier.gi
 
122
 
123
// INPUTs
124
//=========
125 136 olivier.gi
input                cpu_en;       // Enable CPU code execution (asynchronous and non-glitchy)
126
input                dbg_en;       // Debug interface enable (asynchronous and non-glitchy)
127 107 olivier.gi
input                dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input                dco_clk;      // Fast oscillator (fast clock)
129
input         [15:0] dmem_dout;    // Data Memory data output
130
input         [13:0] irq;          // Maskable interrupts
131
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
132 136 olivier.gi
input                nmi;          // Non-maskable interrupt (asynchronous and non-glitchy)
133 80 olivier.gi
input         [15:0] per_dout;     // Peripheral data output
134
input         [15:0] pmem_dout;    // Program Memory data output
135 136 olivier.gi
input                reset_n;      // Reset Pin (active low, asynchronous and non-glitchy)
136
input                scan_enable;  // ASIC ONLY: Scan enable (active during scan shifting)
137
input                scan_mode;    // ASIC ONLY: Scan mode
138
input                wkup;         // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
139 80 olivier.gi
 
140
 
141
 
142
//=============================================================================
143
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
144
//=============================================================================
145
 
146
wire          [7:0] inst_ad;
147
wire          [7:0] inst_as;
148
wire         [11:0] inst_alu;
149
wire                inst_bw;
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wire                inst_irq_rst;
151
wire                inst_mov;
152 80 olivier.gi
wire         [15:0] inst_dest;
153
wire         [15:0] inst_dext;
154
wire         [15:0] inst_sext;
155
wire          [7:0] inst_so;
156
wire         [15:0] inst_src;
157
wire          [2:0] inst_type;
158 111 olivier.gi
wire          [7:0] inst_jmp;
159 80 olivier.gi
wire          [3:0] e_state;
160
wire                exec_done;
161 111 olivier.gi
wire                decode_noirq;
162
wire                cpu_en_s;
163
wire                cpuoff;
164
wire                oscoff;
165 136 olivier.gi
wire                scg0;
166 111 olivier.gi
wire                scg1;
167
wire                por;
168
wire                gie;
169 136 olivier.gi
wire                mclk_enable;
170
wire                mclk_wkup;
171
wire         [31:0] cpu_id;
172 80 olivier.gi
 
173
wire         [15:0] eu_mab;
174
wire         [15:0] eu_mdb_in;
175
wire         [15:0] eu_mdb_out;
176
wire          [1:0] eu_mb_wr;
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wire                eu_mb_en;
178 80 olivier.gi
wire         [15:0] fe_mab;
179
wire         [15:0] fe_mdb_in;
180 111 olivier.gi
wire                fe_mb_en;
181
wire                fe_pmem_wait;
182 80 olivier.gi
 
183 111 olivier.gi
wire                pc_sw_wr;
184 80 olivier.gi
wire         [15:0] pc_sw;
185
wire         [15:0] pc;
186
wire         [15:0] pc_nxt;
187
 
188 111 olivier.gi
wire                nmi_acc;
189 136 olivier.gi
wire                nmi_pnd;
190
wire                nmi_wkup;
191 111 olivier.gi
 
192
wire                wdtie;
193 136 olivier.gi
wire                wdtnmies;
194
wire                wdtifg;
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wire                wdt_irq;
196 136 olivier.gi
wire                wdt_wkup;
197 111 olivier.gi
wire                wdt_reset;
198 136 olivier.gi
wire                wdtifg_sw_clr;
199
wire                wdtifg_sw_set;
200 111 olivier.gi
 
201
wire                dbg_clk;
202
wire                dbg_rst;
203
wire                dbg_en_s;
204
wire                dbg_halt_st;
205 86 olivier.gi
wire                dbg_halt_cmd;
206
wire                dbg_mem_en;
207
wire                dbg_reg_wr;
208 107 olivier.gi
wire                dbg_cpu_reset;
209 80 olivier.gi
wire         [15:0] dbg_mem_addr;
210
wire         [15:0] dbg_mem_dout;
211
wire         [15:0] dbg_mem_din;
212
wire         [15:0] dbg_reg_din;
213
wire          [1:0] dbg_mem_wr;
214 136 olivier.gi
wire                puc_pnd_set;
215
 
216 80 olivier.gi
wire         [15:0] per_dout_or;
217
wire         [15:0] per_dout_sfr;
218
wire         [15:0] per_dout_wdog;
219
wire         [15:0] per_dout_mpy;
220
wire         [15:0] per_dout_clk;
221
 
222
 
223
//=============================================================================
224
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
225
//=============================================================================
226
 
227
omsp_clock_module clock_module_0 (
228
 
229
// OUTPUTs
230 136 olivier.gi
    .aclk         (aclk),          // ACLK
231 80 olivier.gi
    .aclk_en      (aclk_en),       // ACLK enablex
232 107 olivier.gi
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
233
    .dbg_clk      (dbg_clk),       // Debug unit clock
234
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
235
    .dbg_rst      (dbg_rst),       // Debug unit reset
236 136 olivier.gi
    .dco_enable   (dco_enable),    // Fast oscillator enable
237
    .dco_wkup     (dco_wkup),      // Fast oscillator wake-up (asynchronous)
238
    .lfxt_enable  (lfxt_enable),   // Low frequency oscillator enable
239
    .lfxt_wkup    (lfxt_wkup),     // Low frequency oscillator wake-up (asynchronous)
240 80 olivier.gi
    .mclk         (mclk),          // Main system clock
241
    .per_dout     (per_dout_clk),  // Peripheral data output
242
    .por          (por),           // Power-on reset
243 136 olivier.gi
    .puc_pnd_set  (puc_pnd_set),   // PUC pending set for the serial debug interface
244 111 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
245 136 olivier.gi
    .smclk        (smclk),         // SMCLK
246 80 olivier.gi
    .smclk_en     (smclk_en),      // SMCLK enable
247
 
248
// INPUTs
249 107 olivier.gi
    .cpu_en       (cpu_en),        // Enable CPU code execution (asynchronous)
250 136 olivier.gi
    .cpuoff       (cpuoff),        // Turns off the CPU
251 107 olivier.gi
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
252
    .dbg_en       (dbg_en),        // Debug interface enable (asynchronous)
253 80 olivier.gi
    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
254
    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
255 136 olivier.gi
    .mclk_enable  (mclk_enable),   // Main System Clock enable
256
    .mclk_wkup    (mclk_wkup),     // Main System Clock wake-up (asynchronous)
257 80 olivier.gi
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
258
    .per_addr     (per_addr),      // Peripheral address
259
    .per_din      (per_din),       // Peripheral data input
260
    .per_en       (per_en),        // Peripheral enable (high active)
261 107 olivier.gi
    .per_we       (per_we),        // Peripheral write enable (high active)
262
    .reset_n      (reset_n),       // Reset Pin (low active, asynchronous)
263 136 olivier.gi
    .scan_enable  (scan_enable),   // Scan enable (active during scan shifting)
264
    .scan_mode    (scan_mode),     // Scan mode
265
    .scg0         (scg0),          // System clock generator 1. Turns off the DCO
266 80 olivier.gi
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
267
    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
268
);
269
 
270
 
271
//=============================================================================
272
// 3)  FRONTEND (<=> FETCH & DECODE)
273
//=============================================================================
274
 
275
omsp_frontend frontend_0 (
276
 
277
// OUTPUTs
278
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
279
    .decode_noirq (decode_noirq),  // Frontend decode instruction
280
    .e_state      (e_state),       // Execution state
281
    .exec_done    (exec_done),     // Execution completed
282
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
283
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
284
    .inst_alu     (inst_alu),      // ALU control signals
285
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
286
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
287
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
288
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: Reset interrupt
289
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
290 105 olivier.gi
    .inst_mov     (inst_mov),      // Decoded Inst: mov instruction
291 80 olivier.gi
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
292
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
293
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
294
    .inst_type    (inst_type),     // Decoded Instruction type
295
    .irq_acc      (irq_acc),       // Interrupt request accepted
296
    .mab          (fe_mab),        // Frontend Memory address bus
297
    .mb_en        (fe_mb_en),      // Frontend Memory bus enable
298 136 olivier.gi
    .mclk_enable  (mclk_enable),   // Main System Clock enable
299
    .mclk_wkup    (mclk_wkup),     // Main System Clock wake-up (asynchronous)
300 80 olivier.gi
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
301
    .pc           (pc),            // Program counter
302
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
303
 
304
// INPUTs
305 107 olivier.gi
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
306 80 olivier.gi
    .cpuoff       (cpuoff),        // Turns off the CPU
307
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
308
    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
309
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
310
    .gie          (gie),           // General interrupt enable
311
    .irq          (irq),           // Maskable interrupts
312
    .mclk         (mclk),          // Main system clock
313
    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
314 136 olivier.gi
    .nmi_pnd      (nmi_pnd),       // Non-maskable interrupt pending
315
    .nmi_wkup     (nmi_wkup),      // NMI Wakeup
316 80 olivier.gi
    .pc_sw        (pc_sw),         // Program counter software value
317
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
318 111 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
319 136 olivier.gi
    .scan_enable  (scan_enable),   // Scan enable (active during scan shifting)
320
    .wdt_irq      (wdt_irq),       // Watchdog-timer interrupt
321
    .wdt_wkup     (wdt_wkup),      // Watchdog Wakeup
322
    .wkup         (wkup)           // System Wake-up (asynchronous)
323 80 olivier.gi
);
324
 
325
 
326
//=============================================================================
327
// 4)  EXECUTION UNIT
328
//=============================================================================
329
 
330
omsp_execution_unit execution_unit_0 (
331
 
332
// OUTPUTs
333
    .cpuoff       (cpuoff),        // Turns off the CPU
334
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
335
    .mab          (eu_mab),        // Memory address bus
336
    .mb_en        (eu_mb_en),      // Memory bus enable
337
    .mb_wr        (eu_mb_wr),      // Memory bus write transfer
338
    .mdb_out      (eu_mdb_out),    // Memory data bus output
339
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
340
    .pc_sw        (pc_sw),         // Program counter software value
341
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
342 136 olivier.gi
    .scg0         (scg0),          // System clock generator 1. Turns off the DCO
343 80 olivier.gi
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
344
 
345
// INPUTs
346
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
347
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
348
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
349
    .e_state      (e_state),       // Execution state
350
    .exec_done    (exec_done),     // Execution completed
351
    .gie          (gie),           // General interrupt enable
352
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
353
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
354
    .inst_alu     (inst_alu),      // ALU control signals
355
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
356
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
357
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
358
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: reset interrupt
359
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
360 105 olivier.gi
    .inst_mov     (inst_mov),      // Decoded Inst: mov instruction
361 80 olivier.gi
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
362
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
363
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
364
    .inst_type    (inst_type),     // Decoded Instruction type
365
    .mclk         (mclk),          // Main system clock
366
    .mdb_in       (eu_mdb_in),     // Memory data bus input
367
    .pc           (pc),            // Program counter
368
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
369 136 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
370
    .scan_enable  (scan_enable)    // Scan enable (active during scan shifting)
371 80 olivier.gi
);
372
 
373
 
374
//=============================================================================
375
// 5)  MEMORY BACKBONE
376
//=============================================================================
377
 
378
omsp_mem_backbone mem_backbone_0 (
379
 
380
// OUTPUTs
381
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
382
    .dmem_addr    (dmem_addr),     // Data Memory address
383
    .dmem_cen     (dmem_cen),      // Data Memory chip enable (low active)
384
    .dmem_din     (dmem_din),      // Data Memory data input
385
    .dmem_wen     (dmem_wen),      // Data Memory write enable (low active)
386
    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
387
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
388
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
389
    .per_addr     (per_addr),      // Peripheral address
390
    .per_din      (per_din),       // Peripheral data input
391 107 olivier.gi
    .per_we       (per_we),        // Peripheral write enable (high active)
392 80 olivier.gi
    .per_en       (per_en),        // Peripheral enable (high active)
393
    .pmem_addr    (pmem_addr),     // Program Memory address
394
    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
395
    .pmem_din     (pmem_din),      // Program Memory data input (optional)
396
    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
397
 
398
// INPUTs
399
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
400
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
401
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
402
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
403
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
404
    .dmem_dout    (dmem_dout),     // Data Memory data output
405
    .eu_mab       (eu_mab[15:1]),  // Execution Unit Memory address bus
406
    .eu_mb_en     (eu_mb_en),      // Execution Unit Memory bus enable
407
    .eu_mb_wr     (eu_mb_wr),      // Execution Unit Memory bus write transfer
408
    .eu_mdb_out   (eu_mdb_out),    // Execution Unit Memory data bus output
409
    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
410
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
411
    .mclk         (mclk),          // Main system clock
412
    .per_dout     (per_dout_or),   // Peripheral data output
413
    .pmem_dout    (pmem_dout),     // Program Memory data output
414 136 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
415
    .scan_enable  (scan_enable)    // Scan enable (active during scan shifting)
416 80 olivier.gi
);
417
 
418
 
419
//=============================================================================
420
// 6)  SPECIAL FUNCTION REGISTERS
421
//=============================================================================
422
omsp_sfr sfr_0 (
423
 
424
// OUTPUTs
425 136 olivier.gi
    .cpu_id       (cpu_id),        // CPU ID
426
    .nmi_pnd      (nmi_pnd),       // NMI Pending
427
    .nmi_wkup     (nmi_wkup),      // NMI Wakeup
428 80 olivier.gi
    .per_dout     (per_dout_sfr),  // Peripheral data output
429
    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
430 136 olivier.gi
    .wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
431
    .wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
432 80 olivier.gi
 
433
// INPUTs
434
    .mclk         (mclk),          // Main system clock
435 136 olivier.gi
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
436 80 olivier.gi
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
437
    .per_addr     (per_addr),      // Peripheral address
438
    .per_din      (per_din),       // Peripheral data input
439
    .per_en       (per_en),        // Peripheral enable (high active)
440 107 olivier.gi
    .per_we       (per_we),        // Peripheral write enable (high active)
441 111 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
442 136 olivier.gi
    .scan_mode    (scan_mode),     // Scan mode
443
    .wdtifg       (wdtifg),        // Watchdog-timer interrupt flag
444
    .wdtnmies     (wdtnmies)       // Watchdog-timer NMI edge selection
445 80 olivier.gi
);
446
 
447
 
448
//=============================================================================
449
// 7)  WATCHDOG TIMER
450
//=============================================================================
451 136 olivier.gi
`ifdef WATCHDOG
452 80 olivier.gi
omsp_watchdog watchdog_0 (
453
 
454
// OUTPUTs
455 136 olivier.gi
    .per_dout       (per_dout_wdog), // Peripheral data output
456
    .wdt_irq        (wdt_irq),       // Watchdog-timer interrupt
457
    .wdt_reset      (wdt_reset),     // Watchdog-timer reset
458
    .wdt_wkup       (wdt_wkup),      // Watchdog Wakeup
459
    .wdtifg         (wdtifg),        // Watchdog-timer interrupt flag
460
    .wdtnmies       (wdtnmies),      // Watchdog-timer NMI edge selection
461 80 olivier.gi
 
462
// INPUTs
463 136 olivier.gi
    .aclk           (aclk),          // ACLK
464
    .aclk_en        (aclk_en),       // ACLK enable
465
    .dbg_freeze     (dbg_freeze),    // Freeze Watchdog counter
466
    .mclk           (mclk),          // Main system clock
467
    .per_addr       (per_addr),      // Peripheral address
468
    .per_din        (per_din),       // Peripheral data input
469
    .per_en         (per_en),        // Peripheral enable (high active)
470
    .per_we         (per_we),        // Peripheral write enable (high active)
471
    .por            (por),           // Power-on reset
472
    .puc_rst        (puc_rst),       // Main system reset
473
    .scan_enable    (scan_enable),   // Scan enable (active during scan shifting)
474
    .scan_mode      (scan_mode),     // Scan mode
475
    .smclk          (smclk),         // SMCLK
476
    .smclk_en       (smclk_en),      // SMCLK enable
477
    .wdtie          (wdtie),         // Watchdog-timer interrupt enable
478
    .wdtifg_irq_clr (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
479
    .wdtifg_sw_clr  (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
480
    .wdtifg_sw_set  (wdtifg_sw_set)  // Watchdog-timer interrupt flag software set
481 80 olivier.gi
);
482 136 olivier.gi
`else
483
assign per_dout_wdog = 16'h0000;
484
assign wdt_irq       =  1'b0;
485
assign wdt_reset     =  1'b0;
486
assign wdt_wkup      =  1'b0;
487
assign wdtifg        =  1'b0;
488
assign wdtnmies      =  1'b0;
489
`endif
490 80 olivier.gi
 
491
 
492
//=============================================================================
493
// 8)  HARDWARE MULTIPLIER
494
//=============================================================================
495
`ifdef MULTIPLIER
496
omsp_multiplier multiplier_0 (
497
 
498
// OUTPUTs
499
    .per_dout     (per_dout_mpy),  // Peripheral data output
500
 
501
// INPUTs
502
    .mclk         (mclk),          // Main system clock
503
    .per_addr     (per_addr),      // Peripheral address
504
    .per_din      (per_din),       // Peripheral data input
505
    .per_en       (per_en),        // Peripheral enable (high active)
506 107 olivier.gi
    .per_we       (per_we),        // Peripheral write enable (high active)
507 136 olivier.gi
    .puc_rst      (puc_rst),       // Main system reset
508
    .scan_enable  (scan_enable)    // Scan enable (active during scan shifting)
509 80 olivier.gi
);
510
`else
511
assign per_dout_mpy = 16'h0000;
512
`endif
513
 
514
//=============================================================================
515
// 9)  PERIPHERALS' OUTPUT BUS
516
//=============================================================================
517
 
518
assign  per_dout_or  =  per_dout      |
519
                        per_dout_clk  |
520
                        per_dout_sfr  |
521
                        per_dout_wdog |
522
                        per_dout_mpy;
523
 
524
 
525
//=============================================================================
526
// 10)  DEBUG INTERFACE
527
//=============================================================================
528
 
529
`ifdef DBG_EN
530
omsp_dbg dbg_0 (
531
 
532
// OUTPUTs
533
    .dbg_freeze   (dbg_freeze),    // Freeze peripherals
534
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
535
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
536
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
537
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
538
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
539
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
540 107 olivier.gi
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
541 80 olivier.gi
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
542
 
543
// INPUTs
544 107 olivier.gi
    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
545 136 olivier.gi
    .cpu_id       (cpu_id),        // CPU ID
546 107 olivier.gi
    .dbg_clk      (dbg_clk),       // Debug unit clock
547
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
548 80 olivier.gi
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
549
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
550
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
551 107 olivier.gi
    .dbg_rst      (dbg_rst),       // Debug unit reset
552
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD (asynchronous)
553 80 olivier.gi
    .decode_noirq (decode_noirq),  // Frontend decode instruction
554
    .eu_mab       (eu_mab),        // Execution-Unit Memory address bus
555
    .eu_mb_en     (eu_mb_en),      // Execution-Unit Memory bus enable
556
    .eu_mb_wr     (eu_mb_wr),      // Execution-Unit Memory bus write transfer
557
    .eu_mdb_in    (eu_mdb_in),     // Memory data bus input
558
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
559
    .exec_done    (exec_done),     // Execution completed
560
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
561
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
562
    .pc           (pc),            // Program counter
563 136 olivier.gi
    .puc_pnd_set  (puc_pnd_set)    // PUC pending set for the serial debug interface
564 80 olivier.gi
);
565
 
566
`else
567 107 olivier.gi
assign dbg_freeze    =  ~cpu_en_s;
568
assign dbg_halt_cmd  =  1'b0;
569
assign dbg_mem_addr  = 16'h0000;
570
assign dbg_mem_dout  = 16'h0000;
571
assign dbg_mem_en    =  1'b0;
572
assign dbg_mem_wr    =  2'b00;
573
assign dbg_reg_wr    =  1'b0;
574
assign dbg_cpu_reset =  1'b0;
575
assign dbg_uart_txd  =  1'b0;
576 80 olivier.gi
`endif
577
 
578
 
579
endmodule // openMSP430
580
 
581 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
582
`else
583 80 olivier.gi
`include "openMSP430_undefines.v"
584 104 olivier.gi
`endif

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