OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Blame information for rev 218

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 80 olivier.gi
//----------------------------------------------------------------------------
2 136 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 80 olivier.gi
//
4 136 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15 80 olivier.gi
//
16 136 olivier.gi
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27 80 olivier.gi
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: openMSP430.v
31 200 olivier.gi
//
32 80 olivier.gi
// *Module Description:
33
//                       openMSP430 Top level file
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39 202 olivier.gi
// $Rev: 103 $
40 80 olivier.gi
// $LastChangedBy: olivier.girard $
41 202 olivier.gi
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
42 80 olivier.gi
//----------------------------------------------------------------------------
43 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
44
`else
45 80 olivier.gi
`include "openMSP430_defines.v"
46 104 olivier.gi
`endif
47 80 olivier.gi
 
48
module  openMSP430 (
49
 
50
// OUTPUTs
51 202 olivier.gi
    aclk,                                    // ASIC ONLY: ACLK
52
    aclk_en,                                 // FPGA ONLY: ACLK enable
53
    dbg_freeze,                              // Freeze peripherals
54
    dbg_i2c_sda_out,                         // Debug interface: I2C SDA OUT
55
    dbg_uart_txd,                            // Debug interface: UART TXD
56
    dco_enable,                              // ASIC ONLY: Fast oscillator enable
57
    dco_wkup,                                // ASIC ONLY: Fast oscillator wake-up (asynchronous)
58
    dmem_addr,                               // Data Memory address
59
    dmem_cen,                                // Data Memory chip enable (low active)
60
    dmem_din,                                // Data Memory data input
61
    dmem_wen,                                // Data Memory write byte enable (low active)
62
    irq_acc,                                 // Interrupt request accepted (one-hot signal)
63
    lfxt_enable,                             // ASIC ONLY: Low frequency oscillator enable
64
    lfxt_wkup,                               // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
65
    mclk,                                    // Main system clock
66
    dma_dout,                                // Direct Memory Access data output
67
    dma_ready,                               // Direct Memory Access is complete
68
    dma_resp,                                // Direct Memory Access response (0:Okay / 1:Error)
69
    per_addr,                                // Peripheral address
70
    per_din,                                 // Peripheral data input
71
    per_en,                                  // Peripheral enable (high active)
72
    per_we,                                  // Peripheral write byte enable (high active)
73
    pmem_addr,                               // Program Memory address
74
    pmem_cen,                                // Program Memory chip enable (low active)
75
    pmem_din,                                // Program Memory data input (optional)
76
    pmem_wen,                                // Program Memory write byte enable (low active) (optional)
77
    puc_rst,                                 // Main system reset
78
    smclk,                                   // ASIC ONLY: SMCLK
79
    smclk_en,                                // FPGA ONLY: SMCLK enable
80 80 olivier.gi
 
81
// INPUTs
82 202 olivier.gi
    cpu_en,                                  // Enable CPU code execution (asynchronous and non-glitchy)
83
    dbg_en,                                  // Debug interface enable (asynchronous and non-glitchy)
84
    dbg_i2c_addr,                            // Debug interface: I2C Address
85
    dbg_i2c_broadcast,                       // Debug interface: I2C Broadcast Address (for multicore systems)
86
    dbg_i2c_scl,                             // Debug interface: I2C SCL
87
    dbg_i2c_sda_in,                          // Debug interface: I2C SDA IN
88
    dbg_uart_rxd,                            // Debug interface: UART RXD (asynchronous)
89
    dco_clk,                                 // Fast oscillator (fast clock)
90
    dmem_dout,                               // Data Memory data output
91
    irq,                                     // Maskable interrupts
92
    lfxt_clk,                                // Low frequency oscillator (typ 32kHz)
93
    dma_addr,                                // Direct Memory Access address
94
    dma_din,                                 // Direct Memory Access data input
95
    dma_en,                                  // Direct Memory Access enable (high active)
96
    dma_priority,                            // Direct Memory Access priority (0:low / 1:high)
97
    dma_we,                                  // Direct Memory Access write byte enable (high active)
98
    dma_wkup,                                // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
99
    nmi,                                     // Non-maskable interrupt (asynchronous)
100
    per_dout,                                // Peripheral data output
101
    pmem_dout,                               // Program Memory data output
102
    reset_n,                                 // Reset Pin (low active, asynchronous and non-glitchy)
103
    scan_enable,                             // ASIC ONLY: Scan enable (active during scan shifting)
104
    scan_mode,                               // ASIC ONLY: Scan mode
105
    wkup                                     // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
106 80 olivier.gi
);
107
 
108 155 olivier.gi
// PARAMETERs
109
//============
110 202 olivier.gi
parameter            INST_NR  = 8'h00;       // Current oMSP instance number     (for multicore systems)
111
parameter            TOTAL_NR = 8'h00;       // Total number of oMSP instances-1 (for multicore systems)
112 155 olivier.gi
 
113 80 olivier.gi
// OUTPUTs
114 155 olivier.gi
//============
115 202 olivier.gi
output               aclk;                   // ASIC ONLY: ACLK
116
output               aclk_en;                // FPGA ONLY: ACLK enable
117
output               dbg_freeze;             // Freeze peripherals
118
output               dbg_i2c_sda_out;        // Debug interface: I2C SDA OUT
119
output               dbg_uart_txd;           // Debug interface: UART TXD
120
output               dco_enable;             // ASIC ONLY: Fast oscillator enable
121
output               dco_wkup;               // ASIC ONLY: Fast oscillator wake-up (asynchronous)
122
output [`DMEM_MSB:0] dmem_addr;              // Data Memory address
123
output               dmem_cen;               // Data Memory chip enable (low active)
124
output        [15:0] dmem_din;               // Data Memory data input
125
output         [1:0] dmem_wen;               // Data Memory write byte enable (low active)
126
output [`IRQ_NR-3:0] irq_acc;                // Interrupt request accepted (one-hot signal)
127
output               lfxt_enable;            // ASIC ONLY: Low frequency oscillator enable
128
output               lfxt_wkup;              // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
129
output               mclk;                   // Main system clock
130
output        [15:0] dma_dout;               // Direct Memory Access data output
131
output               dma_ready;              // Direct Memory Access is complete
132
output               dma_resp;               // Direct Memory Access response (0:Okay / 1:Error)
133
output        [13:0] per_addr;               // Peripheral address
134
output        [15:0] per_din;                // Peripheral data input
135
output               per_en;                 // Peripheral enable (high active)
136
output         [1:0] per_we;                 // Peripheral write byte enable (high active)
137
output [`PMEM_MSB:0] pmem_addr;              // Program Memory address
138
output               pmem_cen;               // Program Memory chip enable (low active)
139
output        [15:0] pmem_din;               // Program Memory data input (optional)
140
output         [1:0] pmem_wen;               // Program Memory write enable (low active) (optional)
141
output               puc_rst;                // Main system reset
142
output               smclk;                  // ASIC ONLY: SMCLK
143
output               smclk_en;               // FPGA ONLY: SMCLK enable
144 80 olivier.gi
 
145
 
146
// INPUTs
147 155 olivier.gi
//============
148 202 olivier.gi
input                cpu_en;                 // Enable CPU code execution (asynchronous and non-glitchy)
149
input                dbg_en;                 // Debug interface enable (asynchronous and non-glitchy)
150
input          [6:0] dbg_i2c_addr;           // Debug interface: I2C Address
151
input          [6:0] dbg_i2c_broadcast;      // Debug interface: I2C Broadcast Address (for multicore systems)
152
input                dbg_i2c_scl;            // Debug interface: I2C SCL
153
input                dbg_i2c_sda_in;         // Debug interface: I2C SDA IN
154
input                dbg_uart_rxd;           // Debug interface: UART RXD (asynchronous)
155
input                dco_clk;                // Fast oscillator (fast clock)
156
input         [15:0] dmem_dout;              // Data Memory data output
157
input  [`IRQ_NR-3:0] irq;                    // Maskable interrupts (14, 30 or 62)
158
input                lfxt_clk;               // Low frequency oscillator (typ 32kHz)
159
input         [15:1] dma_addr;               // Direct Memory Access address
160
input         [15:0] dma_din;                // Direct Memory Access data input
161
input                dma_en;                 // Direct Memory Access enable (high active)
162
input                dma_priority;           // Direct Memory Access priority (0:low / 1:high)
163
input          [1:0] dma_we;                 // Direct Memory Access write byte enable (high active)
164
input                dma_wkup;               // ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy)
165
input                nmi;                    // Non-maskable interrupt (asynchronous and non-glitchy)
166
input         [15:0] per_dout;               // Peripheral data output
167
input         [15:0] pmem_dout;              // Program Memory data output
168
input                reset_n;                // Reset Pin (active low, asynchronous and non-glitchy)
169
input                scan_enable;            // ASIC ONLY: Scan enable (active during scan shifting)
170
input                scan_mode;              // ASIC ONLY: Scan mode
171
input                wkup;                   // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
172 80 olivier.gi
 
173
 
174
 
175
//=============================================================================
176
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
177
//=============================================================================
178
 
179 202 olivier.gi
wire           [7:0] inst_ad;
180
wire           [7:0] inst_as;
181
wire          [11:0] inst_alu;
182
wire                 inst_bw;
183
wire                 inst_irq_rst;
184
wire                 inst_mov;
185
wire          [15:0] inst_dest;
186
wire          [15:0] inst_dext;
187
wire          [15:0] inst_sext;
188
wire           [7:0] inst_so;
189
wire          [15:0] inst_src;
190
wire           [2:0] inst_type;
191
wire           [7:0] inst_jmp;
192
wire           [3:0] e_state;
193
wire                 exec_done;
194
wire                 decode_noirq;
195
wire                 cpu_en_s;
196
wire                 cpuoff;
197
wire                 oscoff;
198
wire                 scg0;
199
wire                 scg1;
200
wire                 por;
201
wire                 gie;
202
wire                 cpu_mclk;
203
wire                 dma_mclk;
204
wire                 mclk_dma_enable;
205
wire                 mclk_dma_wkup;
206
wire                 mclk_enable;
207
wire                 mclk_wkup;
208
wire          [31:0] cpu_id;
209
wire           [7:0] cpu_nr_inst  = INST_NR;
210
wire           [7:0] cpu_nr_total = TOTAL_NR;
211 200 olivier.gi
 
212 202 olivier.gi
wire          [15:0] eu_mab;
213
wire          [15:0] eu_mdb_in;
214
wire          [15:0] eu_mdb_out;
215
wire           [1:0] eu_mb_wr;
216
wire                 eu_mb_en;
217
wire          [15:0] fe_mab;
218
wire          [15:0] fe_mdb_in;
219
wire                 fe_mb_en;
220
wire                 fe_pmem_wait;
221 80 olivier.gi
 
222 202 olivier.gi
wire                 pc_sw_wr;
223
wire          [15:0] pc_sw;
224
wire          [15:0] pc;
225
wire          [15:0] pc_nxt;
226 80 olivier.gi
 
227 202 olivier.gi
wire                 nmi_acc;
228
wire                 nmi_pnd;
229
wire                 nmi_wkup;
230 111 olivier.gi
 
231 202 olivier.gi
wire                 wdtie;
232
wire                 wdtnmies;
233
wire                 wdtifg;
234
wire                 wdt_irq;
235
wire                 wdt_wkup;
236
wire                 wdt_reset;
237
wire                 wdtifg_sw_clr;
238
wire                 wdtifg_sw_set;
239 111 olivier.gi
 
240 202 olivier.gi
wire                 dbg_clk;
241
wire                 dbg_rst;
242
wire                 dbg_en_s;
243
wire                 dbg_halt_cmd;
244
wire                 dbg_mem_en;
245
wire                 dbg_reg_wr;
246
wire                 dbg_cpu_reset;
247
wire          [15:0] dbg_mem_addr;
248
wire          [15:0] dbg_mem_dout;
249
wire          [15:0] dbg_mem_din;
250
wire          [15:0] dbg_reg_din;
251
wire           [1:0] dbg_mem_wr;
252 200 olivier.gi
 
253 202 olivier.gi
wire                 cpu_halt_st;
254
wire                 cpu_halt_cmd;
255
wire                 puc_pnd_set;
256 80 olivier.gi
 
257 202 olivier.gi
wire          [15:0] per_dout_or;
258
wire          [15:0] per_dout_sfr;
259
wire          [15:0] per_dout_wdog;
260
wire          [15:0] per_dout_mpy;
261
wire          [15:0] per_dout_clk;
262 200 olivier.gi
 
263 202 olivier.gi
 
264 80 olivier.gi
//=============================================================================
265
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
266
//=============================================================================
267
 
268
omsp_clock_module clock_module_0 (
269
 
270
// OUTPUTs
271 202 olivier.gi
    .aclk              (aclk),               // ACLK
272
    .aclk_en           (aclk_en),            // ACLK enablex
273
    .cpu_en_s          (cpu_en_s),           // Enable CPU code execution (synchronous)
274
    .cpu_mclk          (cpu_mclk),           // Main system CPU only clock
275
    .dma_mclk          (dma_mclk),           // Main system DMA and/or CPU clock
276
    .dbg_clk           (dbg_clk),            // Debug unit clock
277
    .dbg_en_s          (dbg_en_s),           // Debug interface enable (synchronous)
278
    .dbg_rst           (dbg_rst),            // Debug unit reset
279
    .dco_enable        (dco_enable),         // Fast oscillator enable
280
    .dco_wkup          (dco_wkup),           // Fast oscillator wake-up (asynchronous)
281
    .lfxt_enable       (lfxt_enable),        // Low frequency oscillator enable
282
    .lfxt_wkup         (lfxt_wkup),          // Low frequency oscillator wake-up (asynchronous)
283
    .per_dout          (per_dout_clk),       // Peripheral data output
284
    .por               (por),                // Power-on reset
285
    .puc_pnd_set       (puc_pnd_set),        // PUC pending set for the serial debug interface
286
    .puc_rst           (puc_rst),            // Main system reset
287
    .smclk             (smclk),              // SMCLK
288
    .smclk_en          (smclk_en),           // SMCLK enable
289 200 olivier.gi
 
290 80 olivier.gi
// INPUTs
291 202 olivier.gi
    .cpu_en            (cpu_en),             // Enable CPU code execution (asynchronous)
292
    .cpuoff            (cpuoff),             // Turns off the CPU
293
    .dbg_cpu_reset     (dbg_cpu_reset),      // Reset CPU from debug interface
294
    .dbg_en            (dbg_en),             // Debug interface enable (asynchronous)
295
    .dco_clk           (dco_clk),            // Fast oscillator (fast clock)
296
    .lfxt_clk          (lfxt_clk),           // Low frequency oscillator (typ 32kHz)
297
    .mclk_dma_enable   (mclk_dma_enable),    // DMA Sub-System Clock enable
298
    .mclk_dma_wkup     (mclk_dma_wkup),      // DMA Sub-System Clock wake-up (asynchronous)
299
    .mclk_enable       (mclk_enable),        // Main System Clock enable
300
    .mclk_wkup         (mclk_wkup),          // Main System Clock wake-up (asynchronous)
301
    .oscoff            (oscoff),             // Turns off LFXT1 clock input
302
    .per_addr          (per_addr),           // Peripheral address
303
    .per_din           (per_din),            // Peripheral data input
304
    .per_en            (per_en),             // Peripheral enable (high active)
305
    .per_we            (per_we),             // Peripheral write enable (high active)
306
    .reset_n           (reset_n),            // Reset Pin (low active, asynchronous)
307
    .scan_enable       (scan_enable),        // Scan enable (active during scan shifting)
308
    .scan_mode         (scan_mode),          // Scan mode
309
    .scg0              (scg0),               // System clock generator 1. Turns off the DCO
310
    .scg1              (scg1),               // System clock generator 1. Turns off the SMCLK
311
    .wdt_reset         (wdt_reset)           // Watchdog-timer reset
312 80 olivier.gi
);
313
 
314 202 olivier.gi
assign mclk = dma_mclk;
315 200 olivier.gi
 
316 202 olivier.gi
 
317 80 olivier.gi
//=============================================================================
318
// 3)  FRONTEND (<=> FETCH & DECODE)
319
//=============================================================================
320
 
321
omsp_frontend frontend_0 (
322
 
323
// OUTPUTs
324 202 olivier.gi
    .cpu_halt_st       (cpu_halt_st),        // Halt/Run status from CPU
325
    .decode_noirq      (decode_noirq),       // Frontend decode instruction
326
    .e_state           (e_state),            // Execution state
327
    .exec_done         (exec_done),          // Execution completed
328
    .inst_ad           (inst_ad),            // Decoded Inst: destination addressing mode
329
    .inst_as           (inst_as),            // Decoded Inst: source addressing mode
330
    .inst_alu          (inst_alu),           // ALU control signals
331
    .inst_bw           (inst_bw),            // Decoded Inst: byte width
332
    .inst_dest         (inst_dest),          // Decoded Inst: destination (one hot)
333
    .inst_dext         (inst_dext),          // Decoded Inst: destination extended instruction word
334
    .inst_irq_rst      (inst_irq_rst),       // Decoded Inst: Reset interrupt
335
    .inst_jmp          (inst_jmp),           // Decoded Inst: Conditional jump
336
    .inst_mov          (inst_mov),           // Decoded Inst: mov instruction
337
    .inst_sext         (inst_sext),          // Decoded Inst: source extended instruction word
338
    .inst_so           (inst_so),            // Decoded Inst: Single-operand arithmetic
339
    .inst_src          (inst_src),           // Decoded Inst: source (one hot)
340
    .inst_type         (inst_type),          // Decoded Instruction type
341
    .irq_acc           (irq_acc),            // Interrupt request accepted
342
    .mab               (fe_mab),             // Frontend Memory address bus
343
    .mb_en             (fe_mb_en),           // Frontend Memory bus enable
344
    .mclk_dma_enable   (mclk_dma_enable),    // DMA Sub-System Clock enable
345
    .mclk_dma_wkup     (mclk_dma_wkup),      // DMA Sub-System Clock wake-up (asynchronous)
346
    .mclk_enable       (mclk_enable),        // Main System Clock enable
347
    .mclk_wkup         (mclk_wkup),          // Main System Clock wake-up (asynchronous)
348
    .nmi_acc           (nmi_acc),            // Non-Maskable interrupt request accepted
349
    .pc                (pc),                 // Program counter
350
    .pc_nxt            (pc_nxt),             // Next PC value (for CALL & IRQ)
351 200 olivier.gi
 
352 80 olivier.gi
// INPUTs
353 202 olivier.gi
    .cpu_en_s          (cpu_en_s),           // Enable CPU code execution (synchronous)
354
    .cpu_halt_cmd      (cpu_halt_cmd),       // Halt CPU command
355
    .cpuoff            (cpuoff),             // Turns off the CPU
356
    .dbg_reg_sel       (dbg_mem_addr[3:0]),  // Debug selected register for rd/wr access
357
    .dma_en            (dma_en),             // Direct Memory Access enable (high active)
358
    .dma_wkup          (dma_wkup),           // DMA Sub-System Wake-up (asynchronous and non-glitchy)
359
    .fe_pmem_wait      (fe_pmem_wait),       // Frontend wait for Instruction fetch
360
    .gie               (gie),                // General interrupt enable
361
    .irq               (irq),                // Maskable interrupts
362
    .mclk              (cpu_mclk),           // Main system clock
363
    .mdb_in            (fe_mdb_in),          // Frontend Memory data bus input
364
    .nmi_pnd           (nmi_pnd),            // Non-maskable interrupt pending
365
    .nmi_wkup          (nmi_wkup),           // NMI Wakeup
366
    .pc_sw             (pc_sw),              // Program counter software value
367
    .pc_sw_wr          (pc_sw_wr),           // Program counter software write
368
    .puc_rst           (puc_rst),            // Main system reset
369
    .scan_enable       (scan_enable),        // Scan enable (active during scan shifting)
370
    .wdt_irq           (wdt_irq),            // Watchdog-timer interrupt
371
    .wdt_wkup          (wdt_wkup),           // Watchdog Wakeup
372
    .wkup              (wkup)                // System Wake-up (asynchronous)
373 80 olivier.gi
);
374
 
375
 
376
//=============================================================================
377
// 4)  EXECUTION UNIT
378
//=============================================================================
379
 
380
omsp_execution_unit execution_unit_0 (
381
 
382
// OUTPUTs
383 202 olivier.gi
    .cpuoff            (cpuoff),             // Turns off the CPU
384
    .dbg_reg_din       (dbg_reg_din),        // Debug unit CPU register data input
385
    .mab               (eu_mab),             // Memory address bus
386
    .mb_en             (eu_mb_en),           // Memory bus enable
387
    .mb_wr             (eu_mb_wr),           // Memory bus write transfer
388
    .mdb_out           (eu_mdb_out),         // Memory data bus output
389
    .oscoff            (oscoff),             // Turns off LFXT1 clock input
390
    .pc_sw             (pc_sw),              // Program counter software value
391
    .pc_sw_wr          (pc_sw_wr),           // Program counter software write
392
    .scg0              (scg0),               // System clock generator 1. Turns off the DCO
393
    .scg1              (scg1),               // System clock generator 1. Turns off the SMCLK
394 80 olivier.gi
 
395
// INPUTs
396 202 olivier.gi
    .dbg_halt_st       (cpu_halt_st),        // Halt/Run status from CPU
397
    .dbg_mem_dout      (dbg_mem_dout),       // Debug unit data output
398
    .dbg_reg_wr        (dbg_reg_wr),         // Debug unit CPU register write
399
    .e_state           (e_state),            // Execution state
400
    .exec_done         (exec_done),          // Execution completed
401
    .gie               (gie),                // General interrupt enable
402
    .inst_ad           (inst_ad),            // Decoded Inst: destination addressing mode
403
    .inst_as           (inst_as),            // Decoded Inst: source addressing mode
404
    .inst_alu          (inst_alu),           // ALU control signals
405
    .inst_bw           (inst_bw),            // Decoded Inst: byte width
406
    .inst_dest         (inst_dest),          // Decoded Inst: destination (one hot)
407
    .inst_dext         (inst_dext),          // Decoded Inst: destination extended instruction word
408
    .inst_irq_rst      (inst_irq_rst),       // Decoded Inst: reset interrupt
409
    .inst_jmp          (inst_jmp),           // Decoded Inst: Conditional jump
410
    .inst_mov          (inst_mov),           // Decoded Inst: mov instruction
411
    .inst_sext         (inst_sext),          // Decoded Inst: source extended instruction word
412
    .inst_so           (inst_so),            // Decoded Inst: Single-operand arithmetic
413
    .inst_src          (inst_src),           // Decoded Inst: source (one hot)
414
    .inst_type         (inst_type),          // Decoded Instruction type
415
    .mclk              (cpu_mclk),           // Main system clock
416
    .mdb_in            (eu_mdb_in),          // Memory data bus input
417
    .pc                (pc),                 // Program counter
418
    .pc_nxt            (pc_nxt),             // Next PC value (for CALL & IRQ)
419
    .puc_rst           (puc_rst),            // Main system reset
420
    .scan_enable       (scan_enable)         // Scan enable (active during scan shifting)
421 80 olivier.gi
);
422
 
423
 
424
//=============================================================================
425
// 5)  MEMORY BACKBONE
426
//=============================================================================
427
 
428
omsp_mem_backbone mem_backbone_0 (
429
 
430
// OUTPUTs
431 202 olivier.gi
    .cpu_halt_cmd      (cpu_halt_cmd),       // Halt CPU command
432
    .dbg_mem_din       (dbg_mem_din),        // Debug unit Memory data input
433
    .dmem_addr         (dmem_addr),          // Data Memory address
434
    .dmem_cen          (dmem_cen),           // Data Memory chip enable (low active)
435
    .dmem_din          (dmem_din),           // Data Memory data input
436
    .dmem_wen          (dmem_wen),           // Data Memory write enable (low active)
437
    .eu_mdb_in         (eu_mdb_in),          // Execution Unit Memory data bus input
438
    .fe_mdb_in         (fe_mdb_in),          // Frontend Memory data bus input
439
    .fe_pmem_wait      (fe_pmem_wait),       // Frontend wait for Instruction fetch
440
    .dma_dout          (dma_dout),           // Direct Memory Access data output
441
    .dma_ready         (dma_ready),          // Direct Memory Access is complete
442
    .dma_resp          (dma_resp),           // Direct Memory Access response (0:Okay / 1:Error)
443
    .per_addr          (per_addr),           // Peripheral address
444
    .per_din           (per_din),            // Peripheral data input
445
    .per_we            (per_we),             // Peripheral write enable (high active)
446
    .per_en            (per_en),             // Peripheral enable (high active)
447
    .pmem_addr         (pmem_addr),          // Program Memory address
448
    .pmem_cen          (pmem_cen),           // Program Memory chip enable (low active)
449
    .pmem_din          (pmem_din),           // Program Memory data input (optional)
450
    .pmem_wen          (pmem_wen),           // Program Memory write enable (low active) (optional)
451 200 olivier.gi
 
452 80 olivier.gi
// INPUTs
453 202 olivier.gi
    .cpu_halt_st       (cpu_halt_st),        // Halt/Run status from CPU
454
    .dbg_halt_cmd      (dbg_halt_cmd),       // Debug interface Halt CPU command
455
    .dbg_mem_addr      (dbg_mem_addr[15:1]), // Debug address for rd/wr access
456
    .dbg_mem_dout      (dbg_mem_dout),       // Debug unit data output
457
    .dbg_mem_en        (dbg_mem_en),         // Debug unit memory enable
458
    .dbg_mem_wr        (dbg_mem_wr),         // Debug unit memory write
459
    .dmem_dout         (dmem_dout),          // Data Memory data output
460
    .eu_mab            (eu_mab[15:1]),       // Execution Unit Memory address bus
461
    .eu_mb_en          (eu_mb_en),           // Execution Unit Memory bus enable
462
    .eu_mb_wr          (eu_mb_wr),           // Execution Unit Memory bus write transfer
463
    .eu_mdb_out        (eu_mdb_out),         // Execution Unit Memory data bus output
464
    .fe_mab            (fe_mab[15:1]),       // Frontend Memory address bus
465
    .fe_mb_en          (fe_mb_en),           // Frontend Memory bus enable
466
    .mclk              (dma_mclk),           // Main system clock
467
    .dma_addr          (dma_addr),           // Direct Memory Access address
468
    .dma_din           (dma_din),            // Direct Memory Access data input
469
    .dma_en            (dma_en),             // Direct Memory Access enable (high active)
470
    .dma_priority      (dma_priority),       // Direct Memory Access priority (0:low / 1:high)
471
    .dma_we            (dma_we),             // Direct Memory Access write byte enable (high active)
472
    .per_dout          (per_dout_or),        // Peripheral data output
473
    .pmem_dout         (pmem_dout),          // Program Memory data output
474
    .puc_rst           (puc_rst),            // Main system reset
475
    .scan_enable       (scan_enable)         // Scan enable (active during scan shifting)
476 80 olivier.gi
);
477
 
478 202 olivier.gi
wire UNUSED_fe_mab_0 = fe_mab[0];
479 80 olivier.gi
 
480
//=============================================================================
481
// 6)  SPECIAL FUNCTION REGISTERS
482
//=============================================================================
483
omsp_sfr sfr_0 (
484
 
485
// OUTPUTs
486 202 olivier.gi
    .cpu_id            (cpu_id),             // CPU ID
487
    .nmi_pnd           (nmi_pnd),            // NMI Pending
488
    .nmi_wkup          (nmi_wkup),           // NMI Wakeup
489
    .per_dout          (per_dout_sfr),       // Peripheral data output
490
    .wdtie             (wdtie),              // Watchdog-timer interrupt enable
491
    .wdtifg_sw_clr     (wdtifg_sw_clr),      // Watchdog-timer interrupt flag software clear
492
    .wdtifg_sw_set     (wdtifg_sw_set),      // Watchdog-timer interrupt flag software set
493 200 olivier.gi
 
494 80 olivier.gi
// INPUTs
495 202 olivier.gi
    .cpu_nr_inst       (cpu_nr_inst),        // Current oMSP instance number
496
    .cpu_nr_total      (cpu_nr_total),       // Total number of oMSP instances-1
497
    .mclk              (dma_mclk),           // Main system clock
498
    .nmi               (nmi),                // Non-maskable interrupt (asynchronous)
499
    .nmi_acc           (nmi_acc),            // Non-Maskable interrupt request accepted
500
    .per_addr          (per_addr),           // Peripheral address
501
    .per_din           (per_din),            // Peripheral data input
502
    .per_en            (per_en),             // Peripheral enable (high active)
503
    .per_we            (per_we),             // Peripheral write enable (high active)
504
    .puc_rst           (puc_rst),            // Main system reset
505
    .scan_mode         (scan_mode),          // Scan mode
506
    .wdtifg            (wdtifg),             // Watchdog-timer interrupt flag
507
    .wdtnmies          (wdtnmies)            // Watchdog-timer NMI edge selection
508 80 olivier.gi
);
509
 
510
 
511
//=============================================================================
512
// 7)  WATCHDOG TIMER
513
//=============================================================================
514 136 olivier.gi
`ifdef WATCHDOG
515 80 olivier.gi
omsp_watchdog watchdog_0 (
516
 
517
// OUTPUTs
518 202 olivier.gi
    .per_dout          (per_dout_wdog),      // Peripheral data output
519
    .wdt_irq           (wdt_irq),            // Watchdog-timer interrupt
520
    .wdt_reset         (wdt_reset),          // Watchdog-timer reset
521
    .wdt_wkup          (wdt_wkup),           // Watchdog Wakeup
522
    .wdtifg            (wdtifg),             // Watchdog-timer interrupt flag
523
    .wdtnmies          (wdtnmies),           // Watchdog-timer NMI edge selection
524 200 olivier.gi
 
525 80 olivier.gi
// INPUTs
526 202 olivier.gi
    .aclk              (aclk),               // ACLK
527
    .aclk_en           (aclk_en),            // ACLK enable
528
    .dbg_freeze        (dbg_freeze),         // Freeze Watchdog counter
529
    .mclk              (dma_mclk),           // Main system clock
530
    .per_addr          (per_addr),           // Peripheral address
531
    .per_din           (per_din),            // Peripheral data input
532
    .per_en            (per_en),             // Peripheral enable (high active)
533
    .per_we            (per_we),             // Peripheral write enable (high active)
534
    .por               (por),                // Power-on reset
535
    .puc_rst           (puc_rst),            // Main system reset
536
    .scan_enable       (scan_enable),        // Scan enable (active during scan shifting)
537
    .scan_mode         (scan_mode),          // Scan mode
538
    .smclk             (smclk),              // SMCLK
539
    .smclk_en          (smclk_en),           // SMCLK enable
540
    .wdtie             (wdtie),              // Watchdog-timer interrupt enable
541
    .wdtifg_irq_clr    (irq_acc[`IRQ_NR-6]), // Clear Watchdog-timer interrupt flag
542
    .wdtifg_sw_clr     (wdtifg_sw_clr),      // Watchdog-timer interrupt flag software clear
543
    .wdtifg_sw_set     (wdtifg_sw_set)       // Watchdog-timer interrupt flag software set
544 80 olivier.gi
);
545 136 olivier.gi
`else
546 202 olivier.gi
assign per_dout_wdog        = 16'h0000;
547
assign wdt_irq              =  1'b0;
548
assign wdt_reset            =  1'b0;
549
assign wdt_wkup             =  1'b0;
550
assign wdtifg               =  1'b0;
551
assign wdtnmies             =  1'b0;
552
wire   UNUSED_por           =  por;
553
wire   UNUSED_wdtie         =  wdtie;
554
wire   UNUSED_wdtifg_sw_clr =  wdtifg_sw_clr;
555
wire   UNUSED_wdtifg_sw_set =  wdtifg_sw_set;
556 136 olivier.gi
`endif
557 80 olivier.gi
 
558
 
559
//=============================================================================
560
// 8)  HARDWARE MULTIPLIER
561
//=============================================================================
562
`ifdef MULTIPLIER
563
omsp_multiplier multiplier_0 (
564
 
565
// OUTPUTs
566 202 olivier.gi
    .per_dout          (per_dout_mpy),       // Peripheral data output
567 200 olivier.gi
 
568 80 olivier.gi
// INPUTs
569 202 olivier.gi
    .mclk              (dma_mclk),           // Main system clock
570
    .per_addr          (per_addr),           // Peripheral address
571
    .per_din           (per_din),            // Peripheral data input
572
    .per_en            (per_en),             // Peripheral enable (high active)
573
    .per_we            (per_we),             // Peripheral write enable (high active)
574
    .puc_rst           (puc_rst),            // Main system reset
575
    .scan_enable       (scan_enable)         // Scan enable (active during scan shifting)
576 80 olivier.gi
);
577
`else
578
assign per_dout_mpy = 16'h0000;
579
`endif
580 200 olivier.gi
 
581 80 olivier.gi
//=============================================================================
582
// 9)  PERIPHERALS' OUTPUT BUS
583
//=============================================================================
584
 
585
assign  per_dout_or  =  per_dout      |
586
                        per_dout_clk  |
587
                        per_dout_sfr  |
588
                        per_dout_wdog |
589
                        per_dout_mpy;
590
 
591 200 olivier.gi
 
592 80 olivier.gi
//=============================================================================
593
// 10)  DEBUG INTERFACE
594
//=============================================================================
595
 
596
`ifdef DBG_EN
597
omsp_dbg dbg_0 (
598
 
599
// OUTPUTs
600 202 olivier.gi
    .dbg_cpu_reset     (dbg_cpu_reset),      // Reset CPU from debug interface
601
    .dbg_freeze        (dbg_freeze),         // Freeze peripherals
602
    .dbg_halt_cmd      (dbg_halt_cmd),       // Halt CPU command
603
    .dbg_i2c_sda_out   (dbg_i2c_sda_out),    // Debug interface: I2C SDA OUT
604
    .dbg_mem_addr      (dbg_mem_addr),       // Debug address for rd/wr access
605
    .dbg_mem_dout      (dbg_mem_dout),       // Debug unit data output
606
    .dbg_mem_en        (dbg_mem_en),         // Debug unit memory enable
607
    .dbg_mem_wr        (dbg_mem_wr),         // Debug unit memory write
608
    .dbg_reg_wr        (dbg_reg_wr),         // Debug unit CPU register write
609
    .dbg_uart_txd      (dbg_uart_txd),       // Debug interface: UART TXD
610 200 olivier.gi
 
611 80 olivier.gi
// INPUTs
612 202 olivier.gi
    .cpu_en_s          (cpu_en_s),           // Enable CPU code execution (synchronous)
613
    .cpu_id            (cpu_id),             // CPU ID
614
    .cpu_nr_inst       (cpu_nr_inst),        // Current oMSP instance number
615
    .cpu_nr_total      (cpu_nr_total),       // Total number of oMSP instances-1
616
    .dbg_clk           (dbg_clk),            // Debug unit clock
617
    .dbg_en_s          (dbg_en_s),           // Debug interface enable (synchronous)
618
    .dbg_halt_st       (cpu_halt_st),        // Halt/Run status from CPU
619
    .dbg_i2c_addr      (dbg_i2c_addr),       // Debug interface: I2C Address
620
    .dbg_i2c_broadcast (dbg_i2c_broadcast),  // Debug interface: I2C Broadcast Address (for multicore systems)
621
    .dbg_i2c_scl       (dbg_i2c_scl),        // Debug interface: I2C SCL
622
    .dbg_i2c_sda_in    (dbg_i2c_sda_in),     // Debug interface: I2C SDA IN
623
    .dbg_mem_din       (dbg_mem_din),        // Debug unit Memory data input
624
    .dbg_reg_din       (dbg_reg_din),        // Debug unit CPU register data input
625
    .dbg_rst           (dbg_rst),            // Debug unit reset
626
    .dbg_uart_rxd      (dbg_uart_rxd),       // Debug interface: UART RXD (asynchronous)
627
    .decode_noirq      (decode_noirq),       // Frontend decode instruction
628
    .eu_mab            (eu_mab),             // Execution-Unit Memory address bus
629
    .eu_mb_en          (eu_mb_en),           // Execution-Unit Memory bus enable
630
    .eu_mb_wr          (eu_mb_wr),           // Execution-Unit Memory bus write transfer
631
    .fe_mdb_in         (fe_mdb_in),          // Frontend Memory data bus input
632
    .pc                (pc),                 // Program counter
633
    .puc_pnd_set       (puc_pnd_set)         // PUC pending set for the serial debug interface
634 80 olivier.gi
);
635
 
636
`else
637 202 olivier.gi
assign      dbg_cpu_reset            =  1'b0;
638
assign      dbg_freeze               =  ~cpu_en_s;
639
assign      dbg_halt_cmd             =  1'b0;
640
assign      dbg_i2c_sda_out          =  1'b1;
641
assign      dbg_mem_addr             = 16'h0000;
642
assign      dbg_mem_dout             = 16'h0000;
643
assign      dbg_mem_en               =  1'b0;
644
assign      dbg_mem_wr               =  2'b00;
645
assign      dbg_reg_wr               =  1'b0;
646
assign      dbg_uart_txd             =  1'b1;
647
wire        UNUSED_decode_noirq      = decode_noirq;
648
wire [31:0] UNUSED_cpu_id            = cpu_id;
649
wire        UNUSED_eu_mab_0          = eu_mab[0];
650
wire        UNUSED_dbg_clk           = dbg_clk;
651
wire        UNUSED_dbg_rst           = dbg_rst;
652
wire        UNUSED_dbg_en_s          = dbg_en_s;
653
wire [15:0] UNUSED_dbg_mem_din       = dbg_mem_din;
654
wire [15:0] UNUSED_dbg_reg_din       = dbg_reg_din;
655
wire        UNUSED_puc_pnd_set       = puc_pnd_set;
656
wire  [6:0] UNUSED_dbg_i2c_addr      = dbg_i2c_addr;
657
wire  [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
658
wire        UNUSED_dbg_i2c_scl       = dbg_i2c_scl;
659
wire        UNUSED_dbg_i2c_sda_in    = dbg_i2c_sda_in;
660
wire        UNUSED_dbg_uart_rxd      = dbg_uart_rxd;
661 80 olivier.gi
`endif
662
 
663 200 olivier.gi
 
664 80 olivier.gi
endmodule // openMSP430
665
 
666 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
667
`else
668 80 olivier.gi
`include "openMSP430_undefines.v"
669 104 olivier.gi
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.