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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Blame information for rev 86

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1 80 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25
// *File Name: openMSP430.v
26
// 
27
// *Module Description:
28
//                       openMSP430 Top level file
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34
// $Rev: 71 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2010-03-07 21:14:33 +0100 (Sun, 07 Mar 2010) $
37
//----------------------------------------------------------------------------
38
`include "timescale.v"
39
`include "openMSP430_defines.v"
40
 
41
module  openMSP430 (
42
 
43
// OUTPUTs
44
    aclk_en,                       // ACLK enable
45
    dbg_freeze,                    // Freeze peripherals
46
    dbg_uart_txd,                  // Debug interface: UART TXD
47
    dmem_addr,                     // Data Memory address
48
    dmem_cen,                      // Data Memory chip enable (low active)
49
    dmem_din,                      // Data Memory data input
50
    dmem_wen,                      // Data Memory write enable (low active)
51
    irq_acc,                       // Interrupt request accepted (one-hot signal)
52
    mclk,                          // Main system clock
53
    per_addr,                      // Peripheral address
54
    per_din,                       // Peripheral data input
55
    per_wen,                       // Peripheral write enable (high active)
56
    per_en,                        // Peripheral enable (high active)
57
    pmem_addr,                     // Program Memory address
58
    pmem_cen,                      // Program Memory chip enable (low active)
59
    pmem_din,                      // Program Memory data input (optional)
60
    pmem_wen,                      // Program Memory write enable (low active) (optional)
61
    puc,                           // Main system reset
62
    smclk_en,                      // SMCLK enable
63
 
64
// INPUTs
65
    dbg_uart_rxd,                  // Debug interface: UART RXD
66
    dco_clk,                       // Fast oscillator (fast clock)
67
    dmem_dout,                     // Data Memory data output
68
    irq,                           // Maskable interrupts
69
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
70
    nmi,                           // Non-maskable interrupt (asynchronous)
71
    per_dout,                      // Peripheral data output
72
    pmem_dout,                     // Program Memory data output
73
    reset_n                        // Reset Pin (low active)
74
);
75
 
76
// OUTPUTs
77
//=========
78
output               aclk_en;      // ACLK enable
79
output               dbg_freeze;   // Freeze peripherals
80
output               dbg_uart_txd; // Debug interface: UART TXD
81
output [`DMEM_MSB:0] dmem_addr;    // Data Memory address
82
output               dmem_cen;     // Data Memory chip enable (low active)
83
output        [15:0] dmem_din;     // Data Memory data input
84
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
85
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
86
output               mclk;         // Main system clock
87
output         [7:0] per_addr;     // Peripheral address
88
output        [15:0] per_din;      // Peripheral data input
89
output         [1:0] per_wen;      // Peripheral write enable (high active)
90
output               per_en;       // Peripheral enable (high active)
91
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
92
output               pmem_cen;     // Program Memory chip enable (low active)
93
output        [15:0] pmem_din;     // Program Memory data input (optional)
94
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
95
output               puc;          // Main system reset
96
output               smclk_en;     // SMCLK enable
97
 
98
 
99
// INPUTs
100
//=========
101
input                dbg_uart_rxd; // Debug interface: UART RXD
102
input                dco_clk;      // Fast oscillator (fast clock)
103
input         [15:0] dmem_dout;    // Data Memory data output
104
input         [13:0] irq;          // Maskable interrupts
105
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
106
input                nmi;          // Non-maskable interrupt (asynchronous)
107
input         [15:0] per_dout;     // Peripheral data output
108
input         [15:0] pmem_dout;    // Program Memory data output
109
input                reset_n;      // Reset Pin (active low)
110
 
111
 
112
 
113
//=============================================================================
114
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
115
//=============================================================================
116
 
117
wire          [7:0] inst_ad;
118
wire          [7:0] inst_as;
119
wire         [11:0] inst_alu;
120
wire                inst_bw;
121
wire         [15:0] inst_dest;
122
wire         [15:0] inst_dext;
123
wire         [15:0] inst_sext;
124
wire          [7:0] inst_so;
125
wire         [15:0] inst_src;
126
wire          [2:0] inst_type;
127
wire          [3:0] e_state;
128
wire                exec_done;
129
 
130
wire         [15:0] eu_mab;
131
wire         [15:0] eu_mdb_in;
132
wire         [15:0] eu_mdb_out;
133
wire          [1:0] eu_mb_wr;
134
wire         [15:0] fe_mab;
135
wire         [15:0] fe_mdb_in;
136
 
137
wire         [15:0] pc_sw;
138
wire          [7:0] inst_jmp;
139
wire         [15:0] pc;
140
wire         [15:0] pc_nxt;
141
 
142 86 olivier.gi
wire                dbg_halt_cmd;
143
wire                dbg_mem_en;
144
wire                dbg_reg_wr;
145
wire                dbg_reset;
146 80 olivier.gi
wire         [15:0] dbg_mem_addr;
147
wire         [15:0] dbg_mem_dout;
148
wire         [15:0] dbg_mem_din;
149
wire         [15:0] dbg_reg_din;
150
wire          [1:0] dbg_mem_wr;
151
 
152
wire         [15:0] per_dout_or;
153
wire         [15:0] per_dout_sfr;
154
wire         [15:0] per_dout_wdog;
155
wire         [15:0] per_dout_mpy;
156
wire         [15:0] per_dout_clk;
157
 
158
 
159
//=============================================================================
160
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
161
//=============================================================================
162
 
163
omsp_clock_module clock_module_0 (
164
 
165
// OUTPUTs
166
    .aclk_en      (aclk_en),       // ACLK enablex
167
    .mclk         (mclk),          // Main system clock
168
    .per_dout     (per_dout_clk),  // Peripheral data output
169
    .por          (por),           // Power-on reset
170
    .puc          (puc),           // Main system reset
171
    .smclk_en     (smclk_en),      // SMCLK enable
172
 
173
// INPUTs
174
    .dbg_reset    (dbg_reset),     // Reset CPU from debug interface
175
    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
176
    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
177
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
178
    .per_addr     (per_addr),      // Peripheral address
179
    .per_din      (per_din),       // Peripheral data input
180
    .per_en       (per_en),        // Peripheral enable (high active)
181
    .per_wen      (per_wen),       // Peripheral write enable (high active)
182
    .reset_n      (reset_n),       // Reset Pin (low active)
183
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
184
    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
185
);
186
 
187
 
188
//=============================================================================
189
// 3)  FRONTEND (<=> FETCH & DECODE)
190
//=============================================================================
191
 
192
omsp_frontend frontend_0 (
193
 
194
// OUTPUTs
195
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
196
    .decode_noirq (decode_noirq),  // Frontend decode instruction
197
    .e_state      (e_state),       // Execution state
198
    .exec_done    (exec_done),     // Execution completed
199
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
200
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
201
    .inst_alu     (inst_alu),      // ALU control signals
202
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
203
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
204
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
205
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: Reset interrupt
206
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
207
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
208
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
209
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
210
    .inst_type    (inst_type),     // Decoded Instruction type
211
    .irq_acc      (irq_acc),       // Interrupt request accepted
212
    .mab          (fe_mab),        // Frontend Memory address bus
213
    .mb_en        (fe_mb_en),      // Frontend Memory bus enable
214
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
215
    .pc           (pc),            // Program counter
216
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
217
 
218
// INPUTs
219
    .cpuoff       (cpuoff),        // Turns off the CPU
220
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
221
    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
222
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
223
    .gie          (gie),           // General interrupt enable
224
    .irq          (irq),           // Maskable interrupts
225
    .mclk         (mclk),          // Main system clock
226
    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
227
    .nmi_evt      (nmi_evt),       // Non-maskable interrupt event
228
    .pc_sw        (pc_sw),         // Program counter software value
229
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
230
    .puc          (puc),           // Main system reset
231
    .wdt_irq      (wdt_irq)        // Watchdog-timer interrupt
232
);
233
 
234
 
235
//=============================================================================
236
// 4)  EXECUTION UNIT
237
//=============================================================================
238
 
239
omsp_execution_unit execution_unit_0 (
240
 
241
// OUTPUTs
242
    .cpuoff       (cpuoff),        // Turns off the CPU
243
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
244
    .mab          (eu_mab),        // Memory address bus
245
    .mb_en        (eu_mb_en),      // Memory bus enable
246
    .mb_wr        (eu_mb_wr),      // Memory bus write transfer
247
    .mdb_out      (eu_mdb_out),    // Memory data bus output
248
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
249
    .pc_sw        (pc_sw),         // Program counter software value
250
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
251
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
252
 
253
// INPUTs
254
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
255
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
256
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
257
    .e_state      (e_state),       // Execution state
258
    .exec_done    (exec_done),     // Execution completed
259
    .gie          (gie),           // General interrupt enable
260
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
261
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
262
    .inst_alu     (inst_alu),      // ALU control signals
263
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
264
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
265
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
266
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: reset interrupt
267
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
268
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
269
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
270
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
271
    .inst_type    (inst_type),     // Decoded Instruction type
272
    .mclk         (mclk),          // Main system clock
273
    .mdb_in       (eu_mdb_in),     // Memory data bus input
274
    .pc           (pc),            // Program counter
275
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
276
    .puc          (puc)            // Main system reset
277
);
278
 
279
 
280
//=============================================================================
281
// 5)  MEMORY BACKBONE
282
//=============================================================================
283
 
284
omsp_mem_backbone mem_backbone_0 (
285
 
286
// OUTPUTs
287
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
288
    .dmem_addr    (dmem_addr),     // Data Memory address
289
    .dmem_cen     (dmem_cen),      // Data Memory chip enable (low active)
290
    .dmem_din     (dmem_din),      // Data Memory data input
291
    .dmem_wen     (dmem_wen),      // Data Memory write enable (low active)
292
    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
293
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
294
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
295
    .per_addr     (per_addr),      // Peripheral address
296
    .per_din      (per_din),       // Peripheral data input
297
    .per_wen      (per_wen),       // Peripheral write enable (high active)
298
    .per_en       (per_en),        // Peripheral enable (high active)
299
    .pmem_addr    (pmem_addr),     // Program Memory address
300
    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
301
    .pmem_din     (pmem_din),      // Program Memory data input (optional)
302
    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
303
 
304
// INPUTs
305
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
306
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
307
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
308
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
309
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
310
    .dmem_dout    (dmem_dout),     // Data Memory data output
311
    .eu_mab       (eu_mab[15:1]),  // Execution Unit Memory address bus
312
    .eu_mb_en     (eu_mb_en),      // Execution Unit Memory bus enable
313
    .eu_mb_wr     (eu_mb_wr),      // Execution Unit Memory bus write transfer
314
    .eu_mdb_out   (eu_mdb_out),    // Execution Unit Memory data bus output
315
    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
316
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
317
    .mclk         (mclk),          // Main system clock
318
    .per_dout     (per_dout_or),   // Peripheral data output
319
    .pmem_dout    (pmem_dout),     // Program Memory data output
320
    .puc          (puc)            // Main system reset
321
);
322
 
323
 
324
//=============================================================================
325
// 6)  SPECIAL FUNCTION REGISTERS
326
//=============================================================================
327
 
328
omsp_sfr sfr_0 (
329
 
330
// OUTPUTs
331
    .nmie         (nmie),          // Non-maskable interrupt enable
332
    .per_dout     (per_dout_sfr),  // Peripheral data output
333
    .wdt_irq      (wdt_irq),       // Watchdog-timer interrupt
334
    .wdt_reset    (wdt_reset),     // Watchdog-timer reset
335
    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
336
 
337
// INPUTs
338
    .mclk         (mclk),          // Main system clock
339
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
340
    .per_addr     (per_addr),      // Peripheral address
341
    .per_din      (per_din),       // Peripheral data input
342
    .per_en       (per_en),        // Peripheral enable (high active)
343
    .per_wen      (per_wen),       // Peripheral write enable (high active)
344
    .por          (por),           // Power-on reset
345
    .puc          (puc),           // Main system reset
346
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
347
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
348
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
349
    .wdttmsel     (wdttmsel)       // Watchdog-timer mode select
350
);
351
 
352
 
353
//=============================================================================
354
// 7)  WATCHDOG TIMER
355
//=============================================================================
356
 
357
omsp_watchdog watchdog_0 (
358
 
359
// OUTPUTs
360
    .nmi_evt      (nmi_evt),       // NMI Event
361
    .per_dout     (per_dout_wdog), // Peripheral data output
362
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
363
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
364
    .wdttmsel     (wdttmsel),      // Watchdog-timer mode select
365
 
366
// INPUTs
367
    .aclk_en      (aclk_en),       // ACLK enable
368
    .dbg_freeze   (dbg_freeze),    // Freeze Watchdog counter
369
    .mclk         (mclk),          // Main system clock
370
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
371
    .nmie         (nmie),          // Non-maskable interrupt enable
372
    .per_addr     (per_addr),      // Peripheral address
373
    .per_din      (per_din),       // Peripheral data input
374
    .per_en       (per_en),        // Peripheral enable (high active)
375
    .per_wen      (per_wen),       // Peripheral write enable (high active)
376
    .puc          (puc),           // Main system reset
377
    .smclk_en     (smclk_en),      // SMCLK enable
378
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
379
);
380
 
381
 
382
//=============================================================================
383
// 8)  HARDWARE MULTIPLIER
384
//=============================================================================
385
`ifdef MULTIPLIER
386
omsp_multiplier multiplier_0 (
387
 
388
// OUTPUTs
389
    .per_dout     (per_dout_mpy),  // Peripheral data output
390
 
391
// INPUTs
392
    .mclk         (mclk),          // Main system clock
393
    .per_addr     (per_addr),      // Peripheral address
394
    .per_din      (per_din),       // Peripheral data input
395
    .per_en       (per_en),        // Peripheral enable (high active)
396
    .per_wen      (per_wen),       // Peripheral write enable (high active)
397
    .puc          (puc)            // Main system reset
398
);
399
`else
400
assign per_dout_mpy = 16'h0000;
401
`endif
402
 
403
//=============================================================================
404
// 9)  PERIPHERALS' OUTPUT BUS
405
//=============================================================================
406
 
407
assign  per_dout_or  =  per_dout      |
408
                        per_dout_clk  |
409
                        per_dout_sfr  |
410
                        per_dout_wdog |
411
                        per_dout_mpy;
412
 
413
 
414
//=============================================================================
415
// 10)  DEBUG INTERFACE
416
//=============================================================================
417
 
418
`ifdef DBG_EN
419
omsp_dbg dbg_0 (
420
 
421
// OUTPUTs
422
    .dbg_freeze   (dbg_freeze),    // Freeze peripherals
423
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
424
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
425
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
426
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
427
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
428
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
429
    .dbg_reset    (dbg_reset),     // Reset CPU from debug interface
430
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
431
 
432
// INPUTs
433
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
434
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
435
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
436
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD
437
    .decode_noirq (decode_noirq),  // Frontend decode instruction
438
    .eu_mab       (eu_mab),        // Execution-Unit Memory address bus
439
    .eu_mb_en     (eu_mb_en),      // Execution-Unit Memory bus enable
440
    .eu_mb_wr     (eu_mb_wr),      // Execution-Unit Memory bus write transfer
441
    .eu_mdb_in    (eu_mdb_in),     // Memory data bus input
442
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
443
    .exec_done    (exec_done),     // Execution completed
444
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
445
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
446
    .mclk         (mclk),          // Main system clock
447
    .pc           (pc),            // Program counter
448
    .por          (por),           // Power on reset
449
    .puc          (puc)            // Main system reset
450
);
451
 
452
`else
453
assign dbg_freeze   =  1'b0;
454
assign dbg_halt_cmd =  1'b0;
455
assign dbg_mem_addr = 16'h0000;
456
assign dbg_mem_dout = 16'h0000;
457
assign dbg_mem_en   =  1'b0;
458
assign dbg_mem_wr   =  2'b00;
459
assign dbg_reg_wr   =  1'b0;
460
assign dbg_reset    =  1'b0;
461
assign dbg_uart_txd =  1'b0;
462
`endif
463
 
464
 
465
endmodule // openMSP430
466
 
467
`include "openMSP430_undefines.v"

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