URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Blame information for rev 84

Go to most recent revision | Details | Compare with Previous | View Log


//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: openMSP430_defines.v
// 
// *Module Description:
//                      openMSP430 Configuration file
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 74 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
//----------------------------------------------------------------------------
`include "openMSP430_undefines.v"
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
//
// Note: the sum of both program and data memories should not exceed 63.5 kB
//
 
// Program Memory Size:
//                     Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
`define PMEM_SIZE_4_KB
//`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
 
// Data Memory Size:
//                     Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
`define DMEM_SIZE_256_B
//`define DMEM_SIZE_128_B
 
 
// Include/Exclude Hardware Multiplier
//`define MULTIPLIER
 
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`define DBG_EN
 
// Debug interface selection
//             `define DBG_UART -> Enable UART (8N1) debug interface
//             `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
//
`define DBG_UART
//`define DBG_JTAG
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
//             `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//             `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//             `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//             `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//
`define  DBG_HWBRK_0
//`define  DBG_HWBRK_1
//`define  DBG_HWBRK_2
//`define  DBG_HWBRK_3
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
//
// PROGRAM & DATA MEMORY CONFIGURATION
//======================================
 
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     60416
`endif
`ifdef PMEM_SIZE_55_KB
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     56320
`endif
`ifdef PMEM_SIZE_54_KB
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     55296
`endif
`ifdef PMEM_SIZE_51_KB
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     52224
`endif
`ifdef PMEM_SIZE_48_KB
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     49152
`endif
`ifdef PMEM_SIZE_41_KB
  `define PMEM_AWIDTH      15
  `define PMEM_SIZE     41984
`endif
`ifdef PMEM_SIZE_32_KB
  `define PMEM_AWIDTH      14
  `define PMEM_SIZE     32768
`endif
`ifdef PMEM_SIZE_24_KB
  `define PMEM_AWIDTH      14
  `define PMEM_SIZE     24576
`endif
`ifdef PMEM_SIZE_16_KB
  `define PMEM_AWIDTH      13
  `define PMEM_SIZE     16384
`endif
`ifdef PMEM_SIZE_12_KB
  `define PMEM_AWIDTH      13
  `define PMEM_SIZE     12288
`endif
`ifdef PMEM_SIZE_8_KB
  `define PMEM_AWIDTH      12
  `define PMEM_SIZE      8192
`endif
`ifdef PMEM_SIZE_4_KB
  `define PMEM_AWIDTH      11
  `define PMEM_SIZE      4096
`endif
`ifdef PMEM_SIZE_2_KB
  `define PMEM_AWIDTH      10
  `define PMEM_SIZE      2048
`endif
`ifdef PMEM_SIZE_1_KB
  `define PMEM_AWIDTH       9
  `define PMEM_SIZE      1024
`endif
 
// Data Memory Size
`ifdef DMEM_SIZE_32_KB
  `define DMEM_AWIDTH       14
  `define DMEM_SIZE      32768
`endif
`ifdef DMEM_SIZE_24_KB
  `define DMEM_AWIDTH       14
  `define DMEM_SIZE      24576
`endif
`ifdef DMEM_SIZE_16_KB
  `define DMEM_AWIDTH       13
  `define DMEM_SIZE      16384
`endif
`ifdef DMEM_SIZE_10_KB
  `define DMEM_AWIDTH       13
  `define DMEM_SIZE      10240
`endif
`ifdef DMEM_SIZE_8_KB
  `define DMEM_AWIDTH       12
  `define DMEM_SIZE       8192
`endif
`ifdef DMEM_SIZE_5_KB
  `define DMEM_AWIDTH       12
  `define DMEM_SIZE       5120
`endif
`ifdef DMEM_SIZE_4_KB
  `define DMEM_AWIDTH       11
  `define DMEM_SIZE       4096
`endif
`ifdef DMEM_SIZE_2p5_KB
  `define DMEM_AWIDTH       11
  `define DMEM_SIZE       2560
`endif
`ifdef DMEM_SIZE_2_KB
  `define DMEM_AWIDTH       10
  `define DMEM_SIZE       2048
`endif
`ifdef DMEM_SIZE_1_KB
  `define DMEM_AWIDTH        9
  `define DMEM_SIZE       1024
`endif
`ifdef DMEM_SIZE_512_B
  `define DMEM_AWIDTH        8
  `define DMEM_SIZE        512
`endif
`ifdef DMEM_SIZE_256_B
  `define DMEM_AWIDTH        7
  `define DMEM_SIZE        256
`endif
`ifdef DMEM_SIZE_128_B
  `define DMEM_AWIDTH        6
  `define DMEM_SIZE        128
`endif
 
// Data Memory Base Adresses
`define DMEM_BASE  16'h0200
 
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB   `PMEM_AWIDTH-1
`define DMEM_MSB   `DMEM_AWIDTH-1
 
//
// STATES, REGISTER FIELDS, ...
//======================================
 
// Instructions type
`define INST_SO  0
`define INST_JMP 1
`define INST_TO  2
 
// Single-operand arithmetic
`define RRC    0
`define SWPB   1
`define RRA    2
`define SXT    3
`define PUSH   4
`define CALL   5
`define RETI   6
`define IRQ    7
 
// Conditional jump
`define JNE    0
`define JEQ    1
`define JNC    2
`define JC     3
`define JN     4
`define JGE    5
`define JL     6
`define JMP    7
 
// Two-operand arithmetic
`define MOV    0
`define ADD    1
`define ADDC   2
`define SUBC   3
`define SUB    4
`define CMP    5
`define DADD   6
`define BIT    7
`define BIC    8
`define BIS    9
`define XOR   10
`define AND   11
 
// Addressing modes
`define DIR      0
`define IDX      1
`define INDIR    2
`define INDIR_I  3
`define SYMB     4
`define IMM      5
`define ABS      6
`define CONST    7
 
// Execution state machine
`define E_IRQ_0    4'h0
`define E_IRQ_1    4'h1
`define E_IRQ_2    4'h2
`define E_IRQ_3    4'h3
`define E_IRQ_4    4'h4
`define E_SRC_AD   4'h5
`define E_SRC_RD   4'h6
`define E_SRC_WR   4'h7
`define E_DST_AD   4'h8
`define E_DST_RD   4'h9
`define E_DST_WR   4'hA
`define E_EXEC     4'hB
`define E_JUMP     4'hC
`define E_IDLE     4'hD
 
// ALU control signals
`define ALU_SRC_INV   0
`define ALU_INC       1
`define ALU_INC_C     2
`define ALU_ADD       3
`define ALU_AND       4
`define ALU_OR        5
`define ALU_XOR       6
`define ALU_DADD      7
`define ALU_STAT_7    8
`define ALU_STAT_F    9
`define ALU_SHIFT    10
`define EXEC_NO_WR   11
 
// Debug interface
`define DBG_UART_WR   18
`define DBG_UART_BW   17
`define DBG_UART_ADDR 16:11
 
// Debug interface CPU_CTL register
`define HALT        0
`define RUN         1
`define ISTEP       2
`define SW_BRK_EN   3
`define FRZ_BRK_EN  4
`define RST_BRK_EN  5
`define CPU_RST     6
 
// Debug interface CPU_STAT register
`define HALT_RUN    0
`define PUC_PND     1
`define SWBRK_PND   3
`define HWBRK0_PND  4
`define HWBRK1_PND  5
 
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE    1:0
`define BRK_EN      2
`define BRK_I_EN    3
`define BRK_RANGE   4
 
// Basic clock module: BCSCTL1 Control Register
`define DIVAx       5:4
 
// Basic clock module: BCSCTL2 Control Register
`define SELS        3
`define DIVSx       2:1
 
// Timer A: TACTL Control Register
`define TASSELx     9:8
`define TAIDx       7:6
`define TAMCx       5:4
`define TACLR       2
`define TAIE        1
`define TAIFG       0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx      15:14
`define TACCISx    13:12
`define TASCS      11
`define TASCCI     10
`define TACAP       8
`define TAOUTMODx   7:5
`define TACCIE      4
`define TACCI       3
`define TAOUT       2
`define TACOV       1
`define TACCIFG     0
 
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
 
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
 
// Debug UART interface data rate
//      In order to properly setup the UART debug interface, you
//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
//      the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD    9600
//`define DBG_UART_BAUD   19200
//`define DBG_UART_BAUD   38400
//`define DBG_UART_BAUD   57600
//`define DBG_UART_BAUD  115200
//`define DBG_UART_BAUD  230400
//`define DBG_UART_BAUD  460800
//`define DBG_UART_BAUD  576000
//`define DBG_UART_BAUD  921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ  20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
// Enable/Disable the hardware breakpoint RANGE mode
`define HWBRK_RANGE 1'b0
 
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
 
// Check configuration
`ifdef DBG_EN
 `ifdef DBG_UART
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
   `endif
 `else
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
   `else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
   `endif
 `endif
`endif
 
//
// MULTIPLIER CONFIGURATION
//======================================
 
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
 

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Blame information for rev 84

Line No.	Rev	Author	Line
1	80	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: openMSP430_defines.v`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 Configuration file`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev: 74 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $`
37			`//----------------------------------------------------------------------------`
38			`include "openMSP430_undefines.v"
39
40			`//----------------------------------------------------------------------------`
41			`// SYSTEM CONFIGURATION`
42			`//----------------------------------------------------------------------------`
43			`//`
44			`// Note: the sum of both program and data memories should not exceed 63.5 kB`
45			`//`
46
47			`// Program Memory Size:`
48			`// Uncomment the required memory size`
49			`//-------------------------------------------------------`
50			//`define PMEM_SIZE_59_KB
51			//`define PMEM_SIZE_55_KB
52			//`define PMEM_SIZE_54_KB
53			//`define PMEM_SIZE_51_KB
54			//`define PMEM_SIZE_48_KB
55			//`define PMEM_SIZE_41_KB
56			//`define PMEM_SIZE_32_KB
57			//`define PMEM_SIZE_24_KB
58			//`define PMEM_SIZE_16_KB
59			//`define PMEM_SIZE_12_KB
60			//`define PMEM_SIZE_8_KB
61			`define PMEM_SIZE_4_KB
62			//`define PMEM_SIZE_2_KB
63			//`define PMEM_SIZE_1_KB
64
65			`// Data Memory Size:`
66			`// Uncomment the required memory size`
67			`//-------------------------------------------------------`
68			//`define DMEM_SIZE_32_KB
69			//`define DMEM_SIZE_24_KB
70			//`define DMEM_SIZE_16_KB
71			//`define DMEM_SIZE_10_KB
72			//`define DMEM_SIZE_8_KB
73			//`define DMEM_SIZE_5_KB
74			//`define DMEM_SIZE_4_KB
75			//`define DMEM_SIZE_2p5_KB
76			//`define DMEM_SIZE_2_KB
77			//`define DMEM_SIZE_1_KB
78			//`define DMEM_SIZE_512_B
79			`define DMEM_SIZE_256_B
80			//`define DMEM_SIZE_128_B
81
82
83			`// Include/Exclude Hardware Multiplier`
84			//`define MULTIPLIER
85
86
87			`//----------------------------------------------------------------------------`
88			`// REMOTE DEBUGGING INTERFACE CONFIGURATION`
89			`//----------------------------------------------------------------------------`
90
91			`// Include Debug interface`
92			`define DBG_EN
93
94			`// Debug interface selection`
95			// `define DBG_UART -> Enable UART (8N1) debug interface
96			// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
97			`//`
98			`define DBG_UART
99			//`define DBG_JTAG
100
101			`// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)`
102			// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
103			// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
104			// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
105			// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
106			`//`
107			`define DBG_HWBRK_0
108			//`define DBG_HWBRK_1
109			//`define DBG_HWBRK_2
110			//`define DBG_HWBRK_3
111
112
113			`//==========================================================================//`
114			`//==========================================================================//`
115			`//==========================================================================//`
116			`//==========================================================================//`
117			`//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//`
118			`//==========================================================================//`
119			`//==========================================================================//`
120			`//==========================================================================//`
121			`//==========================================================================//`
122
123			`//`
124			`// PROGRAM & DATA MEMORY CONFIGURATION`
125			`//======================================`
126
127			`// Program Memory Size`
128			`ifdef PMEM_SIZE_59_KB
129			`define PMEM_AWIDTH 15
130			`define PMEM_SIZE 60416
131			`endif
132			`ifdef PMEM_SIZE_55_KB
133			`define PMEM_AWIDTH 15
134			`define PMEM_SIZE 56320
135			`endif
136			`ifdef PMEM_SIZE_54_KB
137			`define PMEM_AWIDTH 15
138			`define PMEM_SIZE 55296
139			`endif
140			`ifdef PMEM_SIZE_51_KB
141			`define PMEM_AWIDTH 15
142			`define PMEM_SIZE 52224
143			`endif
144			`ifdef PMEM_SIZE_48_KB
145			`define PMEM_AWIDTH 15
146			`define PMEM_SIZE 49152
147			`endif
148			`ifdef PMEM_SIZE_41_KB
149			`define PMEM_AWIDTH 15
150			`define PMEM_SIZE 41984
151			`endif
152			`ifdef PMEM_SIZE_32_KB
153			`define PMEM_AWIDTH 14
154			`define PMEM_SIZE 32768
155			`endif
156			`ifdef PMEM_SIZE_24_KB
157			`define PMEM_AWIDTH 14
158			`define PMEM_SIZE 24576
159			`endif
160			`ifdef PMEM_SIZE_16_KB
161			`define PMEM_AWIDTH 13
162			`define PMEM_SIZE 16384
163			`endif
164			`ifdef PMEM_SIZE_12_KB
165			`define PMEM_AWIDTH 13
166			`define PMEM_SIZE 12288
167			`endif
168			`ifdef PMEM_SIZE_8_KB
169			`define PMEM_AWIDTH 12
170			`define PMEM_SIZE 8192
171			`endif
172			`ifdef PMEM_SIZE_4_KB
173			`define PMEM_AWIDTH 11
174			`define PMEM_SIZE 4096
175			`endif
176			`ifdef PMEM_SIZE_2_KB
177			`define PMEM_AWIDTH 10
178			`define PMEM_SIZE 2048
179			`endif
180			`ifdef PMEM_SIZE_1_KB
181			`define PMEM_AWIDTH 9
182			`define PMEM_SIZE 1024
183			`endif
184
185			`// Data Memory Size`
186			`ifdef DMEM_SIZE_32_KB
187			`define DMEM_AWIDTH 14
188			`define DMEM_SIZE 32768
189			`endif
190			`ifdef DMEM_SIZE_24_KB
191			`define DMEM_AWIDTH 14
192			`define DMEM_SIZE 24576
193			`endif
194			`ifdef DMEM_SIZE_16_KB
195			`define DMEM_AWIDTH 13
196			`define DMEM_SIZE 16384
197			`endif
198			`ifdef DMEM_SIZE_10_KB
199			`define DMEM_AWIDTH 13
200			`define DMEM_SIZE 10240
201			`endif
202			`ifdef DMEM_SIZE_8_KB
203			`define DMEM_AWIDTH 12
204			`define DMEM_SIZE 8192
205			`endif
206			`ifdef DMEM_SIZE_5_KB
207			`define DMEM_AWIDTH 12
208			`define DMEM_SIZE 5120
209			`endif
210			`ifdef DMEM_SIZE_4_KB
211			`define DMEM_AWIDTH 11
212			`define DMEM_SIZE 4096
213			`endif
214			`ifdef DMEM_SIZE_2p5_KB
215			`define DMEM_AWIDTH 11
216			`define DMEM_SIZE 2560
217			`endif
218			`ifdef DMEM_SIZE_2_KB
219			`define DMEM_AWIDTH 10
220			`define DMEM_SIZE 2048
221			`endif
222			`ifdef DMEM_SIZE_1_KB
223			`define DMEM_AWIDTH 9
224			`define DMEM_SIZE 1024
225			`endif
226			`ifdef DMEM_SIZE_512_B
227			`define DMEM_AWIDTH 8
228			`define DMEM_SIZE 512
229			`endif
230			`ifdef DMEM_SIZE_256_B
231			`define DMEM_AWIDTH 7
232			`define DMEM_SIZE 256
233			`endif
234			`ifdef DMEM_SIZE_128_B
235			`define DMEM_AWIDTH 6
236			`define DMEM_SIZE 128
237			`endif
238
239			`// Data Memory Base Adresses`
240			`define DMEM_BASE 16'h0200
241
242			`// Program & Data Memory most significant address bit (for 16 bit words)`
243			`define PMEM_MSB `PMEM_AWIDTH-1
244			`define DMEM_MSB `DMEM_AWIDTH-1
245
246			`//`
247			`// STATES, REGISTER FIELDS, ...`
248			`//======================================`
249
250			`// Instructions type`
251			`define INST_SO 0
252			`define INST_JMP 1
253			`define INST_TO 2
254
255			`// Single-operand arithmetic`
256			`define RRC 0
257			`define SWPB 1
258			`define RRA 2
259			`define SXT 3
260			`define PUSH 4
261			`define CALL 5
262			`define RETI 6
263			`define IRQ 7
264
265			`// Conditional jump`
266			`define JNE 0
267			`define JEQ 1
268			`define JNC 2
269			`define JC 3
270			`define JN 4
271			`define JGE 5
272			`define JL 6
273			`define JMP 7
274
275			`// Two-operand arithmetic`
276			`define MOV 0
277			`define ADD 1
278			`define ADDC 2
279			`define SUBC 3
280			`define SUB 4
281			`define CMP 5
282			`define DADD 6
283			`define BIT 7
284			`define BIC 8
285			`define BIS 9
286			`define XOR 10
287			`define AND 11
288
289			`// Addressing modes`
290			`define DIR 0
291			`define IDX 1
292			`define INDIR 2
293			`define INDIR_I 3
294			`define SYMB 4
295			`define IMM 5
296			`define ABS 6
297			`define CONST 7
298
299			`// Execution state machine`
300			`define E_IRQ_0 4'h0
301			`define E_IRQ_1 4'h1
302			`define E_IRQ_2 4'h2
303			`define E_IRQ_3 4'h3
304			`define E_IRQ_4 4'h4
305			`define E_SRC_AD 4'h5
306			`define E_SRC_RD 4'h6
307			`define E_SRC_WR 4'h7
308			`define E_DST_AD 4'h8
309			`define E_DST_RD 4'h9
310			`define E_DST_WR 4'hA
311			`define E_EXEC 4'hB
312			`define E_JUMP 4'hC
313			`define E_IDLE 4'hD
314
315			`// ALU control signals`
316			`define ALU_SRC_INV 0
317			`define ALU_INC 1
318			`define ALU_INC_C 2
319			`define ALU_ADD 3
320			`define ALU_AND 4
321			`define ALU_OR 5
322			`define ALU_XOR 6
323			`define ALU_DADD 7
324			`define ALU_STAT_7 8
325			`define ALU_STAT_F 9
326			`define ALU_SHIFT 10
327			`define EXEC_NO_WR 11
328
329			`// Debug interface`
330			`define DBG_UART_WR 18
331			`define DBG_UART_BW 17
332			`define DBG_UART_ADDR 16:11
333
334			`// Debug interface CPU_CTL register`
335			`define HALT 0
336			`define RUN 1
337			`define ISTEP 2
338			`define SW_BRK_EN 3
339			`define FRZ_BRK_EN 4
340			`define RST_BRK_EN 5
341			`define CPU_RST 6
342
343			`// Debug interface CPU_STAT register`
344			`define HALT_RUN 0
345			`define PUC_PND 1
346			`define SWBRK_PND 3
347			`define HWBRK0_PND 4
348			`define HWBRK1_PND 5
349
350			`// Debug interface BRKx_CTL register`
351			`define BRK_MODE_RD 0
352			`define BRK_MODE_WR 1
353			`define BRK_MODE 1:0
354			`define BRK_EN 2
355			`define BRK_I_EN 3
356			`define BRK_RANGE 4
357
358			`// Basic clock module: BCSCTL1 Control Register`
359			`define DIVAx 5:4
360
361			`// Basic clock module: BCSCTL2 Control Register`
362			`define SELS 3
363			`define DIVSx 2:1
364
365			`// Timer A: TACTL Control Register`
366			`define TASSELx 9:8
367			`define TAIDx 7:6
368			`define TAMCx 5:4
369			`define TACLR 2
370			`define TAIE 1
371			`define TAIFG 0
372
373			`// Timer A: TACCTLx Capture/Compare Control Register`
374			`define TACMx 15:14
375			`define TACCISx 13:12
376			`define TASCS 11
377			`define TASCCI 10
378			`define TACAP 8
379			`define TAOUTMODx 7:5
380			`define TACCIE 4
381			`define TACCI 3
382			`define TAOUT 2
383			`define TACOV 1
384			`define TACCIFG 0
385
386
387			`//`
388			`// DEBUG INTERFACE EXTRA CONFIGURATION`
389			`//======================================`
390
391			`// Debug interface: Software breakpoint opcode`
392			`define DBG_SWBRK_OP 16'h4343
393
394			`// Debug UART interface auto data synchronization`
395			`// If the following define is commented out, then`
396			`// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly`
397			`// defined.`
398			`define DBG_UART_AUTO_SYNC
399
400			`// Debug UART interface data rate`
401			`// In order to properly setup the UART debug interface, you`
402			`// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and`
403			`// the chosen BAUD rate from the UART interface.`
404			`//`
405			//`define DBG_UART_BAUD 9600
406			//`define DBG_UART_BAUD 19200
407			//`define DBG_UART_BAUD 38400
408			//`define DBG_UART_BAUD 57600
409			//`define DBG_UART_BAUD 115200
410			//`define DBG_UART_BAUD 230400
411			//`define DBG_UART_BAUD 460800
412			//`define DBG_UART_BAUD 576000
413			//`define DBG_UART_BAUD 921600
414			`define DBG_UART_BAUD 2000000
415			`define DBG_DCO_FREQ 20000000
416			`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
417
418			`// Enable/Disable the hardware breakpoint RANGE mode`
419			`define HWBRK_RANGE 1'b0
420
421			`// Counter width for the debug interface UART`
422			`define DBG_UART_XFER_CNT_W 16
423
424			`// Check configuration`
425			`ifdef DBG_EN
426			`ifdef DBG_UART
427			`ifdef DBG_JTAG
428			`CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED`
429			`endif
430			`else
431			`ifdef DBG_JTAG
432			`CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED`
433			`else
434			`CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED`
435			`endif
436			`endif
437			`endif
438
439			`//`
440			`// MULTIPLIER CONFIGURATION`
441			`//======================================`
442
443			`// If uncommented, the following define selects`
444			`// the 16x16 multiplier (1 cycle) instead of the`
445			`// default 16x8 multplier (2 cycles)`
446			//`define MPY_16x16
447