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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Blame information for rev 107

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Line No. Rev Author Line
1 80 olivier.gi 
//----------------------------------------------------------------------------
2 
// Copyright (C) 2001 Authors
3 
//
4 
// This source file may be used and distributed without restriction provided
5 
// that this copyright statement is not removed from the file and that any
6 
// derivative work contains the original copyright notice and the associated
7 
// disclaimer.
8 
//
9 
// This source file is free software; you can redistribute it and/or modify
10 
// it under the terms of the GNU Lesser General Public License as published
11 
// by the Free Software Foundation; either version 2.1 of the License, or
12 
// (at your option) any later version.
13 
//
14 
// This source is distributed in the hope that it will be useful, but WITHOUT
15 
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17 
// License for more details.
18 
//
19 
// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
23 
//----------------------------------------------------------------------------
24 
//
25 
// *File Name: openMSP430_undefines.v
26 
//
27 
// *Module Description:
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//                      openMSP430 Verilog `undef file
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//
30 
// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
33 
//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
37 
//----------------------------------------------------------------------------
38 
 
39 
//----------------------------------------------------------------------------
40 
// SYSTEM CONFIGURATION
41 
//----------------------------------------------------------------------------
42 
 
43 
// Program Memory Size:
44 
`ifdef PMEM_AWIDTH
45 
`undef PMEM_AWIDTH
46 
`endif
47 
 
48 
// Data Memory Size:
49 
`ifdef DMEM_AWIDTH
50 
`undef DMEM_AWIDTH
51 
`endif
52 
 
53 
// Include/Exclude Hardware Multiplier
54 
`ifdef MULTIPLIER
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`undef MULTIPLIER
56 
`endif
57 
 
58 
//----------------------------------------------------------------------------
59 
// REMOTE DEBUGGING INTERFACE CONFIGURATION
60 
//----------------------------------------------------------------------------
61 
 
62 
// Include Debug interface
63 
`ifdef DBG_EN
64 
`undef DBG_EN
65 
`endif
66 
 
67 
// Debug interface selection
68 
`ifdef DBG_UART
69 
`undef DBG_UART
70 
`endif
71 
`ifdef DBG_JTAG
72 
`undef DBG_JTAG
73 
`endif
74 
 
75 
// Number of hardware breakpoints
76 
`ifdef DBG_HWBRK_0
77 
`undef DBG_HWBRK_0
78 
`endif
79 
`ifdef DBG_HWBRK_1
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`undef DBG_HWBRK_1
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`endif
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`ifdef DBG_HWBRK_2
83 
`undef DBG_HWBRK_2
84 
`endif
85 
`ifdef DBG_HWBRK_3
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`undef DBG_HWBRK_3
87 
`endif
88 
 
89 107 olivier.gi 
// Let the CPU break after a PUC occurrence by default
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`ifdef DBG_RST_BRK_EN
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`undef DBG_RST_BRK_EN
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`endif
93 80 olivier.gi 
 
94 107 olivier.gi 
 
95 80 olivier.gi 
//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
104 
 
105 
// Program and Data Memory sizes
106 
`ifdef PMEM_SIZE_59_KB
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`undef PMEM_SIZE_59_KB
108 
`endif
109 
`ifdef PMEM_SIZE_55_KB
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`undef PMEM_SIZE_55_KB
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`endif
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`ifdef PMEM_SIZE_54_KB
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`undef PMEM_SIZE_54_KB
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`endif
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`ifdef PMEM_SIZE_51_KB
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`undef PMEM_SIZE_51_KB
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`endif
118 
`ifdef PMEM_SIZE_48_KB
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`undef PMEM_SIZE_48_KB
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`endif
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`ifdef PMEM_SIZE_41_KB
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`undef PMEM_SIZE_41_KB
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`endif
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`ifdef PMEM_SIZE_32_KB
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`undef PMEM_SIZE_32_KB
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`endif
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`ifdef PMEM_SIZE_24_KB
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`undef PMEM_SIZE_24_KB
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`endif
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`ifdef PMEM_SIZE_16_KB
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`undef PMEM_SIZE_16_KB
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`endif
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`ifdef PMEM_SIZE_12_KB
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`undef PMEM_SIZE_12_KB
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`endif
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`ifdef PMEM_SIZE_8_KB
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`undef PMEM_SIZE_8_KB
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`endif
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`ifdef PMEM_SIZE_4_KB
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`undef PMEM_SIZE_4_KB
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`endif
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`ifdef PMEM_SIZE_2_KB
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`undef PMEM_SIZE_2_KB
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`endif
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`ifdef PMEM_SIZE_1_KB
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`undef PMEM_SIZE_1_KB
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`endif
148 
`ifdef DMEM_SIZE_32_KB
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`undef DMEM_SIZE_32_KB
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`endif
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`ifdef DMEM_SIZE_24_KB
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`undef DMEM_SIZE_24_KB
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`endif
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`ifdef DMEM_SIZE_16_KB
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`undef DMEM_SIZE_16_KB
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`endif
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`ifdef DMEM_SIZE_10_KB
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`undef DMEM_SIZE_10_KB
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`endif
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`ifdef DMEM_SIZE_8_KB
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`undef DMEM_SIZE_8_KB
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`endif
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`ifdef DMEM_SIZE_5_KB
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`undef DMEM_SIZE_5_KB
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`endif
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`ifdef DMEM_SIZE_4_KB
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`undef DMEM_SIZE_4_KB
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`endif
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`ifdef DMEM_SIZE_2p5_KB
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`undef DMEM_SIZE_2p5_KB
171 
`endif
172 
`ifdef DMEM_SIZE_2_KB
173 
`undef DMEM_SIZE_2_KB
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`endif
175 
`ifdef DMEM_SIZE_1_KB
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`undef DMEM_SIZE_1_KB
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`endif
178 
`ifdef DMEM_SIZE_512_B
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`undef DMEM_SIZE_512_B
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`endif
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`ifdef DMEM_SIZE_256_B
182 
`undef DMEM_SIZE_256_B
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`endif
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`ifdef DMEM_SIZE_128_B
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`undef DMEM_SIZE_128_B
186 
`endif
187 
`ifdef PMEM_SIZE
188 
`undef PMEM_SIZE
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`endif
190 
`ifdef PMEM_AWIDTH
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`undef PMEM_AWIDTH
192 
`endif
193 
`ifdef DMEM_SIZE
194 
`undef DMEM_SIZE
195 
`endif
196 
`ifdef DMEM_AWIDTH
197 
`undef DMEM_AWIDTH
198 
`endif
199 
 
200 
// Data Memory Base Adresses
201 
`ifdef DMEM_BASE
202 
`undef DMEM_BASE
203 
`endif
204 
 
205 
// Program & Data Memory most significant address bit (for 16 bit words)
206 
`ifdef PMEM_MSB
207 
`undef PMEM_MSB
208 
`endif
209 
`ifdef DMEM_MSB
210 
`undef DMEM_MSB
211 
`endif
212 
 
213 
 
214 
// Instructions type
215 
`ifdef INST_SO
216 
`undef INST_SO
217 
`endif
218 
`ifdef INST_JMP
219 
`undef INST_JMP
220 
`endif
221 
`ifdef INST_TO
222 
`undef INST_TO
223 
`endif
224 
 
225 
// Single-operand arithmetic
226 
`ifdef RRC
227 
`undef RRC
228 
`endif
229 
`ifdef SWPB
230 
`undef SWPB
231 
`endif
232 
`ifdef RRA
233 
`undef RRA
234 
`endif
235 
`ifdef SXT
236 
`undef SXT
237 
`endif
238 
`ifdef PUSH
239 
`undef PUSH
240 
`endif
241 
`ifdef CALL
242 
`undef CALL
243 
`endif
244 
`ifdef RETI
245 
`undef RETI
246 
`endif
247 
`ifdef IRQ
248 
`undef IRQ
249 
`endif
250 
 
251 
// Conditional jump
252 
`ifdef JNE
253 
`undef JNE
254 
`endif
255 
`ifdef JEQ
256 
`undef JEQ
257 
`endif
258 
`ifdef JNC
259 
`undef JNC
260 
`endif
261 
`ifdef JC
262 
`undef JC
263 
`endif
264 
`ifdef JN
265 
`undef JN
266 
`endif
267 
`ifdef JGE
268 
`undef JGE
269 
`endif
270 
`ifdef JL
271 
`undef JL
272 
`endif
273 
`ifdef JMP
274 
`undef JMP
275 
`endif
276 
 
277 
// Two-operand arithmetic
278 
`ifdef MOV
279 
`undef MOV
280 
`endif
281 
`ifdef ADD
282 
`undef ADD
283 
`endif
284 
`ifdef ADDC
285 
`undef ADDC
286 
`endif
287 
`ifdef SUBC
288 
`undef SUBC
289 
`endif
290 
`ifdef SUB
291 
`undef SUB
292 
`endif
293 
`ifdef CMP
294 
`undef CMP
295 
`endif
296 
`ifdef DADD
297 
`undef DADD
298 
`endif
299 
`ifdef BIT
300 
`undef BIT
301 
`endif
302 
`ifdef BIC
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`undef BIC
304 
`endif
305 
`ifdef BIS
306 
`undef BIS
307 
`endif
308 
`ifdef XOR
309 
`undef XOR
310 
`endif
311 
`ifdef AND
312 
`undef AND
313 
`endif
314 
 
315 
// Addressing modes
316 
`ifdef DIR
317 
`undef DIR
318 
`endif
319 
`ifdef IDX
320 
`undef IDX
321 
`endif
322 
`ifdef INDIR
323 
`undef INDIR
324 
`endif
325 
`ifdef INDIR_I
326 
`undef INDIR_I
327 
`endif
328 
`ifdef SYMB
329 
`undef SYMB
330 
`endif
331 
`ifdef IMM
332 
`undef IMM
333 
`endif
334 
`ifdef ABS
335 
`undef ABS
336 
`endif
337 
`ifdef CONST
338 
`undef CONST
339 
`endif
340 
 
341 
// Execution state machine
342 
`ifdef E_IRQ_0
343 
`undef E_IRQ_0
344 
`endif
345 
`ifdef E_IRQ_1
346 
`undef E_IRQ_1
347 
`endif
348 
`ifdef E_IRQ_2
349 
`undef E_IRQ_2
350 
`endif
351 
`ifdef E_IRQ_3
352 
`undef E_IRQ_3
353 
`endif
354 
`ifdef E_IRQ_4
355 
`undef E_IRQ_4
356 
`endif
357 
`ifdef E_SRC_AD
358 
`undef E_SRC_AD
359 
`endif
360 
`ifdef E_SRC_RD
361 
`undef E_SRC_RD
362 
`endif
363 
`ifdef E_SRC_WR
364 
`undef E_SRC_WR
365 
`endif
366 
`ifdef E_DST_AD
367 
`undef E_DST_AD
368 
`endif
369 
`ifdef E_DST_RD
370 
`undef E_DST_RD
371 
`endif
372 
`ifdef E_DST_WR
373 
`undef E_DST_WR
374 
`endif
375 
`ifdef E_EXEC
376 
`undef E_EXEC
377 
`endif
378 
`ifdef E_JUMP
379 
`undef E_JUMP
380 
`endif
381 
`ifdef E_IDLE
382 
`undef E_IDLE
383 
`endif
384 
 
385 
// ALU control signals
386 
`ifdef ALU_SRC_INV
387 
`undef ALU_SRC_INV
388 
`endif
389 
`ifdef ALU_INC
390 
`undef ALU_INC
391 
`endif
392 
`ifdef ALU_INC_C
393 
`undef ALU_INC_C
394 
`endif
395 
`ifdef ALU_ADD
396 
`undef ALU_ADD
397 
`endif
398 
`ifdef ALU_AND
399 
`undef ALU_AND
400 
`endif
401 
`ifdef ALU_OR
402 
`undef ALU_OR
403 
`endif
404 
`ifdef ALU_XOR
405 
`undef ALU_XOR
406 
`endif
407 
`ifdef ALU_DADD
408 
`undef ALU_DADD
409 
`endif
410 
`ifdef ALU_STAT_7
411 
`undef ALU_STAT_7
412 
`endif
413 
`ifdef ALU_STAT_F
414 
`undef ALU_STAT_F
415 
`endif
416 
`ifdef ALU_SHIFT
417 
`undef ALU_SHIFT
418 
`endif
419 
`ifdef EXEC_NO_WR
420 
`undef EXEC_NO_WR
421 
`endif
422 
 
423 
// Debug interface
424 
`ifdef DBG_UART_WR
425 
`undef DBG_UART_WR
426 
`endif
427 
`ifdef DBG_UART_BW
428 
`undef DBG_UART_BW
429 
`endif
430 
`ifdef DBG_UART_ADDR
431 
`undef DBG_UART_ADDR
432 
`endif
433 
 
434 
// Debug interface CPU_CTL register
435 
`ifdef HALT
436 
`undef HALT
437 
`endif
438 
`ifdef RUN
439 
`undef RUN
440 
`endif
441 
`ifdef ISTEP
442 
`undef ISTEP
443 
`endif
444 
`ifdef SW_BRK_EN
445 
`undef SW_BRK_EN
446 
`endif
447 
`ifdef FRZ_BRK_EN
448 
`undef FRZ_BRK_EN
449 
`endif
450 
`ifdef RST_BRK_EN
451 
`undef RST_BRK_EN
452 
`endif
453 
`ifdef CPU_RST
454 
`undef CPU_RST
455 
`endif
456 
 
457 
// Debug interface CPU_STAT register
458 
`ifdef HALT_RUN
459 
`undef HALT_RUN
460 
`endif
461 
`ifdef PUC_PND
462 
`undef PUC_PND
463 
`endif
464 
`ifdef SWBRK_PND
465 
`undef SWBRK_PND
466 
`endif
467 
`ifdef HWBRK0_PND
468 
`undef HWBRK0_PND
469 
`endif
470 
`ifdef HWBRK1_PND
471 
`undef HWBRK1_PND
472 
`endif
473 
 
474 
// Debug interface BRKx_CTL register
475 
`ifdef BRK_MODE_RD
476 
`undef BRK_MODE_RD
477 
`endif
478 
`ifdef BRK_MODE_WR
479 
`undef BRK_MODE_WR
480 
`endif
481 
`ifdef BRK_MODE
482 
`undef BRK_MODE
483 
`endif
484 
`ifdef BRK_EN
485 
`undef BRK_EN
486 
`endif
487 
`ifdef BRK_I_EN
488 
`undef BRK_I_EN
489 
`endif
490 
`ifdef BRK_RANGE
491 
`undef BRK_RANGE
492 
`endif
493 
 
494 
// Basic clock module: BCSCTL1 Control Register
495 
`ifdef DIVAx
496 
`undef DIVAx
497 
`endif
498 
 
499 
// Basic clock module: BCSCTL2 Control Register
500 
`ifdef SELS
501 
`undef SELS
502 
`endif
503 
`ifdef DIVSx
504 
`undef DIVSx
505 
`endif
506 
 
507 
 
508 
//
509 
// DEBUG INTERFACE EXTRA CONFIGURATION
510 
//======================================
511 
 
512 
// Debug interface: Software breakpoint opcode
513 
`ifdef DBG_SWBRK_OP
514 
`undef DBG_SWBRK_OP
515 
`endif
516 
 
517 
// Debug UART interface auto data synchronization
518 
`ifdef DBG_UART_AUTO_SYNC
519 
`undef DBG_UART_AUTO_SYNC
520 
`endif
521 
 
522 
// Debug UART interface data rate
523 
`ifdef DBG_UART_BAUD
524 
`undef DBG_UART_BAUD
525 
`endif
526 
`ifdef DBG_DCO_FREQ
527 
`undef DBG_DCO_FREQ
528 
`endif
529 
`ifdef DBG_UART_CNT
530 
`undef DBG_UART_CNT
531 
`endif
532 
 
533 
// Enable/Disable the hardware breakpoint RANGE mode
534 
`ifdef HWBRK_RANGE
535 
`undef HWBRK_RANGE
536 
`endif
537 
 
538 
// Counter width for the debug interface UART
539 
`ifdef DBG_UART_XFER_CNT_W
540 
`undef DBG_UART_XFER_CNT_W
541 
`endif
542 
 
543 
//
544 
// MULTIPLIER CONFIGURATION
545 
//======================================
546 
 
547 
`ifdef MPY_16x16
548 
`undef MPY_16x16
549 
`endif

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