OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA_undefines.v] - Blame information for rev 127

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 107 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
// 
25
// *File Name: omsp_timerA_undefines.v
26
// 
27
// *Module Description:
28
//                      omsp_timerA Verilog `undef file
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34
// $Rev: 23 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
37
//----------------------------------------------------------------------------
38
 
39
//----------------------------------------------------------------------------
40
// SYSTEM CONFIGURATION
41
//----------------------------------------------------------------------------
42
 
43
 
44
 
45
//==========================================================================//
46
//==========================================================================//
47
//==========================================================================//
48
//==========================================================================//
49
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
50
//==========================================================================//
51
//==========================================================================//
52
//==========================================================================//
53
//==========================================================================//
54
 
55
// Timer A: TACTL Control Register
56
`ifdef TASSELx
57
`undef TASSELx
58
`endif
59
`ifdef TAIDx
60
`undef TAIDx
61
`endif
62
`ifdef TAMCx
63
`undef TAMCx
64
`endif
65
`ifdef TACLR
66
`undef TACLR
67
`endif
68
`ifdef TAIE
69
`undef TAIE
70
`endif
71
`ifdef TAIFG
72
`undef TAIFG
73
`endif
74
 
75
// Timer A: TACCTLx Capture/Compare Control Register
76
`ifdef TACMx
77
`undef TACMx
78
`endif
79
`ifdef TACCISx
80
`undef TACCISx
81
`endif
82
`ifdef TASCS
83
`undef TASCS
84
`endif
85
`ifdef TASCCI
86
`undef TASCCI
87
`endif
88
`ifdef TACAP
89
`undef TACAP
90
`endif
91
`ifdef TAOUTMODx
92
`undef TAOUTMODx
93
`endif
94
`ifdef TACCIE
95
`undef TACCIE
96
`endif
97
`ifdef TACCI
98
`undef TACCI
99
`endif
100
`ifdef TAOUT
101
`undef TAOUT
102
`endif
103
`ifdef TACOV
104
`undef TACOV
105
`endif
106
`ifdef TACCIFG
107
`undef TACCIFG
108
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.