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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [template_periph_8b.v] - Blame information for rev 127

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//----------------------------------------------------------------------------
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// Copyright (C) 2009 Authors
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: template_periph_8b.v
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// 
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// *Module Description:
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//                       8 bit peripheral template.
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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module  template_periph_8b (
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// OUTPUTs
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    per_dout,                       // Peripheral data output
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// INPUTs
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    mclk,                           // Main system clock
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_en,                         // Peripheral enable (high active)
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    per_we,                         // Peripheral write enable (high active)
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    puc_rst                         // Main system reset
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);
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// OUTPUTs
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//=========
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output      [15:0] per_dout;        // Peripheral data output
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// INPUTs
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//=========
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input              mclk;            // Main system clock
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input       [13:0] per_addr;        // Peripheral address
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input       [15:0] per_din;         // Peripheral data input
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input              per_en;          // Peripheral enable (high active)
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input        [1:0] per_we;          // Peripheral write enable (high active)
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input              puc_rst;         // Main system reset
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//=============================================================================
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// 1)  PARAMETER DECLARATION
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//=============================================================================
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// Register base address (must be aligned to decoder bit width)
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parameter       [14:0] BASE_ADDR   = 15'h0090;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter              DEC_WD      =  2;
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// Register addresses offset
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parameter [DEC_WD-1:0] CNTRL1      =  'h0,
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                       CNTRL2      =  'h1,
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                       CNTRL3      =  'h2,
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                       CNTRL4      =  'h3;
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// Register one-hot decoder utilities
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parameter              DEC_SZ      =  2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] CNTRL1_D  = (BASE_REG << CNTRL1),
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                       CNTRL2_D  = (BASE_REG << CNTRL2),
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                       CNTRL3_D  = (BASE_REG << CNTRL3),
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                       CNTRL4_D  = (BASE_REG << CNTRL4);
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//============================================================================
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// 2)  REGISTER DECODER
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//============================================================================
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// Local register selection
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wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};
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// Register address decode
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wire [DEC_SZ-1:0] reg_dec      = (CNTRL1_D  &  {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) |
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                                 (CNTRL2_D  &  {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) |
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                                 (CNTRL3_D  &  {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) |
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                                 (CNTRL4_D  &  {DEC_SZ{(reg_addr==(CNTRL4 >>1))}});
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// Read/Write probes
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wire              reg_lo_write =  per_we[0] & reg_sel;
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wire              reg_hi_write =  per_we[1] & reg_sel;
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wire              reg_read     = ~|per_we   & reg_sel;
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// Read/Write vectors
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wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
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wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
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wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// CNTRL1 Register
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//-----------------
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reg  [7:0] cntrl1;
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wire       cntrl1_wr  = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1];
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wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8]     : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)        cntrl1 <=  8'h00;
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  else if (cntrl1_wr) cntrl1 <=  cntrl1_nxt;
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// CNTRL2 Register
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//-----------------
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reg  [7:0] cntrl2;
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wire       cntrl2_wr  = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2];
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wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8]     : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)        cntrl2 <=  8'h00;
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  else if (cntrl2_wr) cntrl2 <=  cntrl2_nxt;
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// CNTRL3 Register
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//-----------------
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reg  [7:0] cntrl3;
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wire       cntrl3_wr  = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3];
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wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8]     : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)        cntrl3 <=  8'h00;
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  else if (cntrl3_wr) cntrl3 <=  cntrl3_nxt;
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// CNTRL4 Register
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//-----------------
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reg  [7:0] cntrl4;
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wire       cntrl4_wr  = CNTRL4[0] ? reg_hi_wr[CNTRL4] : reg_lo_wr[CNTRL4];
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wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8]     : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)        cntrl4 <=  8'h00;
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  else if (cntrl4_wr) cntrl4 <=  cntrl4_nxt;
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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// Data output mux
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wire [15:0] cntrl1_rd   = {8'h00, (cntrl1  & {8{reg_rd[CNTRL1]}})}  << (8 & {4{CNTRL1[0]}});
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wire [15:0] cntrl2_rd   = {8'h00, (cntrl2  & {8{reg_rd[CNTRL2]}})}  << (8 & {4{CNTRL2[0]}});
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wire [15:0] cntrl3_rd   = {8'h00, (cntrl3  & {8{reg_rd[CNTRL3]}})}  << (8 & {4{CNTRL3[0]}});
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wire [15:0] cntrl4_rd   = {8'h00, (cntrl4  & {8{reg_rd[CNTRL4]}})}  << (8 & {4{CNTRL4[0]}});
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wire [15:0] per_dout  =  cntrl1_rd  |
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                         cntrl2_rd  |
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                         cntrl3_rd  |
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                         cntrl4_rd;
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endmodule // template_periph_8b

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