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olivier.gi |
`timescale 1 ns/100 ps
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// Version: 9.0 SP1 9.0.2.9
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module pmem_2kB(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
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input [7:0] WD;
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output [7:0] RD;
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input WEN, REN;
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input [10:0] WADDR, RADDR;
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input RWCLK;
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input RESET;
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wire VCC, GND;
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VCC VCC_1_net(.Y(VCC));
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GND GND_1_net(.Y(GND));
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81 |
olivier.gi |
RAM4K9 pmem_2kB_R0C0(.ADDRA11(GND), .ADDRA10(WADDR[10]),
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80 |
olivier.gi |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
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.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
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.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
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.ADDRA0(WADDR[0]), .ADDRB11(GND), .ADDRB10(RADDR[10]),
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.ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]),
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.ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]),
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.ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]),
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.ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND),
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.DINA5(GND), .DINA4(GND), .DINA3(GND), .DINA2(GND),
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.DINA1(WD[1]), .DINA0(WD[0]), .DINB8(GND), .DINB7(GND),
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.DINB6(GND), .DINB5(GND), .DINB4(GND), .DINB3(GND),
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.DINB2(GND), .DINB1(GND), .DINB0(GND), .WIDTHA0(VCC),
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.WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(GND), .PIPEA(GND),
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.PIPEB(GND), .WMODEA(GND), .WMODEB(GND), .BLKA(WEN),
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.BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(
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RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(),
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.DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(),
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.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
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.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[1]), .DOUTB0(
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RD[0]));
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81 |
olivier.gi |
RAM4K9 pmem_2kB_R0C1(.ADDRA11(GND), .ADDRA10(WADDR[10]),
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80 |
olivier.gi |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
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.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
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.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
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.ADDRA0(WADDR[0]), .ADDRB11(GND), .ADDRB10(RADDR[10]),
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.ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]),
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.ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]),
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.ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]),
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.ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND),
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.DINA5(GND), .DINA4(GND), .DINA3(GND), .DINA2(GND),
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.DINA1(WD[3]), .DINA0(WD[2]), .DINB8(GND), .DINB7(GND),
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.DINB6(GND), .DINB5(GND), .DINB4(GND), .DINB3(GND),
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.DINB2(GND), .DINB1(GND), .DINB0(GND), .WIDTHA0(VCC),
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.WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(GND), .PIPEA(GND),
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.PIPEB(GND), .WMODEA(GND), .WMODEB(GND), .BLKA(WEN),
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.BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(
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RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(),
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.DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(),
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.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
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.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[3]), .DOUTB0(
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RD[2]));
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81 |
olivier.gi |
RAM4K9 pmem_2kB_R0C3(.ADDRA11(GND), .ADDRA10(WADDR[10]),
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80 |
olivier.gi |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
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.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
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.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
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.ADDRA0(WADDR[0]), .ADDRB11(GND), .ADDRB10(RADDR[10]),
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.ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]),
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.ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]),
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.ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]),
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.ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND),
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.DINA5(GND), .DINA4(GND), .DINA3(GND), .DINA2(GND),
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.DINA1(WD[7]), .DINA0(WD[6]), .DINB8(GND), .DINB7(GND),
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.DINB6(GND), .DINB5(GND), .DINB4(GND), .DINB3(GND),
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.DINB2(GND), .DINB1(GND), .DINB0(GND), .WIDTHA0(VCC),
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.WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(GND), .PIPEA(GND),
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.PIPEB(GND), .WMODEA(GND), .WMODEB(GND), .BLKA(WEN),
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.BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(
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RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(),
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.DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(),
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.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
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.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[7]), .DOUTB0(
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RD[6]));
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81 |
olivier.gi |
RAM4K9 pmem_2kB_R0C2(.ADDRA11(GND), .ADDRA10(WADDR[10]),
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80 |
olivier.gi |
.ADDRA9(WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]),
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.ADDRA6(WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]),
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.ADDRA3(WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]),
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.ADDRA0(WADDR[0]), .ADDRB11(GND), .ADDRB10(RADDR[10]),
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.ADDRB9(RADDR[9]), .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]),
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.ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]),
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.ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]),
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.ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND),
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.DINA5(GND), .DINA4(GND), .DINA3(GND), .DINA2(GND),
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.DINA1(WD[5]), .DINA0(WD[4]), .DINB8(GND), .DINB7(GND),
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.DINB6(GND), .DINB5(GND), .DINB4(GND), .DINB3(GND),
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.DINB2(GND), .DINB1(GND), .DINB0(GND), .WIDTHA0(VCC),
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.WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(GND), .PIPEA(GND),
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.PIPEB(GND), .WMODEA(GND), .WMODEB(GND), .BLKA(WEN),
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.BLKB(REN), .WENA(GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(
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RWCLK), .RESET(RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(),
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.DOUTA5(), .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(),
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.DOUTA0(), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(),
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.DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(RD[5]), .DOUTB0(
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RD[4]));
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endmodule
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