OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [bin/] [msp430sim] - Blame information for rev 151

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 80 olivier.gi
#!/bin/bash
2
#------------------------------------------------------------------------------
3
# Copyright (C) 2001 Authors
4
#
5
# This source file may be used and distributed without restriction provided
6
# that this copyright statement is not removed from the file and that any
7
# derivative work contains the original copyright notice and the associated
8
# disclaimer.
9
#
10
# This source file is free software; you can redistribute it and/or modify
11
# it under the terms of the GNU Lesser General Public License as published
12
# by the Free Software Foundation; either version 2.1 of the License, or
13
# (at your option) any later version.
14
#
15
# This source is distributed in the hope that it will be useful, but WITHOUT
16
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
18
# License for more details.
19
#
20
# You should have received a copy of the GNU Lesser General Public License
21
# along with this source; if not, write to the Free Software Foundation,
22
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
23
#
24
#------------------------------------------------------------------------------
25
#
26
# File Name: msp430sim
27
#
28
# Author(s):
29
#             - Olivier Girard,    olgirard@gmail.com
30
#
31
#------------------------------------------------------------------------------
32
# $Rev: 73 $
33
# $LastChangedBy: olivier.girard $
34
# $LastChangedDate: 2010-08-03 21:26:39 +0200 (Tue, 03 Aug 2010) $
35
#------------------------------------------------------------------------------
36
 
37
###############################################################################
38
#                            Parameter Check                                  #
39
###############################################################################
40
EXPECTED_ARGS=1
41
if [ $# -ne $EXPECTED_ARGS ]; then
42
  echo "ERROR    : wrong number of arguments"
43
  echo "USAGE    : msp430sim "
44
  echo "Example  : msp430sim leds"
45 98 olivier.gi
  echo ""
46 136 olivier.gi
  echo "In order to switch the verilog simulator, the OMSP_SIMULATOR environment"
47 98 olivier.gi
  echo "variable can be set to the following values:"
48
  echo ""
49
  echo "                  - iverilog  : Icarus Verilog  (default)"
50
  echo "                  - cver      : CVer"
51
  echo "                  - verilog   : Verilog-XL"
52
  echo "                  - ncverilog : NC-Verilog"
53
  echo "                  - vcs       : VCS"
54
  echo "                  - vsim      : Modelsim"
55 136 olivier.gi
  echo "                  - isim      : Xilinx simulator"
56 98 olivier.gi
  echo ""
57 80 olivier.gi
  exit 1
58
fi
59
 
60
 
61
###############################################################################
62
#                     Check if the required files exist                       #
63
###############################################################################
64
softdir=../../../software/$1;
65
elffile=../../../software/$1/$1.elf;
66
verfile=../src/$1.v;
67
submitfile=../src/submit.f;
68
incfile=../../../rtl/verilog/openmsp430/openMSP430_defines.v;
69
 
70
if [ ! -e $softdir ]; then
71
    echo "Software directory doesn't exist: $softdir"
72
    exit 1
73
fi
74
if [ ! -e $verfile ]; then
75
    echo "Verilog stimulus file $verfile doesn't exist: $verfile"
76
    exit 1
77
fi
78
if [ ! -e $submitfile ]; then
79
    echo "Verilog submit file $submitfile doesn't exist: $submitfile"
80
    exit 1
81
fi
82
 
83
 
84
###############################################################################
85
#                               Cleanup                                       #
86
###############################################################################
87
echo "Cleanup..."
88 98 olivier.gi
rm -rf *.vcd
89
rm -rf *.vpd
90
rm -rf *.trn
91
rm -rf *.dsn
92 80 olivier.gi
rm -rf pmem.*
93
rm -rf stimulus.v
94
 
95
 
96
###############################################################################
97
#                              Run simulation                                 #
98
###############################################################################
99
echo " ======================================================="
100
echo "| Start simulation:             $1"
101
echo " ======================================================="
102
 
103
# Make C program
104
cd $softdir
105
make clean
106
make
107
cd ../../sim/rtl_sim/run/
108
 
109
# Create links
110 138 olivier.gi
if [ `uname -o` = "Cygwin" ]
111
then
112
    cp $elffile pmem.elf
113
    cp $verfile stimulus.v
114
else
115
    ln -s $elffile pmem.elf
116
    ln -s $verfile stimulus.v
117
fi
118 80 olivier.gi
 
119 151 olivier.gi
# Make local copy of the openMSP403 configuration file
120
# and prepare it for MSPGCC preprocessing
121
cp  $incfile  ./pmem.h
122
sed -i 's/`ifdef/#ifdef/g'   ./pmem.h
123
sed -i 's/`else/#else/g'     ./pmem.h
124
sed -i 's/`endif/#endif/g'   ./pmem.h
125
sed -i 's/`define/#define/g' ./pmem.h
126
sed -i 's/`//g'              ./pmem.h
127
sed -i "s/'//g"              ./pmem.h
128 80 olivier.gi
 
129 151 olivier.gi
# Use MSPGCC preprocessor to extract the Program, Data
130
# and Peripheral memory sizes
131
msp430-gcc -E -P -x c ../bin/omsp_config.sh > pmem.sh
132 80 olivier.gi
 
133 151 olivier.gi
# Source the extracted configuration file
134
source pmem.sh
135
 
136 80 olivier.gi
# Create IHEX file from ELF
137
echo "Convert ELF file to IHEX format..."
138
msp430-objcopy -O ihex  pmem.elf pmem.ihex
139
 
140
# Generate Program memory file
141
echo "Convert IHEX file to Verilog MEMH format..."
142
../bin/ihex2mem.tcl -ihex pmem.ihex -out pmem.mem -mem_size $pmemsize
143
 
144
# Start verilog simulation
145
echo "Start Verilog simulation..."
146
../bin/rtlsim.sh    stimulus.v pmem.mem $submitfile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.