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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [src/] [spacewar.v] - Blame information for rev 211

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Line No. Rev Author Line
1 80 olivier.gi
/*===========================================================================*/
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/*                                 DIGITAL I/O                               */
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/*---------------------------------------------------------------------------*/
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/* Test the Digital I/O interface.                                           */
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/*===========================================================================*/
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge oscclk);
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      stimulus_done = 0;
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15 107 olivier.gi
      repeat(50) @(posedge mclk);
16 80 olivier.gi
 
17 107 olivier.gi
      // Send uart synchronization frame
18 136 olivier.gi
      dbg_uart_sync;
19 80 olivier.gi
 
20 107 olivier.gi
      // Let the CPU run
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      dbg_uart_wr(CPU_CTL,  16'h0002);
22 80 olivier.gi
 
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      stimulus_done = 1;
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   end
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