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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.pdc] - Blame information for rev 211

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#------------------------------------------------------------------------------
# Actel Physical design constraints file
#------------------------------------------------------------------------------
 
#----------------------#
# I/O constraints      #
# ---------------------#
 
# CLOCK & RESET
#------------------------------------------------
set_io oscclk              -pinname E4
set_io porst_n             -pinname V7
set_io pbrst_n             -pinname T9
 
 
# GPIOA
#------------------------------------------------
set_io din_x               -pinname D5     ;# GPIOA_0
set_io sclk_x              -pinname D6     ;# GPIOA_1
set_io sync_n_x            -pinname D10    ;# GPIOA_2
set_io din_y               -pinname G10    ;# GPIOA_3
set_io sync_n_y            -pinname G11    ;# GPIOA_4
set_io sclk_y              -pinname E11    ;# GPIOA_5
 
 
# UART INTERFACE
#------------------------------------------------
set_io uart_rx             -pinname D9
set_io uart_tx             -pinname G9
 
 
# SWITCHES & LEDS
#------------------------------------------------
#set_io switch\[0\]         -pinname D18
#set_io switch\[1\]         -pinname D17
#set_io switch\[2\]         -pinname E17
#set_io switch\[3\]         -pinname F16
#set_io switch\[4\]         -pinname D15
#set_io switch\[5\]         -pinname G14
#set_io switch\[6\]         -pinname E14
#set_io switch\[7\]         -pinname F14
#set_io switch\[8\]         -pinname G13
#set_io switch\[9\]         -pinname D14
set_io led\[0\]            -pinname E10
set_io led\[1\]            -pinname F10
set_io led\[2\]            -pinname U8
set_io led\[3\]            -pinname W5
set_io led\[4\]            -pinname U7
set_io led\[5\]            -pinname V6
set_io led\[6\]            -pinname U5
set_io led\[7\]            -pinname U4
set_io led\[8\]            -pinname V4
set_io led\[9\]            -pinname V5
 

Line No.	Rev	Author	Line
1	82	olivier.gi	`#------------------------------------------------------------------------------`
2			`# Actel Physical design constraints file`
3			`#------------------------------------------------------------------------------`
4
5			`#----------------------#`
6			`# I/O constraints #`
7			`# ---------------------#`
8
9			`# CLOCK & RESET`
10			`#------------------------------------------------`
11			`set_io oscclk -pinname E4`
12			`set_io porst_n -pinname V7`
13			`set_io pbrst_n -pinname T9`
14
15
16			`# GPIOA`
17			`#------------------------------------------------`
18			`set_io din_x -pinname D5 ;# GPIOA_0`
19			`set_io sclk_x -pinname D6 ;# GPIOA_1`
20			`set_io sync_n_x -pinname D10 ;# GPIOA_2`
21			`set_io din_y -pinname G10 ;# GPIOA_3`
22			`set_io sync_n_y -pinname G11 ;# GPIOA_4`
23			`set_io sclk_y -pinname E11 ;# GPIOA_5`
24
25
26			`# UART INTERFACE`
27			`#------------------------------------------------`
28			`set_io uart_rx -pinname D9`
29			`set_io uart_tx -pinname G9`
30
31
32			`# SWITCHES & LEDS`
33			`#------------------------------------------------`
34			`#set_io switch\[0\] -pinname D18`
35			`#set_io switch\[1\] -pinname D17`
36			`#set_io switch\[2\] -pinname E17`
37			`#set_io switch\[3\] -pinname F16`
38			`#set_io switch\[4\] -pinname D15`
39			`#set_io switch\[5\] -pinname G14`
40			`#set_io switch\[6\] -pinname E14`
41			`#set_io switch\[7\] -pinname F14`
42			`#set_io switch\[8\] -pinname G13`
43			`#set_io switch\[9\] -pinname D14`
44			`set_io led\[0\] -pinname E10`
45			`set_io led\[1\] -pinname F10`
46			`set_io led\[2\] -pinname U8`
47			`set_io led\[3\] -pinname W5`
48			`set_io led\[4\] -pinname U7`
49			`set_io led\[5\] -pinname V6`
50			`set_io led\[6\] -pinname U5`
51			`set_io led\[7\] -pinname U4`
52			`set_io led\[8\] -pinname V4`
53			`set_io led\[9\] -pinname V5`
54

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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.pdc] - Blame information for rev 211