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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.post.sdc] - Blame information for rev 150

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# Design Constraints
 
create_clock -name oscclk  -period 20.0 -waveform [list 0.0 10.0]  oscclk
create_clock -name dco_clk -period 62.5 -waveform [list 0.0 31.25] pll_0:GLA
 
set_false_path -from {pbrst_n}
set_false_path -from {porst_n}

Line No.	Rev	Author	Line
1	82	olivier.gi	`# Design Constraints`
2
3			`create_clock -name oscclk -period 20.0 -waveform [list 0.0 10.0] oscclk`
4			`create_clock -name dco_clk -period 62.5 -waveform [list 0.0 31.25] pll_0:GLA`
5
6			`set_false_path -from {pbrst_n}`
7			`set_false_path -from {porst_n}`

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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.post.sdc] - Blame information for rev 150