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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.pre.sdc] - Blame information for rev 111

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# Design Constraints
 
define_clock   {oscclk}       -name {oscclk }  -freq 50  -rise 0.0  -fall 10
define_clock   {n:pll_0.GLA}  -name {dco_clk}  -freq 16  -rise 0.0  -fall 31.25
 
define_input_delay   -default  15.00 -improve 0.00 -route 0.00
define_output_delay  -default   8.00 -improve 0.00 -route 0.00
 
define_false_path  -from {{p:pbrst_n}}
define_false_path  -from {{p:porst_n}}

Line No.	Rev	Author	Line
1	82	olivier.gi	`# Design Constraints`
2
3			`define_clock {oscclk} -name {oscclk } -freq 50 -rise 0.0 -fall 10`
4			`define_clock {n:pll_0.GLA} -name {dco_clk} -freq 16 -rise 0.0 -fall 31.25`
5
6			`define_input_delay -default 15.00 -improve 0.00 -route 0.00`
7			`define_output_delay -default 8.00 -improve 0.00 -route 0.00`
8
9			`define_false_path -from {{p:pbrst_n}}`
10			`define_false_path -from {{p:porst_n}}`

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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.pre.sdc] - Blame information for rev 111