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olivier.gi |
// START_MODULE_NAME------------------------------------------------------------
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//
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// Module Name : ALTSYNCRAM
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//
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// Description : Synchronous ram model for Stratix series family
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//
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// Limitation :
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//
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// END_MODULE_NAME--------------------------------------------------------------
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`timescale 1 ps / 1 ps
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// BEGINNING OF MODULE
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// MODULE DECLARATION
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module altsyncram (
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wren_a,
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wren_b,
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rden_a,
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rden_b,
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data_a,
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data_b,
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address_a,
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address_b,
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clock0,
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clock1,
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clocken0,
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clocken1,
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clocken2,
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clocken3,
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aclr0,
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aclr1,
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byteena_a,
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byteena_b,
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addressstall_a,
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addressstall_b,
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q_a,
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q_b,
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eccstatus
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);
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// GLOBAL PARAMETER DECLARATION
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// PORT A PARAMETERS
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parameter width_a = 1;
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parameter widthad_a = 1;
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parameter numwords_a = 0;
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parameter outdata_reg_a = "UNREGISTERED";
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parameter address_aclr_a = "NONE";
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parameter outdata_aclr_a = "NONE";
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parameter indata_aclr_a = "NONE";
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parameter wrcontrol_aclr_a = "NONE";
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parameter byteena_aclr_a = "NONE";
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parameter width_byteena_a = 1;
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// PORT B PARAMETERS
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parameter width_b = 1;
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parameter widthad_b = 1;
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parameter numwords_b = 0;
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parameter rdcontrol_reg_b = "CLOCK1";
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parameter address_reg_b = "CLOCK1";
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parameter outdata_reg_b = "UNREGISTERED";
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parameter outdata_aclr_b = "NONE";
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parameter rdcontrol_aclr_b = "NONE";
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parameter indata_reg_b = "CLOCK1";
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parameter wrcontrol_wraddress_reg_b = "CLOCK1";
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parameter byteena_reg_b = "CLOCK1";
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parameter indata_aclr_b = "NONE";
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parameter wrcontrol_aclr_b = "NONE";
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parameter address_aclr_b = "NONE";
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parameter byteena_aclr_b = "NONE";
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parameter width_byteena_b = 1;
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// STRATIX II RELATED PARAMETERS
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parameter clock_enable_input_a = "NORMAL";
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parameter clock_enable_output_a = "NORMAL";
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parameter clock_enable_input_b = "NORMAL";
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parameter clock_enable_output_b = "NORMAL";
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parameter clock_enable_core_a = "USE_INPUT_CLKEN";
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parameter clock_enable_core_b = "USE_INPUT_CLKEN";
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parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
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parameter read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
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// ECC STATUS RELATED PARAMETERS
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parameter enable_ecc = "FALSE";
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// GLOBAL PARAMETERS
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parameter operation_mode = "BIDIR_DUAL_PORT";
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parameter byte_size = 0;
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parameter read_during_write_mode_mixed_ports = "DONT_CARE";
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parameter ram_block_type = "AUTO";
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parameter init_file = "UNUSED";
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parameter init_file_layout = "UNUSED";
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parameter maximum_depth = 0;
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parameter intended_device_family = "Stratix";
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parameter lpm_hint = "UNUSED";
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parameter lpm_type = "altsyncram";
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parameter implement_in_les = "OFF";
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parameter power_up_uninitialized = "FALSE";
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parameter sim_show_memory_data_in_port_b_layout = "OFF";
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// Internal parameters
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parameter is_lutram = ((ram_block_type == "LUTRAM") || (ram_block_type == "MLAB"))? 1 : 0;
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parameter is_bidir_and_wrcontrol_addb_clk0 = (((operation_mode == "BIDIR_DUAL_PORT") && (address_reg_b == "CLOCK0"))?
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1 : 0);
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parameter is_bidir_and_wrcontrol_addb_clk1 = (((operation_mode == "BIDIR_DUAL_PORT") && (address_reg_b == "CLOCK1"))?
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1 : 0);
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parameter check_simultaneous_read_write = (((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "DUAL_PORT")) &&
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((ram_block_type == "M-RAM") ||
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(ram_block_type == "MEGARAM") ||
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((ram_block_type == "AUTO") && (read_during_write_mode_mixed_ports == "DONT_CARE")) ||
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((is_lutram == 1) && ((read_during_write_mode_mixed_ports != "OLD_DATA") || (outdata_reg_b == "UNREGISTERED")))))? 1 : 0;
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parameter dual_port_addreg_b_clk0 = (((operation_mode == "DUAL_PORT") && (address_reg_b == "CLOCK0"))? 1: 0);
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parameter dual_port_addreg_b_clk1 = (((operation_mode == "DUAL_PORT") && (address_reg_b == "CLOCK1"))? 1: 0);
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parameter i_byte_size_tmp = (width_byteena_a > 1)? width_a / width_byteena_a : 8;
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parameter i_lutram_read = (((is_lutram == 1) && (read_during_write_mode_port_a == "DONT_CARE")) ||
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((is_lutram == 1) && (outdata_reg_a == "UNREGISTERED") && (operation_mode == "SINGLE_PORT")))? 1 : 0;
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parameter enable_mem_data_b_reading = (sim_show_memory_data_in_port_b_layout == "ON") &&
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((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "DUAL_PORT")) ? 1 : 0;
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// INPUT PORT DECLARATION
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input wren_a; // Port A write/read enable input
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input wren_b; // Port B write enable input
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input rden_a; // Port A read enable input
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input rden_b; // Port B read enable input
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input [width_a-1:0] data_a; // Port A data input
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input [width_b-1:0] data_b; // Port B data input
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input [widthad_a-1:0] address_a; // Port A address input
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input [widthad_b-1:0] address_b; // Port B address input
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// clock inputs on both ports and here are their usage
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// Port A -- 1. all input registers must be clocked by clock0.
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// 2. output register can be clocked by either clock0, clock1 or none.
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// Port B -- 1. all input registered must be clocked by either clock0 or clock1.
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// 2. output register can be clocked by either clock0, clock1 or none.
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input clock0;
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input clock1;
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// clock enable inputs and here are their usage
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// clocken0 -- can only be used for enabling clock0.
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// clocken1 -- can only be used for enabling clock1.
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// clocken2 -- as an alternative for enabling clock0.
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// clocken3 -- as an alternative for enabling clock1.
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input clocken0;
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input clocken1;
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input clocken2;
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input clocken3;
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// clear inputs on both ports and here are their usage
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// Port A -- 1. all input registers can only be cleared by clear0 or none.
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// 2. output register can be cleared by either clear0, clear1 or none.
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// Port B -- 1. all input registers can be cleared by clear0, clear1 or none.
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// 2. output register can be cleared by either clear0, clear1 or none.
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input aclr0;
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input aclr1;
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input [width_byteena_a-1:0] byteena_a; // Port A byte enable input
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input [width_byteena_b-1:0] byteena_b; // Port B byte enable input
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// Stratix II related ports
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input addressstall_a;
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input addressstall_b;
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// OUTPUT PORT DECLARATION
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output [width_a-1:0] q_a; // Port A output
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output [width_b-1:0] q_b; // Port B output
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output [2:0] eccstatus; // ECC status flags
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// INTERNAL REGISTERS DECLARATION
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reg [width_a-1:0] mem_data [0:(1<<widthad_a)-1];
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reg [width_b-1:0] mem_data_b [0:(1<<widthad_b)-1];
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reg [width_a-1:0] i_data_reg_a;
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reg [width_a-1:0] temp_wa;
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reg [width_a-1:0] temp_wa2;
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reg [width_a-1:0] temp_wa2b;
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reg [width_a-1:0] init_temp;
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reg [width_b-1:0] i_data_reg_b;
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reg [width_b-1:0] temp_wb;
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reg [width_b-1:0] temp_wb2;
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reg temp;
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reg [width_a-1:0] i_q_reg_a;
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reg [width_a-1:0] i_q_tmp_a;
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reg [width_a-1:0] i_q_tmp2_a;
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reg [width_b-1:0] i_q_reg_b;
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reg [width_b-1:0] i_q_tmp_b;
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reg [width_b-1:0] i_q_tmp2_b;
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reg [width_b-1:0] i_q_output_latch;
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reg [width_a-1:0] i_byteena_mask_reg_a;
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reg [width_b-1:0] i_byteena_mask_reg_b;
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reg [widthad_a-1:0] i_address_reg_a;
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reg [widthad_b-1:0] i_address_reg_b;
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reg [widthad_a-1:0] i_original_address_a;
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reg [width_a-1:0] i_byteena_mask_reg_a_tmp;
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reg [width_b-1:0] i_byteena_mask_reg_b_tmp;
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reg [width_a-1:0] i_byteena_mask_reg_a_out;
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reg [width_b-1:0] i_byteena_mask_reg_b_out;
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reg [width_a-1:0] i_byteena_mask_reg_a_x;
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reg [width_b-1:0] i_byteena_mask_reg_b_x;
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reg [width_a-1:0] i_byteena_mask_reg_a_out_b;
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reg [width_b-1:0] i_byteena_mask_reg_b_out_a;
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reg [8*256:1] ram_initf;
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reg i_wren_reg_a;
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reg i_wren_reg_b;
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reg i_rden_reg_a;
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reg i_rden_reg_b;
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reg i_read_flag_a;
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reg i_read_flag_b;
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reg i_write_flag_a;
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reg i_write_flag_b;
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reg good_to_go_a;
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reg good_to_go_b;
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reg [31:0] file_desc;
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reg init_file_b_port;
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reg i_nmram_write_a;
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reg i_nmram_write_b;
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reg [width_a - 1: 0] wa_mult_x;
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reg [width_a - 1: 0] wa_mult_x_ii;
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reg [width_a - 1: 0] wa_mult_x_iii;
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reg [widthad_a + width_a - 1:0] add_reg_a_mult_wa;
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reg [widthad_b + width_b -1:0] add_reg_b_mult_wb;
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reg [widthad_a + width_a - 1:0] add_reg_a_mult_wa_pl_wa;
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reg [widthad_b + width_b -1:0] add_reg_b_mult_wb_pl_wb;
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reg same_clock_pulse0;
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reg same_clock_pulse1;
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reg [width_b - 1 : 0] i_original_data_b;
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reg [width_a - 1 : 0] i_original_data_a;
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reg i_address_aclr_a_flag;
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reg i_address_aclr_a_prev;
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reg i_address_aclr_b_flag;
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reg i_address_aclr_b_prev;
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reg i_outdata_aclr_a_prev;
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reg i_outdata_aclr_b_prev;
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reg i_force_reread_a;
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reg i_force_reread_a1;
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reg i_force_reread_b;
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reg i_force_reread_b1;
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reg i_force_reread_a_signal;
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reg i_force_reread_b_signal;
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// INTERNAL PARAMETER
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reg is_write_positive_edge_reg;
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reg [9*8:0] cread_during_write_mode_mixed_ports;
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reg i_lutram_single_port_fast_read;
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reg i_lutram_dual_port_fast_read;
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reg [7*8:0] i_ram_block_type;
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integer i_byte_size;
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wire i_good_to_write_a;
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wire i_good_to_write_b;
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reg i_good_to_write_a2;
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reg i_good_to_write_b2;
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reg i_core_clocken_a_reg;
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reg i_core_clocken0_b_reg;
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reg i_core_clocken1_b_reg;
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wire s3_address_aclr_a;
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wire s3_address_aclr_b;
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// INTERNAL WIRE DECLARATIONS
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wire i_indata_aclr_a;
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wire i_address_aclr_a;
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wire i_address_aclr_family_a;
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wire i_wrcontrol_aclr_a;
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wire i_indata_aclr_b;
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wire i_address_aclr_b;
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wire i_address_aclr_family_b;
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wire i_wrcontrol_aclr_b;
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wire i_outdata_aclr_a;
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wire i_outdata_aclr_b;
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wire i_rdcontrol_aclr_b;
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wire i_byteena_aclr_a;
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wire i_byteena_aclr_b;
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wire i_outdata_clk_a;
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wire i_outdata_clken_a;
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|
|
wire i_outdata_clk_b;
|
| 309 |
|
|
wire i_outdata_clken_b;
|
| 310 |
|
|
wire i_clocken0;
|
| 311 |
|
|
wire i_clocken1_b;
|
| 312 |
|
|
wire i_clocken0_b;
|
| 313 |
|
|
wire i_core_clocken_a;
|
| 314 |
|
|
wire i_core_clocken_b;
|
| 315 |
|
|
wire i_core_clocken0_b;
|
| 316 |
|
|
wire i_core_clocken1_b;
|
| 317 |
|
|
|
| 318 |
|
|
// INTERNAL TRI DECLARATION
|
| 319 |
|
|
|
| 320 |
|
|
tri0 wren_a;
|
| 321 |
|
|
tri0 wren_b;
|
| 322 |
|
|
tri1 rden_a;
|
| 323 |
|
|
tri1 rden_b;
|
| 324 |
|
|
tri1 clock0;
|
| 325 |
|
|
tri1 clocken0;
|
| 326 |
|
|
tri1 clocken1;
|
| 327 |
|
|
tri1 clocken2;
|
| 328 |
|
|
tri1 clocken3;
|
| 329 |
|
|
tri0 aclr0;
|
| 330 |
|
|
tri0 aclr1;
|
| 331 |
|
|
tri0 addressstall_a;
|
| 332 |
|
|
tri0 addressstall_b;
|
| 333 |
|
|
tri1 [width_byteena_a-1:0] i_byteena_a;
|
| 334 |
|
|
tri1 [width_byteena_b-1:0] i_byteena_b;
|
| 335 |
|
|
|
| 336 |
|
|
|
| 337 |
|
|
// LOCAL INTEGER DECLARATION
|
| 338 |
|
|
|
| 339 |
|
|
integer i_numwords_a;
|
| 340 |
|
|
integer i_numwords_b;
|
| 341 |
|
|
integer i_aclr_flag_a;
|
| 342 |
|
|
integer i_aclr_flag_b;
|
| 343 |
|
|
integer i_q_tmp2_a_idx;
|
| 344 |
|
|
|
| 345 |
|
|
// for loop iterators
|
| 346 |
|
|
integer init_i;
|
| 347 |
|
|
integer i;
|
| 348 |
|
|
integer i2;
|
| 349 |
|
|
integer i3;
|
| 350 |
|
|
integer i4;
|
| 351 |
|
|
integer i5;
|
| 352 |
|
|
integer j;
|
| 353 |
|
|
integer j2;
|
| 354 |
|
|
integer j3;
|
| 355 |
|
|
integer k;
|
| 356 |
|
|
integer k2;
|
| 357 |
|
|
integer k3;
|
| 358 |
|
|
integer k4;
|
| 359 |
|
|
|
| 360 |
|
|
// For temporary calculation
|
| 361 |
|
|
integer i_div_wa;
|
| 362 |
|
|
integer i_div_wb;
|
| 363 |
|
|
integer j_plus_i2;
|
| 364 |
|
|
integer j2_plus_i5;
|
| 365 |
|
|
integer j3_plus_i5;
|
| 366 |
|
|
integer j_plus_i2_div_a;
|
| 367 |
|
|
integer j2_plus_i5_div_a;
|
| 368 |
|
|
integer j3_plus_i5_div_a;
|
| 369 |
|
|
integer j3_plus_i5_div_b;
|
| 370 |
|
|
integer i_byteena_count;
|
| 371 |
|
|
integer port_a_bit_count_low;
|
| 372 |
|
|
integer port_a_bit_count_high;
|
| 373 |
|
|
integer port_b_bit_count_low;
|
| 374 |
|
|
integer port_b_bit_count_high;
|
| 375 |
|
|
|
| 376 |
|
|
time i_data_write_time_a;
|
| 377 |
|
|
|
| 378 |
|
|
// ------------------------
|
| 379 |
|
|
// COMPONENT INSTANTIATIONS
|
| 380 |
|
|
// ------------------------
|
| 381 |
|
|
ALTERA_DEVICE_FAMILIES dev ();
|
| 382 |
|
|
ALTERA_MF_MEMORY_INITIALIZATION mem ();
|
| 383 |
|
|
|
| 384 |
|
|
// INITIAL CONSTRUCT BLOCK
|
| 385 |
|
|
|
| 386 |
|
|
initial
|
| 387 |
|
|
begin
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
i_numwords_a = (numwords_a != 0) ? numwords_a : (1 << widthad_a);
|
| 391 |
|
|
i_numwords_b = (numwords_b != 0) ? numwords_b : (1 << widthad_b);
|
| 392 |
|
|
|
| 393 |
|
|
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 394 |
|
|
begin
|
| 395 |
|
|
if ((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM"))
|
| 396 |
|
|
i_ram_block_type = "M144K";
|
| 397 |
|
|
else if ((((ram_block_type == "M144K") || (is_lutram == 1)) && (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1)) ||
|
| 398 |
|
|
(ram_block_type == "M9K"))
|
| 399 |
|
|
i_ram_block_type = ram_block_type;
|
| 400 |
|
|
else
|
| 401 |
|
|
i_ram_block_type = "AUTO";
|
| 402 |
|
|
end
|
| 403 |
|
|
else
|
| 404 |
|
|
begin
|
| 405 |
|
|
if ((ram_block_type != "AUTO") &&
|
| 406 |
|
|
(ram_block_type != "M-RAM") && (ram_block_type != "MEGARAM") &&
|
| 407 |
|
|
(ram_block_type != "M512") &&
|
| 408 |
|
|
(ram_block_type != "M4K"))
|
| 409 |
|
|
i_ram_block_type = "AUTO";
|
| 410 |
|
|
else
|
| 411 |
|
|
i_ram_block_type = ram_block_type;
|
| 412 |
|
|
end
|
| 413 |
|
|
|
| 414 |
|
|
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")) || (i_ram_block_type == "M9K") || (i_ram_block_type == "M144K") ||
|
| 415 |
|
|
((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (i_ram_block_type == "AUTO")))
|
| 416 |
|
|
is_write_positive_edge_reg = 1;
|
| 417 |
|
|
else
|
| 418 |
|
|
is_write_positive_edge_reg = 0;
|
| 419 |
|
|
|
| 420 |
|
|
if ((dev.FEATURE_FAMILY_CYCLONE(intended_device_family) == 1) || (dev.FEATURE_FAMILY_CYCLONEII(intended_device_family) == 1))
|
| 421 |
|
|
cread_during_write_mode_mixed_ports = "OLD_DATA";
|
| 422 |
|
|
else if (read_during_write_mode_mixed_ports == "UNUSED")
|
| 423 |
|
|
cread_during_write_mode_mixed_ports = "DONT_CARE";
|
| 424 |
|
|
else
|
| 425 |
|
|
cread_during_write_mode_mixed_ports = read_during_write_mode_mixed_ports;
|
| 426 |
|
|
|
| 427 |
|
|
if ((is_lutram == 1) &&
|
| 428 |
|
|
((read_during_write_mode_port_a == "DONT_CARE") || (outdata_reg_a == "UNREGISTERED")) &&
|
| 429 |
|
|
(operation_mode == "SINGLE_PORT"))
|
| 430 |
|
|
i_lutram_single_port_fast_read = 1;
|
| 431 |
|
|
else
|
| 432 |
|
|
i_lutram_single_port_fast_read = 0;
|
| 433 |
|
|
|
| 434 |
|
|
if ((is_lutram == 1) &&
|
| 435 |
|
|
((read_during_write_mode_mixed_ports == "NEW_DATA") ||
|
| 436 |
|
|
(read_during_write_mode_mixed_ports == "DONT_CARE") ||
|
| 437 |
|
|
((read_during_write_mode_mixed_ports == "OLD_DATA") && (outdata_reg_b == "UNREGISTERED"))))
|
| 438 |
|
|
i_lutram_dual_port_fast_read = 1;
|
| 439 |
|
|
else
|
| 440 |
|
|
i_lutram_dual_port_fast_read = 0;
|
| 441 |
|
|
|
| 442 |
|
|
i_byte_size = (byte_size > 0) ? byte_size
|
| 443 |
|
|
: ((((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) || dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) && (i_byte_size_tmp != 8) && (i_byte_size_tmp != 9)) ||
|
| 444 |
|
|
(((dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1) || (dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) && (i_byte_size_tmp != 1) && (i_byte_size_tmp != 2) && (i_byte_size_tmp != 4) && (i_byte_size_tmp != 8) && (i_byte_size_tmp != 9)) ||
|
| 445 |
|
|
((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (i_byte_size_tmp != 5) && (i_byte_size_tmp !=10) && (i_byte_size_tmp != 8) && (i_byte_size_tmp != 9))) ?
|
| 446 |
|
|
8 : i_byte_size_tmp;
|
| 447 |
|
|
|
| 448 |
|
|
// Parameter Checking
|
| 449 |
|
|
if ((operation_mode != "BIDIR_DUAL_PORT") && (operation_mode != "SINGLE_PORT") &&
|
| 450 |
|
|
(operation_mode != "DUAL_PORT") && (operation_mode != "ROM"))
|
| 451 |
|
|
begin
|
| 452 |
|
|
$display("Error: Not a valid operation mode.");
|
| 453 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 454 |
|
|
$finish;
|
| 455 |
|
|
end
|
| 456 |
|
|
|
| 457 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) &&
|
| 458 |
|
|
(ram_block_type != "M9K") && (ram_block_type != "M144K") && (is_lutram != 1) &&
|
| 459 |
|
|
(ram_block_type != "AUTO") && (((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM")) != 1))
|
| 460 |
|
|
begin
|
| 461 |
|
|
$display("Warning: RAM_BLOCK_TYPE HAS AN INVALID VALUE. IT CAN ONLY BE M9K, M144K, LUTRAM OR AUTO for %s device family. This parameter will take AUTO as it's value", intended_device_family);
|
| 462 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 463 |
|
|
end
|
| 464 |
|
|
|
| 465 |
|
|
if (i_ram_block_type != ram_block_type)
|
| 466 |
|
|
begin
|
| 467 |
|
|
$display("Warning: RAM block type is assumed as %s", i_ram_block_type);
|
| 468 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 469 |
|
|
end
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
if ((cread_during_write_mode_mixed_ports != "DONT_CARE") &&
|
| 473 |
|
|
(cread_during_write_mode_mixed_ports != "OLD_DATA") &&
|
| 474 |
|
|
(cread_during_write_mode_mixed_ports != "NEW_DATA"))
|
| 475 |
|
|
begin
|
| 476 |
|
|
$display("Error: Invalid value for read_during_write_mode_mixed_ports parameter. It has to be OLD_DATA or DONT_CARE or NEW_DATA");
|
| 477 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 478 |
|
|
$finish;
|
| 479 |
|
|
end
|
| 480 |
|
|
|
| 481 |
|
|
if ((cread_during_write_mode_mixed_ports != read_during_write_mode_mixed_ports) && ((operation_mode != "SINGLE_PORT") && (operation_mode != "ROM")))
|
| 482 |
|
|
begin
|
| 483 |
|
|
$display("Warning: read_during_write_mode_mixed_ports is assumed as %s", cread_during_write_mode_mixed_ports);
|
| 484 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 485 |
|
|
end
|
| 486 |
|
|
|
| 487 |
|
|
if ((is_lutram != 1) && (cread_during_write_mode_mixed_ports == "NEW_DATA"))
|
| 488 |
|
|
begin
|
| 489 |
|
|
$display("Warning: read_during_write_mode_mixed_ports cannot be set to NEW_DATA for non-LUTRAM ram block type. This will cause incorrect simulation result.");
|
| 490 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 491 |
|
|
end
|
| 492 |
|
|
|
| 493 |
|
|
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")) && init_file != "UNUSED")
|
| 494 |
|
|
begin
|
| 495 |
|
|
$display("Error: M-RAM block type doesn't support the use of an initialization file");
|
| 496 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 497 |
|
|
$finish;
|
| 498 |
|
|
end
|
| 499 |
|
|
|
| 500 |
|
|
if ((i_byte_size != 8) && (i_byte_size != 9) && (dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1))
|
| 501 |
|
|
begin
|
| 502 |
|
|
$display("Error: byte_size HAS TO BE EITHER 8 or 9");
|
| 503 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 504 |
|
|
$finish;
|
| 505 |
|
|
end
|
| 506 |
|
|
|
| 507 |
|
|
if ((i_byte_size != 8) && (i_byte_size != 9) && (i_byte_size != 1) &&
|
| 508 |
|
|
(i_byte_size != 2) && (i_byte_size != 4) &&
|
| 509 |
|
|
((dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1) || (dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)))
|
| 510 |
|
|
begin
|
| 511 |
|
|
$display("Error: byte_size has to be either 1, 2, 4, 8 or 9 for %s device family", intended_device_family);
|
| 512 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 513 |
|
|
$finish;
|
| 514 |
|
|
end
|
| 515 |
|
|
|
| 516 |
|
|
if ((i_byte_size != 5) && (i_byte_size != 8) && (i_byte_size != 9) && (i_byte_size != 10) &&
|
| 517 |
|
|
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))
|
| 518 |
|
|
begin
|
| 519 |
|
|
$display("Error: byte_size has to be either 5,8,9 or 10 for %s device family", intended_device_family);
|
| 520 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 521 |
|
|
$finish;
|
| 522 |
|
|
end
|
| 523 |
|
|
|
| 524 |
|
|
if (width_a <= 0)
|
| 525 |
|
|
begin
|
| 526 |
|
|
$display("Error: Invalid value for WIDTH_A parameter");
|
| 527 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 528 |
|
|
$finish;
|
| 529 |
|
|
end
|
| 530 |
|
|
|
| 531 |
|
|
if ((width_b <= 0) &&
|
| 532 |
|
|
((operation_mode != "SINGLE_PORT") || (operation_mode != "ROM")))
|
| 533 |
|
|
begin
|
| 534 |
|
|
$display("Error: Invalid value for WIDTH_B parameter");
|
| 535 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 536 |
|
|
$finish;
|
| 537 |
|
|
end
|
| 538 |
|
|
|
| 539 |
|
|
if (widthad_a <= 0)
|
| 540 |
|
|
begin
|
| 541 |
|
|
$display("Error: Invalid value for WIDTHAD_A parameter");
|
| 542 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 543 |
|
|
$finish;
|
| 544 |
|
|
end
|
| 545 |
|
|
|
| 546 |
|
|
if ((width_b <= 0) &&
|
| 547 |
|
|
((operation_mode != "SINGLE_PORT") || (operation_mode != "ROM")))
|
| 548 |
|
|
begin
|
| 549 |
|
|
$display("Error: Invalid value for WIDTHAD_B parameter");
|
| 550 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 551 |
|
|
$finish;
|
| 552 |
|
|
end
|
| 553 |
|
|
|
| 554 |
|
|
if ((operation_mode == "ROM") &&
|
| 555 |
|
|
((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")))
|
| 556 |
|
|
begin
|
| 557 |
|
|
$display("Error: ROM mode does not support RAM_BLOCK_TYPE = M-RAM");
|
| 558 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 559 |
|
|
$finish;
|
| 560 |
|
|
end
|
| 561 |
|
|
|
| 562 |
|
|
if (((wrcontrol_aclr_a != "NONE") && (wrcontrol_aclr_a != "UNUSED")) && (i_ram_block_type == "M512") && (operation_mode == "SINGLE_PORT"))
|
| 563 |
|
|
begin
|
| 564 |
|
|
$display("Error: Wren_a cannot have clear in single port mode for M512 block");
|
| 565 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 566 |
|
|
$finish;
|
| 567 |
|
|
end
|
| 568 |
|
|
|
| 569 |
|
|
if ((operation_mode == "DUAL_PORT") && (i_numwords_a * width_a != i_numwords_b * width_b))
|
| 570 |
|
|
begin
|
| 571 |
|
|
$display("Error: Total number of bits of port A and port B should be the same for dual port mode");
|
| 572 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 573 |
|
|
$finish;
|
| 574 |
|
|
end
|
| 575 |
|
|
|
| 576 |
|
|
if (((rdcontrol_aclr_b != "NONE") && (rdcontrol_aclr_b != "UNUSED")) && (i_ram_block_type == "M512") && (operation_mode == "DUAL_PORT"))
|
| 577 |
|
|
begin
|
| 578 |
|
|
$display("Error: rden_b cannot have clear in simple dual port mode for M512 block");
|
| 579 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 580 |
|
|
$finish;
|
| 581 |
|
|
end
|
| 582 |
|
|
|
| 583 |
|
|
if ((operation_mode == "BIDIR_DUAL_PORT") && (i_numwords_a * width_a != i_numwords_b * width_b))
|
| 584 |
|
|
begin
|
| 585 |
|
|
$display("Error: Total number of bits of port A and port B should be the same for bidir dual port mode");
|
| 586 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 587 |
|
|
$finish;
|
| 588 |
|
|
end
|
| 589 |
|
|
|
| 590 |
|
|
if ((operation_mode == "BIDIR_DUAL_PORT") && (i_ram_block_type == "M512"))
|
| 591 |
|
|
begin
|
| 592 |
|
|
$display("Error: M512 block type doesn't support bidir dual mode");
|
| 593 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 594 |
|
|
$finish;
|
| 595 |
|
|
end
|
| 596 |
|
|
|
| 597 |
|
|
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")) &&
|
| 598 |
|
|
(cread_during_write_mode_mixed_ports == "OLD_DATA"))
|
| 599 |
|
|
begin
|
| 600 |
|
|
$display("Error: M-RAM doesn't support OLD_DATA value for READ_DURING_WRITE_MODE_MIXED_PORTS parameter");
|
| 601 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 602 |
|
|
$finish;
|
| 603 |
|
|
end
|
| 604 |
|
|
|
| 605 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
|
| 606 |
|
|
(clock_enable_input_a == "BYPASS"))
|
| 607 |
|
|
begin
|
| 608 |
|
|
$display("Error: BYPASS value for CLOCK_ENABLE_INPUT_A is not supported in %s device family", intended_device_family);
|
| 609 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 610 |
|
|
$finish;
|
| 611 |
|
|
end
|
| 612 |
|
|
|
| 613 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
|
| 614 |
|
|
(clock_enable_output_a == "BYPASS"))
|
| 615 |
|
|
begin
|
| 616 |
|
|
$display("Error: BYPASS value for CLOCK_ENABLE_OUTPUT_A is not supported in %s device family", intended_device_family);
|
| 617 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 618 |
|
|
$finish;
|
| 619 |
|
|
end
|
| 620 |
|
|
|
| 621 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
|
| 622 |
|
|
(clock_enable_input_b == "BYPASS"))
|
| 623 |
|
|
begin
|
| 624 |
|
|
$display("Error: BYPASS value for CLOCK_ENABLE_INPUT_B is not supported in %s device family", intended_device_family);
|
| 625 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 626 |
|
|
$finish;
|
| 627 |
|
|
end
|
| 628 |
|
|
|
| 629 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
|
| 630 |
|
|
(clock_enable_output_b == "BYPASS"))
|
| 631 |
|
|
begin
|
| 632 |
|
|
$display("Error: BYPASS value for CLOCK_ENABLE_OUTPUT_B is not supported in %s device family", intended_device_family);
|
| 633 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 634 |
|
|
$finish;
|
| 635 |
|
|
end
|
| 636 |
|
|
|
| 637 |
|
|
if ((implement_in_les != "OFF") && (implement_in_les != "ON"))
|
| 638 |
|
|
begin
|
| 639 |
|
|
$display("Error: Illegal value for implement_in_les parameter");
|
| 640 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 641 |
|
|
$finish;
|
| 642 |
|
|
end
|
| 643 |
|
|
|
| 644 |
|
|
if (((dev.FEATURE_FAMILY_HAS_M512(intended_device_family)) == 0) && (i_ram_block_type == "M512"))
|
| 645 |
|
|
begin
|
| 646 |
|
|
$display("Error: M512 value for RAM_BLOCK_TYPE parameter is not supported in %s device family", intended_device_family);
|
| 647 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 648 |
|
|
$finish;
|
| 649 |
|
|
end
|
| 650 |
|
|
|
| 651 |
|
|
if (((dev.FEATURE_FAMILY_HAS_MEGARAM(intended_device_family)) == 0) &&
|
| 652 |
|
|
((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")))
|
| 653 |
|
|
begin
|
| 654 |
|
|
$display("Error: MEGARAM value for RAM_BLOCK_TYPE parameter is not supported in %s device family", intended_device_family);
|
| 655 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 656 |
|
|
$finish;
|
| 657 |
|
|
end
|
| 658 |
|
|
|
| 659 |
|
|
if (((init_file == "UNUSED") || (init_file == "")) &&
|
| 660 |
|
|
(operation_mode == "ROM"))
|
| 661 |
|
|
begin
|
| 662 |
|
|
$display("Error! Altsyncram needs data file for memory initialization in ROM mode.");
|
| 663 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 664 |
|
|
$finish;
|
| 665 |
|
|
end
|
| 666 |
|
|
|
| 667 |
|
|
if (((dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1) || (dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) &&
|
| 668 |
|
|
(((indata_aclr_a != "UNUSED") && (indata_aclr_a != "NONE")) ||
|
| 669 |
|
|
((wrcontrol_aclr_a != "UNUSED") && (wrcontrol_aclr_a != "NONE")) ||
|
| 670 |
|
|
((byteena_aclr_a != "UNUSED") && (byteena_aclr_a != "NONE")) ||
|
| 671 |
|
|
((address_aclr_a != "UNUSED") && (address_aclr_a != "NONE") && (operation_mode != "ROM")) ||
|
| 672 |
|
|
((indata_aclr_b != "UNUSED") && (indata_aclr_b != "NONE")) ||
|
| 673 |
|
|
((rdcontrol_aclr_b != "UNUSED") && (rdcontrol_aclr_b != "NONE")) ||
|
| 674 |
|
|
((wrcontrol_aclr_b != "UNUSED") && (wrcontrol_aclr_b != "NONE")) ||
|
| 675 |
|
|
((byteena_aclr_b != "UNUSED") && (byteena_aclr_b != "NONE")) ||
|
| 676 |
|
|
((address_aclr_b != "UNUSED") && (address_aclr_b != "NONE") && (operation_mode != "DUAL_PORT"))))
|
| 677 |
|
|
begin
|
| 678 |
|
|
$display("Warning: %s device family does not support aclr signal on input ports. The aclr to input ports will be ignored.", intended_device_family);
|
| 679 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 680 |
|
|
end
|
| 681 |
|
|
|
| 682 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) &&
|
| 683 |
|
|
(((indata_aclr_a != "UNUSED") && (indata_aclr_a != "NONE")) ||
|
| 684 |
|
|
((wrcontrol_aclr_a != "UNUSED") && (wrcontrol_aclr_a != "NONE")) ||
|
| 685 |
|
|
((byteena_aclr_a != "UNUSED") && (byteena_aclr_a != "NONE")) ||
|
| 686 |
|
|
((address_aclr_a != "UNUSED") && (address_aclr_a != "NONE") && (operation_mode != "ROM")) ||
|
| 687 |
|
|
((indata_aclr_b != "UNUSED") && (indata_aclr_b != "NONE")) ||
|
| 688 |
|
|
((rdcontrol_aclr_b != "UNUSED") && (rdcontrol_aclr_b != "NONE")) ||
|
| 689 |
|
|
((wrcontrol_aclr_b != "UNUSED") && (wrcontrol_aclr_b != "NONE")) ||
|
| 690 |
|
|
((byteena_aclr_b != "UNUSED") && (byteena_aclr_b != "NONE")) ||
|
| 691 |
|
|
((address_aclr_b != "UNUSED") && (address_aclr_b != "NONE") && (operation_mode != "DUAL_PORT"))))
|
| 692 |
|
|
begin
|
| 693 |
|
|
$display("Warning: %s device family does not support aclr signal on input ports. The aclr to input ports will be ignored.", intended_device_family);
|
| 694 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 695 |
|
|
end
|
| 696 |
|
|
|
| 697 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
|
| 698 |
|
|
&& (read_during_write_mode_port_a != "NEW_DATA_NO_NBE_READ"))
|
| 699 |
|
|
begin
|
| 700 |
|
|
$display("Warning: %s value for read_during_write_mode_port_a is not supported in %s device family, it might cause incorrect behavioural simulation result", read_during_write_mode_port_a, intended_device_family);
|
| 701 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 702 |
|
|
end
|
| 703 |
|
|
|
| 704 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
|
| 705 |
|
|
&& (read_during_write_mode_port_b != "NEW_DATA_NO_NBE_READ"))
|
| 706 |
|
|
begin
|
| 707 |
|
|
$display("Warning: %s value for read_during_write_mode_port_b is not supported in %s device family, it might cause incorrect behavioural simulation result", read_during_write_mode_port_b, intended_device_family);
|
| 708 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 709 |
|
|
end
|
| 710 |
|
|
// SPR 249576: Enable don't care as RDW setting in MegaFunctions - eliminates checking for ram_block_type = "AUTO"
|
| 711 |
|
|
if (!((is_lutram == 1) || ((i_ram_block_type == "AUTO") && (dev.FEATURE_FAMILY_HAS_LUTRAM(intended_device_family) == 1)) ||
|
| 712 |
|
|
((i_ram_block_type != "AUTO") && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))) &&
|
| 713 |
|
|
(operation_mode != "SINGLE_PORT") && (read_during_write_mode_port_a == "DONT_CARE"))
|
| 714 |
|
|
begin
|
| 715 |
|
|
$display("Error: %s value for read_during_write_mode_port_a is not supported in %s device family for %s ram block type in %s operation_mode",
|
| 716 |
|
|
read_during_write_mode_port_a, intended_device_family, i_ram_block_type, operation_mode);
|
| 717 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 718 |
|
|
$finish;
|
| 719 |
|
|
end
|
| 720 |
|
|
|
| 721 |
|
|
if ((is_lutram != 1) && (i_ram_block_type != "AUTO") &&
|
| 722 |
|
|
(read_during_write_mode_mixed_ports == "NEW_DATA"))
|
| 723 |
|
|
begin
|
| 724 |
|
|
$display("Error: %s value for read_during_write_mode_mixed_ports is not supported in %s RAM block type", read_during_write_mode_mixed_ports, i_ram_block_type);
|
| 725 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 726 |
|
|
$finish;
|
| 727 |
|
|
end
|
| 728 |
|
|
|
| 729 |
|
|
if ((operation_mode == "DUAL_PORT") && (outdata_reg_b != "CLOCK0") && (is_lutram == 1) && (read_during_write_mode_mixed_ports == "OLD_DATA"))
|
| 730 |
|
|
begin
|
| 731 |
|
|
$display("Warning: Value for read_during_write_mode_mixed_ports of instance is not honoured in DUAL PORT operation mode when output registers are not clocked by clock0 for LUTRAM.");
|
| 732 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 733 |
|
|
end
|
| 734 |
|
|
|
| 735 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 736 |
|
|
&& ((indata_aclr_a != "NONE") && (indata_aclr_a != "UNUSED")))
|
| 737 |
|
|
begin
|
| 738 |
|
|
$display("Warning: %s value for indata_aclr_a is not supported in %s device family. The aclr to data_a registers will be ignored.", indata_aclr_a, intended_device_family);
|
| 739 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 740 |
|
|
end
|
| 741 |
|
|
|
| 742 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 743 |
|
|
&& ((wrcontrol_aclr_a != "NONE") && (wrcontrol_aclr_a != "UNUSED")))
|
| 744 |
|
|
begin
|
| 745 |
|
|
$display("Warning: %s value for wrcontrol_aclr_a is not supported in %s device family. The aclr to write control registers of port A will be ignored.", wrcontrol_aclr_a, intended_device_family);
|
| 746 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 747 |
|
|
end
|
| 748 |
|
|
|
| 749 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 750 |
|
|
&& ((byteena_aclr_a != "NONE") && (byteena_aclr_a != "UNUSED")))
|
| 751 |
|
|
begin
|
| 752 |
|
|
$display("Warning: %s value for byteena_aclr_a is not supported in %s device family. The aclr to byteena_a registers will be ignored.", byteena_aclr_a, intended_device_family);
|
| 753 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 754 |
|
|
end
|
| 755 |
|
|
|
| 756 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 757 |
|
|
&& ((address_aclr_a != "NONE") && (address_aclr_a != "UNUSED")) && (operation_mode != "ROM"))
|
| 758 |
|
|
begin
|
| 759 |
|
|
$display("Warning: %s value for address_aclr_a is not supported for write port in %s device family. The aclr to address_a registers will be ignored.", byteena_aclr_a, intended_device_family);
|
| 760 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 761 |
|
|
end
|
| 762 |
|
|
|
| 763 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 764 |
|
|
&& ((indata_aclr_b != "NONE") && (indata_aclr_b != "UNUSED")))
|
| 765 |
|
|
begin
|
| 766 |
|
|
$display("Warning: %s value for indata_aclr_b is not supported in %s device family. The aclr to data_b registers will be ignored.", indata_aclr_b, intended_device_family);
|
| 767 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 768 |
|
|
end
|
| 769 |
|
|
|
| 770 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 771 |
|
|
&& ((rdcontrol_aclr_b != "NONE") && (rdcontrol_aclr_b != "UNUSED")))
|
| 772 |
|
|
begin
|
| 773 |
|
|
$display("Warning: %s value for rdcontrol_aclr_b is not supported in %s device family. The aclr to read control registers will be ignored.", rdcontrol_aclr_b, intended_device_family);
|
| 774 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 775 |
|
|
end
|
| 776 |
|
|
|
| 777 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 778 |
|
|
&& ((wrcontrol_aclr_b != "NONE") && (wrcontrol_aclr_b != "UNUSED")))
|
| 779 |
|
|
begin
|
| 780 |
|
|
$display("Warning: %s value for wrcontrol_aclr_b is not supported in %s device family. The aclr to write control registers will be ignored.", wrcontrol_aclr_b, intended_device_family);
|
| 781 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 782 |
|
|
end
|
| 783 |
|
|
|
| 784 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 785 |
|
|
&& ((byteena_aclr_b != "NONE") && (byteena_aclr_b != "UNUSED")))
|
| 786 |
|
|
begin
|
| 787 |
|
|
$display("Warning: %s value for byteena_aclr_b is not supported in %s device family. The aclr to byteena_a register will be ignored.", byteena_aclr_b, intended_device_family);
|
| 788 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 789 |
|
|
end
|
| 790 |
|
|
|
| 791 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 792 |
|
|
&& ((address_aclr_b != "NONE") && (address_aclr_b != "UNUSED")) && (operation_mode == "BIDIR_DUAL_PORT"))
|
| 793 |
|
|
begin
|
| 794 |
|
|
$display("Warning: %s value for address_aclr_b is not supported for write port in %s device family. The aclr to address_b registers will be ignored.", address_aclr_b, intended_device_family);
|
| 795 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 796 |
|
|
end
|
| 797 |
|
|
|
| 798 |
|
|
if ((is_lutram == 1) && (read_during_write_mode_mixed_ports == "OLD_DATA")
|
| 799 |
|
|
&& ((address_aclr_b != "NONE") && (address_aclr_b != "UNUSED")) && (operation_mode == "DUAL_PORT"))
|
| 800 |
|
|
begin
|
| 801 |
|
|
$display("Warning : aclr signal for address_b is ignored for RAM block type %s when read_during_write_mode_mixed_ports is set to OLD_DATA", ram_block_type);
|
| 802 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 803 |
|
|
end
|
| 804 |
|
|
|
| 805 |
|
|
if (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1))
|
| 806 |
|
|
&& ((clock_enable_core_a != clock_enable_input_a) && (clock_enable_core_a != "USE_INPUT_CLKEN")))
|
| 807 |
|
|
begin
|
| 808 |
|
|
$display("Warning: clock_enable_core_a value must be USE_INPUT_CLKEN or same as clock_enable_input_a in %s device family. It will be set to clock_enable_input_a value.", intended_device_family);
|
| 809 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 810 |
|
|
end
|
| 811 |
|
|
|
| 812 |
|
|
if (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1))
|
| 813 |
|
|
&& ((clock_enable_core_b != clock_enable_input_b) && (clock_enable_core_b != "USE_INPUT_CLKEN")))
|
| 814 |
|
|
begin
|
| 815 |
|
|
$display("Warning: clock_enable_core_b must be USE_INPUT_CLKEN or same as clock_enable_input_b in %s device family. It will be set to clock_enable_input_b value.", intended_device_family);
|
| 816 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 817 |
|
|
end
|
| 818 |
|
|
|
| 819 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
|
| 820 |
|
|
&& (clock_enable_input_a == "ALTERNATE"))
|
| 821 |
|
|
begin
|
| 822 |
|
|
$display("Error: %s value for clock_enable_input_a is not supported in %s device family.", clock_enable_input_a, intended_device_family);
|
| 823 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 824 |
|
|
$finish;
|
| 825 |
|
|
end
|
| 826 |
|
|
|
| 827 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
|
| 828 |
|
|
&& (clock_enable_input_b == "ALTERNATE"))
|
| 829 |
|
|
begin
|
| 830 |
|
|
$display("Error: %s value for clock_enable_input_b is not supported in %s device family.", clock_enable_input_b, intended_device_family);
|
| 831 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 832 |
|
|
$finish;
|
| 833 |
|
|
end
|
| 834 |
|
|
|
| 835 |
|
|
if ((i_ram_block_type != "M144K") && ((enable_ecc != "FALSE") && (enable_ecc != "NONE")) && (operation_mode != "DUAL_PORT"))
|
| 836 |
|
|
begin
|
| 837 |
|
|
$display("Warning: %s value for enable_ecc is not supported in %s ram block type for %s device family in %s operation mode", enable_ecc, i_ram_block_type, intended_device_family, operation_mode);
|
| 838 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 839 |
|
|
end
|
| 840 |
|
|
|
| 841 |
|
|
if ((i_ram_block_type == "M144K") && (enable_ecc == "TRUE") && (read_during_write_mode_mixed_ports == "OLD_DATA"))
|
| 842 |
|
|
begin
|
| 843 |
|
|
$display("Error : ECC is not supported for read-before-write mode.");
|
| 844 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 845 |
|
|
$finish;
|
| 846 |
|
|
end
|
| 847 |
|
|
|
| 848 |
|
|
if (operation_mode != "DUAL_PORT")
|
| 849 |
|
|
begin
|
| 850 |
|
|
if ((outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1") && (outdata_reg_a != "UNUSED") && (outdata_reg_a != "UNREGISTERED"))
|
| 851 |
|
|
begin
|
| 852 |
|
|
$display("Error: %s value for outdata_reg_a is not supported.", outdata_reg_a);
|
| 853 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 854 |
|
|
$finish;
|
| 855 |
|
|
end
|
| 856 |
|
|
end
|
| 857 |
|
|
|
| 858 |
|
|
if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "DUAL_PORT"))
|
| 859 |
|
|
begin
|
| 860 |
|
|
if ((address_reg_b != "CLOCK0") && (address_reg_b != "CLOCK1") && (address_reg_b != "UNUSED"))
|
| 861 |
|
|
begin
|
| 862 |
|
|
$display("Error: %s value for address_reg_b is not supported.", address_reg_b);
|
| 863 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 864 |
|
|
$finish;
|
| 865 |
|
|
end
|
| 866 |
|
|
|
| 867 |
|
|
if ((outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1") && (outdata_reg_b != "UNUSED") && (outdata_reg_b != "UNREGISTERED"))
|
| 868 |
|
|
begin
|
| 869 |
|
|
$display("Error: %s value for outdata_reg_b is not supported.", outdata_reg_b);
|
| 870 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 871 |
|
|
$finish;
|
| 872 |
|
|
end
|
| 873 |
|
|
|
| 874 |
|
|
if ((rdcontrol_reg_b != "CLOCK0") && (rdcontrol_reg_b != "CLOCK1") && (rdcontrol_reg_b != "UNUSED") && (operation_mode == "DUAL_PORT"))
|
| 875 |
|
|
begin
|
| 876 |
|
|
$display("Error: %s value for rdcontrol_reg_b is not supported.", rdcontrol_reg_b);
|
| 877 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 878 |
|
|
$finish;
|
| 879 |
|
|
end
|
| 880 |
|
|
|
| 881 |
|
|
if ((indata_reg_b != "CLOCK0") && (indata_reg_b != "CLOCK1") && (indata_reg_b != "UNUSED") && (operation_mode == "BIDIR_DUAL_PORT"))
|
| 882 |
|
|
begin
|
| 883 |
|
|
$display("Error: %s value for indata_reg_b is not supported.", indata_reg_b);
|
| 884 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 885 |
|
|
$finish;
|
| 886 |
|
|
end
|
| 887 |
|
|
|
| 888 |
|
|
if ((wrcontrol_wraddress_reg_b != "CLOCK0") && (wrcontrol_wraddress_reg_b != "CLOCK1") && (wrcontrol_wraddress_reg_b != "UNUSED") && (operation_mode == "BIDIR_DUAL_PORT"))
|
| 889 |
|
|
begin
|
| 890 |
|
|
$display("Error: %s value for wrcontrol_wraddress_reg_b is not supported.", wrcontrol_wraddress_reg_b);
|
| 891 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 892 |
|
|
$finish;
|
| 893 |
|
|
end
|
| 894 |
|
|
|
| 895 |
|
|
if ((byteena_reg_b != "CLOCK0") && (byteena_reg_b != "CLOCK1") && (byteena_reg_b != "UNUSED") && (operation_mode == "BIDIR_DUAL_PORT"))
|
| 896 |
|
|
begin
|
| 897 |
|
|
$display("Error: %s value for byteena_reg_b is not supported.", byteena_reg_b);
|
| 898 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 899 |
|
|
$finish;
|
| 900 |
|
|
end
|
| 901 |
|
|
end
|
| 902 |
|
|
|
| 903 |
|
|
// *****************************************
|
| 904 |
|
|
// legal operations for all operation modes:
|
| 905 |
|
|
// | PORT A | PORT B |
|
| 906 |
|
|
// | RD WR | RD WR |
|
| 907 |
|
|
// BDP | x x | x x |
|
| 908 |
|
|
// DP | x | x |
|
| 909 |
|
|
// SP | x x | |
|
| 910 |
|
|
// ROM | x | |
|
| 911 |
|
|
// *****************************************
|
| 912 |
|
|
|
| 913 |
|
|
|
| 914 |
|
|
// Initialize mem_data
|
| 915 |
|
|
|
| 916 |
|
|
if ((init_file == "UNUSED") || (init_file == ""))
|
| 917 |
|
|
begin
|
| 918 |
|
|
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (power_up_uninitialized != "TRUE"))
|
| 919 |
|
|
begin
|
| 920 |
|
|
wa_mult_x = {width_a{1'b0}};
|
| 921 |
|
|
for (i = 0; i < (1 << widthad_a); i = i + 1)
|
| 922 |
|
|
mem_data[i] = wa_mult_x;
|
| 923 |
|
|
|
| 924 |
|
|
if (enable_mem_data_b_reading)
|
| 925 |
|
|
begin
|
| 926 |
|
|
for (i = 0; i < (1 << widthad_b); i = i + 1)
|
| 927 |
|
|
mem_data_b[i] = {width_b{1'b0}};
|
| 928 |
|
|
end
|
| 929 |
|
|
|
| 930 |
|
|
end
|
| 931 |
|
|
else if (((i_ram_block_type == "M-RAM") ||
|
| 932 |
|
|
(i_ram_block_type == "MEGARAM") ||
|
| 933 |
|
|
((i_ram_block_type == "AUTO") && (cread_during_write_mode_mixed_ports == "DONT_CARE")) ||
|
| 934 |
|
|
(dev.FEATURE_FAMILY_STRATIX_HC(intended_device_family) == 1) ||
|
| 935 |
|
|
(dev.FEATURE_FAMILY_HARDCOPYII(intended_device_family) == 1) ||
|
| 936 |
|
|
(power_up_uninitialized == "TRUE") ) && (implement_in_les == "OFF"))
|
| 937 |
|
|
begin
|
| 938 |
|
|
wa_mult_x = {width_a{1'bx}};
|
| 939 |
|
|
for (i = 0; i < (1 << widthad_a); i = i + 1)
|
| 940 |
|
|
mem_data[i] = wa_mult_x;
|
| 941 |
|
|
|
| 942 |
|
|
if (enable_mem_data_b_reading)
|
| 943 |
|
|
begin
|
| 944 |
|
|
for (i = 0; i < (1 << widthad_b); i = i + 1)
|
| 945 |
|
|
mem_data_b[i] = {width_b{1'bx}};
|
| 946 |
|
|
end
|
| 947 |
|
|
end
|
| 948 |
|
|
else
|
| 949 |
|
|
begin
|
| 950 |
|
|
wa_mult_x = {width_a{1'b0}};
|
| 951 |
|
|
for (i = 0; i < (1 << widthad_a); i = i + 1)
|
| 952 |
|
|
mem_data[i] = wa_mult_x;
|
| 953 |
|
|
|
| 954 |
|
|
if (enable_mem_data_b_reading)
|
| 955 |
|
|
begin
|
| 956 |
|
|
for (i = 0; i < (1 << widthad_b); i = i + 1)
|
| 957 |
|
|
mem_data_b[i] = {width_b{1'b0}};
|
| 958 |
|
|
end
|
| 959 |
|
|
end
|
| 960 |
|
|
end
|
| 961 |
|
|
|
| 962 |
|
|
else // Memory initialization file is used
|
| 963 |
|
|
begin
|
| 964 |
|
|
|
| 965 |
|
|
wa_mult_x = {width_a{1'b0}};
|
| 966 |
|
|
for (i = 0; i < (1 << widthad_a); i = i + 1)
|
| 967 |
|
|
mem_data[i] = wa_mult_x;
|
| 968 |
|
|
|
| 969 |
|
|
for (i = 0; i < (1 << widthad_b); i = i + 1)
|
| 970 |
|
|
mem_data_b[i] = {width_b{1'b0}};
|
| 971 |
|
|
|
| 972 |
|
|
init_file_b_port = 0;
|
| 973 |
|
|
|
| 974 |
|
|
if ((init_file_layout != "PORT_A") &&
|
| 975 |
|
|
(init_file_layout != "PORT_B"))
|
| 976 |
|
|
begin
|
| 977 |
|
|
if (operation_mode == "DUAL_PORT")
|
| 978 |
|
|
init_file_b_port = 1;
|
| 979 |
|
|
else
|
| 980 |
|
|
init_file_b_port = 0;
|
| 981 |
|
|
end
|
| 982 |
|
|
else
|
| 983 |
|
|
begin
|
| 984 |
|
|
if (init_file_layout == "PORT_A")
|
| 985 |
|
|
init_file_b_port = 0;
|
| 986 |
|
|
else if (init_file_layout == "PORT_B")
|
| 987 |
|
|
init_file_b_port = 1;
|
| 988 |
|
|
end
|
| 989 |
|
|
|
| 990 |
|
|
if (init_file_b_port)
|
| 991 |
|
|
begin
|
| 992 |
|
|
`ifdef NO_PLI
|
| 993 |
|
|
$readmemh(init_file, mem_data_b);
|
| 994 |
|
|
`else
|
| 995 |
|
|
`ifdef USE_RIF
|
| 996 |
|
|
$readmemh(init_file, mem_data_b);
|
| 997 |
|
|
`else
|
| 998 |
|
|
mem.convert_to_ver_file(init_file, width_b, ram_initf);
|
| 999 |
|
|
$readmemh(ram_initf, mem_data_b);
|
| 1000 |
|
|
`endif
|
| 1001 |
|
|
`endif
|
| 1002 |
|
|
|
| 1003 |
|
|
for (i = 0; i < (i_numwords_b * width_b); i = i + 1)
|
| 1004 |
|
|
begin
|
| 1005 |
|
|
temp_wb = mem_data_b[i / width_b];
|
| 1006 |
|
|
i_div_wa = i / width_a;
|
| 1007 |
|
|
temp_wa = mem_data[i_div_wa];
|
| 1008 |
|
|
temp_wa[i % width_a] = temp_wb[i % width_b];
|
| 1009 |
|
|
mem_data[i_div_wa] = temp_wa;
|
| 1010 |
|
|
end
|
| 1011 |
|
|
end
|
| 1012 |
|
|
else
|
| 1013 |
|
|
begin
|
| 1014 |
|
|
`ifdef NO_PLI
|
| 1015 |
|
|
$readmemh(init_file, mem_data);
|
| 1016 |
|
|
`else
|
| 1017 |
|
|
`ifdef USE_RIF
|
| 1018 |
|
|
$readmemh(init_file, mem_data);
|
| 1019 |
|
|
`else
|
| 1020 |
|
|
mem.convert_to_ver_file(init_file, width_a, ram_initf);
|
| 1021 |
|
|
$readmemh(ram_initf, mem_data);
|
| 1022 |
|
|
`endif
|
| 1023 |
|
|
`endif
|
| 1024 |
|
|
|
| 1025 |
|
|
if (enable_mem_data_b_reading)
|
| 1026 |
|
|
begin
|
| 1027 |
|
|
for (i = 0; i < (i_numwords_a * width_a); i = i + 1)
|
| 1028 |
|
|
begin
|
| 1029 |
|
|
temp_wa = mem_data[i / width_a];
|
| 1030 |
|
|
i_div_wb = i / width_b;
|
| 1031 |
|
|
temp_wb = mem_data_b[i_div_wb];
|
| 1032 |
|
|
temp_wb[i % width_b] = temp_wa[i % width_a];
|
| 1033 |
|
|
mem_data_b[i_div_wb] = temp_wb;
|
| 1034 |
|
|
end
|
| 1035 |
|
|
end
|
| 1036 |
|
|
end
|
| 1037 |
|
|
end
|
| 1038 |
|
|
i_nmram_write_a = 0;
|
| 1039 |
|
|
i_nmram_write_b = 0;
|
| 1040 |
|
|
|
| 1041 |
|
|
i_aclr_flag_a = 0;
|
| 1042 |
|
|
i_aclr_flag_b = 0;
|
| 1043 |
|
|
|
| 1044 |
|
|
i_outdata_aclr_a_prev = 0;
|
| 1045 |
|
|
i_outdata_aclr_b_prev = 0;
|
| 1046 |
|
|
i_address_aclr_a_prev = 0;
|
| 1047 |
|
|
i_address_aclr_b_prev = 0;
|
| 1048 |
|
|
|
| 1049 |
|
|
i_force_reread_a = 0;
|
| 1050 |
|
|
i_force_reread_a1 = 0;
|
| 1051 |
|
|
i_force_reread_b = 0;
|
| 1052 |
|
|
i_force_reread_b1 = 0;
|
| 1053 |
|
|
i_force_reread_a_signal = 0;
|
| 1054 |
|
|
i_force_reread_b_signal = 0;
|
| 1055 |
|
|
|
| 1056 |
|
|
// Initialize internal registers/signals
|
| 1057 |
|
|
i_data_reg_a = 0;
|
| 1058 |
|
|
i_data_reg_b = 0;
|
| 1059 |
|
|
i_address_reg_a = 0;
|
| 1060 |
|
|
i_address_reg_b = 0;
|
| 1061 |
|
|
i_original_address_a = 0;
|
| 1062 |
|
|
i_wren_reg_a = 0;
|
| 1063 |
|
|
i_wren_reg_b = 0;
|
| 1064 |
|
|
i_read_flag_a = 0;
|
| 1065 |
|
|
i_read_flag_b = 0;
|
| 1066 |
|
|
i_write_flag_a = 0;
|
| 1067 |
|
|
i_write_flag_b = 0;
|
| 1068 |
|
|
i_byteena_mask_reg_a = {width_a{1'b1}};
|
| 1069 |
|
|
i_byteena_mask_reg_b = {width_b{1'b1}};
|
| 1070 |
|
|
i_byteena_mask_reg_a_x = 0;
|
| 1071 |
|
|
i_byteena_mask_reg_b_x = 0;
|
| 1072 |
|
|
i_byteena_mask_reg_a_out = {width_a{1'b1}};
|
| 1073 |
|
|
i_byteena_mask_reg_b_out = {width_b{1'b1}};
|
| 1074 |
|
|
i_original_data_b = 0;
|
| 1075 |
|
|
i_original_data_a = 0;
|
| 1076 |
|
|
i_data_write_time_a = 0;
|
| 1077 |
|
|
i_core_clocken_a_reg = 0;
|
| 1078 |
|
|
i_core_clocken0_b_reg = 0;
|
| 1079 |
|
|
i_core_clocken1_b_reg = 0;
|
| 1080 |
|
|
|
| 1081 |
|
|
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 1082 |
|
|
begin
|
| 1083 |
|
|
i_rden_reg_a = 0;
|
| 1084 |
|
|
i_rden_reg_b = 0;
|
| 1085 |
|
|
end
|
| 1086 |
|
|
else
|
| 1087 |
|
|
begin
|
| 1088 |
|
|
i_rden_reg_a = 1;
|
| 1089 |
|
|
i_rden_reg_b = 1;
|
| 1090 |
|
|
end
|
| 1091 |
|
|
|
| 1092 |
|
|
|
| 1093 |
|
|
|
| 1094 |
|
|
if (((i_ram_block_type == "M-RAM") ||
|
| 1095 |
|
|
(i_ram_block_type == "MEGARAM") ||
|
| 1096 |
|
|
((i_ram_block_type == "AUTO") && (cread_during_write_mode_mixed_ports == "DONT_CARE"))) &&
|
| 1097 |
|
|
dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
|
| 1098 |
|
|
begin
|
| 1099 |
|
|
i_q_tmp_a = {width_a{1'bx}};
|
| 1100 |
|
|
i_q_tmp_b = {width_b{1'bx}};
|
| 1101 |
|
|
i_q_tmp2_a = {width_a{1'bx}};
|
| 1102 |
|
|
i_q_tmp2_b = {width_b{1'bx}};
|
| 1103 |
|
|
i_q_reg_a = {width_a{1'bx}};
|
| 1104 |
|
|
i_q_reg_b = {width_b{1'bx}};
|
| 1105 |
|
|
end
|
| 1106 |
|
|
else
|
| 1107 |
|
|
begin
|
| 1108 |
|
|
if (is_lutram == 1)
|
| 1109 |
|
|
begin
|
| 1110 |
|
|
i_q_tmp_a = mem_data[0];
|
| 1111 |
|
|
i_q_tmp2_a = mem_data[0];
|
| 1112 |
|
|
|
| 1113 |
|
|
for (init_i = 0; init_i < width_b; init_i = init_i + 1)
|
| 1114 |
|
|
begin
|
| 1115 |
|
|
init_temp = mem_data[init_i / width_a];
|
| 1116 |
|
|
i_q_tmp_b[init_i] = init_temp[init_i % width_a];
|
| 1117 |
|
|
i_q_tmp2_b[init_i] = init_temp[init_i % width_a];
|
| 1118 |
|
|
end
|
| 1119 |
|
|
|
| 1120 |
|
|
i_q_reg_a = 0;
|
| 1121 |
|
|
i_q_reg_b = 0;
|
| 1122 |
|
|
i_q_output_latch = 0;
|
| 1123 |
|
|
end
|
| 1124 |
|
|
else
|
| 1125 |
|
|
begin
|
| 1126 |
|
|
i_q_tmp_a = 0;
|
| 1127 |
|
|
i_q_tmp_b = 0;
|
| 1128 |
|
|
i_q_tmp2_a = 0;
|
| 1129 |
|
|
i_q_tmp2_b = 0;
|
| 1130 |
|
|
i_q_reg_a = 0;
|
| 1131 |
|
|
i_q_reg_b = 0;
|
| 1132 |
|
|
end
|
| 1133 |
|
|
end
|
| 1134 |
|
|
|
| 1135 |
|
|
good_to_go_a = 0;
|
| 1136 |
|
|
good_to_go_b = 0;
|
| 1137 |
|
|
|
| 1138 |
|
|
same_clock_pulse0 = 1'b0;
|
| 1139 |
|
|
same_clock_pulse1 = 1'b0;
|
| 1140 |
|
|
|
| 1141 |
|
|
i_byteena_count = 0;
|
| 1142 |
|
|
|
| 1143 |
|
|
if (((dev.FEATURE_FAMILY_STRATIX_HC(intended_device_family) == 1) || (dev.FEATURE_FAMILY_HARDCOPYII(intended_device_family) == 1)) &&
|
| 1144 |
|
|
(ram_block_type == "M4K") && (operation_mode != "SINGLE_PORT"))
|
| 1145 |
|
|
begin
|
| 1146 |
|
|
i_good_to_write_a2 = 0;
|
| 1147 |
|
|
i_good_to_write_b2 = 0;
|
| 1148 |
|
|
end
|
| 1149 |
|
|
else
|
| 1150 |
|
|
begin
|
| 1151 |
|
|
i_good_to_write_a2 = 1;
|
| 1152 |
|
|
i_good_to_write_b2 = 1;
|
| 1153 |
|
|
end
|
| 1154 |
|
|
|
| 1155 |
|
|
end
|
| 1156 |
|
|
|
| 1157 |
|
|
|
| 1158 |
|
|
// SIGNAL ASSIGNMENT
|
| 1159 |
|
|
|
| 1160 |
|
|
// Clock signal assignment
|
| 1161 |
|
|
|
| 1162 |
|
|
// port a clock assignments:
|
| 1163 |
|
|
assign i_outdata_clk_a = (outdata_reg_a == "CLOCK1") ?
|
| 1164 |
|
|
clock1 : ((outdata_reg_a == "CLOCK0") ?
|
| 1165 |
|
|
clock0 : 1'b0);
|
| 1166 |
|
|
// port b clock assignments:
|
| 1167 |
|
|
assign i_outdata_clk_b = (outdata_reg_b == "CLOCK1") ?
|
| 1168 |
|
|
clock1 : ((outdata_reg_b == "CLOCK0") ?
|
| 1169 |
|
|
clock0 : 1'b0);
|
| 1170 |
|
|
|
| 1171 |
|
|
// Clock enable signal assignment
|
| 1172 |
|
|
|
| 1173 |
|
|
// port a clock enable assignments:
|
| 1174 |
|
|
assign i_outdata_clken_a = (clock_enable_output_a == "BYPASS") ?
|
| 1175 |
|
|
1'b1 : ((clock_enable_output_a == "ALTERNATE") && (outdata_reg_a == "CLOCK1")) ?
|
| 1176 |
|
|
clocken3 : ((clock_enable_output_a == "ALTERNATE") && (outdata_reg_a == "CLOCK0")) ?
|
| 1177 |
|
|
clocken2 : (outdata_reg_a == "CLOCK1") ?
|
| 1178 |
|
|
clocken1 : (outdata_reg_a == "CLOCK0") ?
|
| 1179 |
|
|
clocken0 : 1'b1;
|
| 1180 |
|
|
// port b clock enable assignments:
|
| 1181 |
|
|
assign i_outdata_clken_b = (clock_enable_output_b == "BYPASS") ?
|
| 1182 |
|
|
1'b1 : ((clock_enable_output_b == "ALTERNATE") && (outdata_reg_b == "CLOCK1")) ?
|
| 1183 |
|
|
clocken3 : ((clock_enable_output_b == "ALTERNATE") && (outdata_reg_b == "CLOCK0")) ?
|
| 1184 |
|
|
clocken2 : (outdata_reg_b == "CLOCK1") ?
|
| 1185 |
|
|
clocken1 : (outdata_reg_b == "CLOCK0") ?
|
| 1186 |
|
|
clocken0 : 1'b1;
|
| 1187 |
|
|
|
| 1188 |
|
|
|
| 1189 |
|
|
assign i_clocken0 = (clock_enable_input_a == "BYPASS") ?
|
| 1190 |
|
|
1'b1 : (clock_enable_input_a == "NORMAL") ?
|
| 1191 |
|
|
clocken0 : clocken2;
|
| 1192 |
|
|
|
| 1193 |
|
|
assign i_clocken0_b = (clock_enable_input_b == "BYPASS") ?
|
| 1194 |
|
|
1'b1 : (clock_enable_input_b == "NORMAL") ?
|
| 1195 |
|
|
clocken0 : clocken2;
|
| 1196 |
|
|
|
| 1197 |
|
|
assign i_clocken1_b = (clock_enable_input_b == "BYPASS") ?
|
| 1198 |
|
|
1'b1 : (clock_enable_input_b == "NORMAL") ?
|
| 1199 |
|
|
clocken1 : clocken3;
|
| 1200 |
|
|
|
| 1201 |
|
|
assign i_core_clocken_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)) ?
|
| 1202 |
|
|
i_clocken0 : ((clock_enable_core_a == "BYPASS") ?
|
| 1203 |
|
|
1'b1 : ((clock_enable_core_a == "USE_INPUT_CLKEN") ?
|
| 1204 |
|
|
i_clocken0 : ((clock_enable_core_a == "NORMAL") ?
|
| 1205 |
|
|
clocken0 : clocken2)));
|
| 1206 |
|
|
|
| 1207 |
|
|
assign i_core_clocken0_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)) ?
|
| 1208 |
|
|
i_clocken0_b : ((clock_enable_core_b == "BYPASS") ?
|
| 1209 |
|
|
1'b1 : ((clock_enable_core_b == "USE_INPUT_CLKEN") ?
|
| 1210 |
|
|
i_clocken0_b : ((clock_enable_core_b == "NORMAL") ?
|
| 1211 |
|
|
clocken0 : clocken2)));
|
| 1212 |
|
|
|
| 1213 |
|
|
assign i_core_clocken1_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)) ?
|
| 1214 |
|
|
i_clocken1_b : ((clock_enable_core_b == "BYPASS") ?
|
| 1215 |
|
|
1'b1 : ((clock_enable_core_b == "USE_INPUT_CLKEN") ?
|
| 1216 |
|
|
i_clocken1_b : ((clock_enable_core_b == "NORMAL") ?
|
| 1217 |
|
|
clocken1 : clocken3)));
|
| 1218 |
|
|
|
| 1219 |
|
|
assign i_core_clocken_b = (address_reg_b == "CLOCK0") ?
|
| 1220 |
|
|
i_core_clocken0_b : i_core_clocken1_b;
|
| 1221 |
|
|
|
| 1222 |
|
|
// Async clear signal assignment
|
| 1223 |
|
|
|
| 1224 |
|
|
// port a clear assigments:
|
| 1225 |
|
|
|
| 1226 |
|
|
assign i_indata_aclr_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1227 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
|
| 1228 |
|
|
1'b0 : ((indata_aclr_a == "CLEAR0") ? aclr0 : 1'b0);
|
| 1229 |
|
|
assign i_address_aclr_a = (address_aclr_a == "CLEAR0") ? aclr0 : 1'b0;
|
| 1230 |
|
|
assign i_wrcontrol_aclr_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1231 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1))?
|
| 1232 |
|
|
1'b0 : ((wrcontrol_aclr_a == "CLEAR0") ? aclr0 : 1'b0);
|
| 1233 |
|
|
assign i_byteena_aclr_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1234 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
|
| 1235 |
|
|
1'b0 : ((byteena_aclr_a == "CLEAR0") ?
|
| 1236 |
|
|
aclr0 : ((byteena_aclr_a == "CLEAR1") ?
|
| 1237 |
|
|
aclr1 : 1'b0));
|
| 1238 |
|
|
assign i_outdata_aclr_a = (outdata_aclr_a == "CLEAR0") ?
|
| 1239 |
|
|
aclr0 : ((outdata_aclr_a == "CLEAR1") ?
|
| 1240 |
|
|
aclr1 : 1'b0);
|
| 1241 |
|
|
// port b clear assignments:
|
| 1242 |
|
|
assign i_indata_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1243 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1))?
|
| 1244 |
|
|
1'b0 : ((indata_aclr_b == "CLEAR0") ?
|
| 1245 |
|
|
aclr0 : ((indata_aclr_b == "CLEAR1") ?
|
| 1246 |
|
|
aclr1 : 1'b0));
|
| 1247 |
|
|
assign i_address_aclr_b = (address_aclr_b == "CLEAR0") ?
|
| 1248 |
|
|
aclr0 : ((address_aclr_b == "CLEAR1") ?
|
| 1249 |
|
|
aclr1 : 1'b0);
|
| 1250 |
|
|
assign i_wrcontrol_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1251 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1))?
|
| 1252 |
|
|
1'b0 : ((wrcontrol_aclr_b == "CLEAR0") ?
|
| 1253 |
|
|
aclr0 : ((wrcontrol_aclr_b == "CLEAR1") ?
|
| 1254 |
|
|
aclr1 : 1'b0));
|
| 1255 |
|
|
assign i_rdcontrol_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1256 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
|
| 1257 |
|
|
1'b0 : ((rdcontrol_aclr_b == "CLEAR0") ?
|
| 1258 |
|
|
aclr0 : ((rdcontrol_aclr_b == "CLEAR1") ?
|
| 1259 |
|
|
aclr1 : 1'b0));
|
| 1260 |
|
|
assign i_byteena_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
|
| 1261 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
|
| 1262 |
|
|
1'b0 : ((byteena_aclr_b == "CLEAR0") ?
|
| 1263 |
|
|
aclr0 : ((byteena_aclr_b == "CLEAR1") ?
|
| 1264 |
|
|
aclr1 : 1'b0));
|
| 1265 |
|
|
assign i_outdata_aclr_b = (outdata_aclr_b == "CLEAR0") ?
|
| 1266 |
|
|
aclr0 : ((outdata_aclr_b == "CLEAR1") ?
|
| 1267 |
|
|
aclr1 : 1'b0);
|
| 1268 |
|
|
|
| 1269 |
|
|
assign i_byteena_a = byteena_a;
|
| 1270 |
|
|
assign i_byteena_b = byteena_b;
|
| 1271 |
|
|
|
| 1272 |
|
|
|
| 1273 |
|
|
// Ready to write setting
|
| 1274 |
|
|
|
| 1275 |
|
|
assign i_good_to_write_a = (((is_bidir_and_wrcontrol_addb_clk0 == 1) || (dual_port_addreg_b_clk0 == 1)) && (i_core_clocken0_b) && (~clock0)) ?
|
| 1276 |
|
|
1'b1 : (((is_bidir_and_wrcontrol_addb_clk1 == 1) || (dual_port_addreg_b_clk1 == 1)) && (i_core_clocken1_b) && (~clock1)) ?
|
| 1277 |
|
|
1'b1 : i_good_to_write_a2;
|
| 1278 |
|
|
|
| 1279 |
|
|
assign i_good_to_write_b = ((i_core_clocken0_b) && (~clock0)) ? 1'b1 : i_good_to_write_b2;
|
| 1280 |
|
|
|
| 1281 |
|
|
assign s3_address_aclr_a = ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) && (is_lutram != 1) && (outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1")) ?
|
| 1282 |
|
|
1'b1 : 1'b0;
|
| 1283 |
|
|
|
| 1284 |
|
|
assign s3_address_aclr_b = ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) && (is_lutram != 1) && (outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1")) ?
|
| 1285 |
|
|
1'b1 : 1'b0;
|
| 1286 |
|
|
|
| 1287 |
|
|
assign i_address_aclr_family_a = (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (operation_mode != "ROM")) ||
|
| 1288 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
|
| 1289 |
|
|
1'b1 : 1'b0;
|
| 1290 |
|
|
|
| 1291 |
|
|
assign i_address_aclr_family_b = (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (operation_mode != "DUAL_PORT")) ||
|
| 1292 |
|
|
((is_lutram == 1) && (operation_mode == "DUAL_PORT") && (read_during_write_mode_mixed_ports == "OLD_DATA")) ||
|
| 1293 |
|
|
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
|
| 1294 |
|
|
1'b1 : 1'b0;
|
| 1295 |
|
|
|
| 1296 |
|
|
always @(i_good_to_write_a)
|
| 1297 |
|
|
begin
|
| 1298 |
|
|
i_good_to_write_a2 = i_good_to_write_a;
|
| 1299 |
|
|
end
|
| 1300 |
|
|
|
| 1301 |
|
|
always @(i_good_to_write_b)
|
| 1302 |
|
|
begin
|
| 1303 |
|
|
i_good_to_write_b2 = i_good_to_write_b;
|
| 1304 |
|
|
end
|
| 1305 |
|
|
|
| 1306 |
|
|
|
| 1307 |
|
|
// Port A inputs registered : indata, address, byeteena, wren
|
| 1308 |
|
|
// Aclr status flags get updated here for M-RAM ram_block_type
|
| 1309 |
|
|
|
| 1310 |
|
|
always @(posedge clock0)
|
| 1311 |
|
|
begin
|
| 1312 |
|
|
|
| 1313 |
|
|
if (i_force_reread_a)
|
| 1314 |
|
|
begin
|
| 1315 |
|
|
i_force_reread_a_signal <= ~ i_force_reread_a_signal;
|
| 1316 |
|
|
i_force_reread_a <= 0;
|
| 1317 |
|
|
end
|
| 1318 |
|
|
|
| 1319 |
|
|
if (i_force_reread_b && ((is_bidir_and_wrcontrol_addb_clk0 == 1) || (dual_port_addreg_b_clk0 == 1)))
|
| 1320 |
|
|
begin
|
| 1321 |
|
|
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
|
| 1322 |
|
|
i_force_reread_b <= 0;
|
| 1323 |
|
|
end
|
| 1324 |
|
|
|
| 1325 |
|
|
if (clock1)
|
| 1326 |
|
|
same_clock_pulse0 <= 1'b1;
|
| 1327 |
|
|
else
|
| 1328 |
|
|
same_clock_pulse0 <= 1'b0;
|
| 1329 |
|
|
|
| 1330 |
|
|
if (i_address_aclr_a && (~i_address_aclr_family_a))
|
| 1331 |
|
|
i_address_reg_a <= 0;
|
| 1332 |
|
|
|
| 1333 |
|
|
i_core_clocken_a_reg <= i_core_clocken_a;
|
| 1334 |
|
|
i_core_clocken0_b_reg <= i_core_clocken0_b;
|
| 1335 |
|
|
|
| 1336 |
|
|
if (i_core_clocken_a)
|
| 1337 |
|
|
begin
|
| 1338 |
|
|
|
| 1339 |
|
|
if (i_force_reread_a1)
|
| 1340 |
|
|
begin
|
| 1341 |
|
|
i_force_reread_a_signal <= ~ i_force_reread_a_signal;
|
| 1342 |
|
|
i_force_reread_a1 <= 0;
|
| 1343 |
|
|
end
|
| 1344 |
|
|
i_read_flag_a <= ~ i_read_flag_a;
|
| 1345 |
|
|
if (i_force_reread_b1 && ((is_bidir_and_wrcontrol_addb_clk0 == 1) || (dual_port_addreg_b_clk0 == 1)))
|
| 1346 |
|
|
begin
|
| 1347 |
|
|
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
|
| 1348 |
|
|
i_force_reread_b1 <= 0;
|
| 1349 |
|
|
end
|
| 1350 |
|
|
if (is_write_positive_edge_reg)
|
| 1351 |
|
|
begin
|
| 1352 |
|
|
if (i_wren_reg_a || wren_a)
|
| 1353 |
|
|
begin
|
| 1354 |
|
|
i_write_flag_a <= ~ i_write_flag_a;
|
| 1355 |
|
|
end
|
| 1356 |
|
|
if (operation_mode != "ROM")
|
| 1357 |
|
|
i_nmram_write_a <= 1'b0;
|
| 1358 |
|
|
end
|
| 1359 |
|
|
else
|
| 1360 |
|
|
begin
|
| 1361 |
|
|
if (operation_mode != "ROM")
|
| 1362 |
|
|
i_nmram_write_a <= 1'b1;
|
| 1363 |
|
|
end
|
| 1364 |
|
|
|
| 1365 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) && (is_lutram != 1))
|
| 1366 |
|
|
begin
|
| 1367 |
|
|
good_to_go_a <= 1;
|
| 1368 |
|
|
|
| 1369 |
|
|
i_rden_reg_a <= rden_a;
|
| 1370 |
|
|
|
| 1371 |
|
|
if (i_wrcontrol_aclr_a)
|
| 1372 |
|
|
i_wren_reg_a <= 0;
|
| 1373 |
|
|
else
|
| 1374 |
|
|
begin
|
| 1375 |
|
|
i_wren_reg_a <= wren_a;
|
| 1376 |
|
|
end
|
| 1377 |
|
|
end
|
| 1378 |
|
|
end
|
| 1379 |
|
|
else
|
| 1380 |
|
|
i_nmram_write_a <= 1'b0;
|
| 1381 |
|
|
|
| 1382 |
|
|
if (i_core_clocken_b)
|
| 1383 |
|
|
i_address_aclr_b_flag <= 0;
|
| 1384 |
|
|
|
| 1385 |
|
|
if (is_lutram)
|
| 1386 |
|
|
begin
|
| 1387 |
|
|
if (i_wrcontrol_aclr_a)
|
| 1388 |
|
|
i_wren_reg_a <= 0;
|
| 1389 |
|
|
else if (i_core_clocken_a)
|
| 1390 |
|
|
begin
|
| 1391 |
|
|
i_wren_reg_a <= wren_a;
|
| 1392 |
|
|
end
|
| 1393 |
|
|
end
|
| 1394 |
|
|
|
| 1395 |
|
|
if ((clock_enable_input_a == "BYPASS") ||
|
| 1396 |
|
|
((clock_enable_input_a == "NORMAL") && clocken0) ||
|
| 1397 |
|
|
((clock_enable_input_a == "ALTERNATE") && clocken2))
|
| 1398 |
|
|
begin
|
| 1399 |
|
|
|
| 1400 |
|
|
// Port A inputs
|
| 1401 |
|
|
|
| 1402 |
|
|
if (i_indata_aclr_a)
|
| 1403 |
|
|
i_data_reg_a <= 0;
|
| 1404 |
|
|
else
|
| 1405 |
|
|
i_data_reg_a <= data_a;
|
| 1406 |
|
|
|
| 1407 |
|
|
if (i_address_aclr_a && (~i_address_aclr_family_a))
|
| 1408 |
|
|
i_address_reg_a <= 0;
|
| 1409 |
|
|
else if (!addressstall_a)
|
| 1410 |
|
|
i_address_reg_a <= address_a;
|
| 1411 |
|
|
|
| 1412 |
|
|
if (i_byteena_aclr_a)
|
| 1413 |
|
|
begin
|
| 1414 |
|
|
i_byteena_mask_reg_a <= {width_a{1'b1}};
|
| 1415 |
|
|
i_byteena_mask_reg_a_out <= 0;
|
| 1416 |
|
|
i_byteena_mask_reg_a_x <= 0;
|
| 1417 |
|
|
i_byteena_mask_reg_a_out_b <= {width_a{1'bx}};
|
| 1418 |
|
|
end
|
| 1419 |
|
|
else
|
| 1420 |
|
|
begin
|
| 1421 |
|
|
|
| 1422 |
|
|
if (width_byteena_a == 1)
|
| 1423 |
|
|
begin
|
| 1424 |
|
|
i_byteena_mask_reg_a <= {width_a{i_byteena_a[0]}};
|
| 1425 |
|
|
i_byteena_mask_reg_a_out <= (i_byteena_a[0])? {width_a{1'b0}} : {width_a{1'bx}};
|
| 1426 |
|
|
i_byteena_mask_reg_a_out_b <= (i_byteena_a[0])? {width_a{1'bx}} : {width_a{1'b0}};
|
| 1427 |
|
|
i_byteena_mask_reg_a_x <= ((i_byteena_a[0]) || (i_byteena_a[0] == 1'b0))? {width_a{1'b0}} : {width_a{1'bx}};
|
| 1428 |
|
|
end
|
| 1429 |
|
|
else
|
| 1430 |
|
|
for (k = 0; k < width_a; k = k+1)
|
| 1431 |
|
|
begin
|
| 1432 |
|
|
i_byteena_mask_reg_a[k] <= i_byteena_a[k/i_byte_size];
|
| 1433 |
|
|
i_byteena_mask_reg_a_out_b[k] <= (i_byteena_a[k/i_byte_size])? 1'bx: 1'b0;
|
| 1434 |
|
|
i_byteena_mask_reg_a_out[k] <= (i_byteena_a[k/i_byte_size])? 1'b0: 1'bx;
|
| 1435 |
|
|
i_byteena_mask_reg_a_x[k] <= ((i_byteena_a[k/i_byte_size]) || (i_byteena_a[k/i_byte_size] == 1'b0))? 1'b0: 1'bx;
|
| 1436 |
|
|
end
|
| 1437 |
|
|
|
| 1438 |
|
|
end
|
| 1439 |
|
|
|
| 1440 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0) ||
|
| 1441 |
|
|
(is_lutram == 1))
|
| 1442 |
|
|
begin
|
| 1443 |
|
|
good_to_go_a <= 1;
|
| 1444 |
|
|
|
| 1445 |
|
|
i_rden_reg_a <= rden_a;
|
| 1446 |
|
|
|
| 1447 |
|
|
if (i_wrcontrol_aclr_a)
|
| 1448 |
|
|
i_wren_reg_a <= 0;
|
| 1449 |
|
|
else
|
| 1450 |
|
|
begin
|
| 1451 |
|
|
i_wren_reg_a <= wren_a;
|
| 1452 |
|
|
end
|
| 1453 |
|
|
end
|
| 1454 |
|
|
|
| 1455 |
|
|
end
|
| 1456 |
|
|
|
| 1457 |
|
|
|
| 1458 |
|
|
if (i_indata_aclr_a)
|
| 1459 |
|
|
i_data_reg_a <= 0;
|
| 1460 |
|
|
|
| 1461 |
|
|
if (i_address_aclr_a && (~i_address_aclr_family_a))
|
| 1462 |
|
|
i_address_reg_a <= 0;
|
| 1463 |
|
|
|
| 1464 |
|
|
if (i_byteena_aclr_a)
|
| 1465 |
|
|
begin
|
| 1466 |
|
|
i_byteena_mask_reg_a <= {width_a{1'b1}};
|
| 1467 |
|
|
i_byteena_mask_reg_a_out <= 0;
|
| 1468 |
|
|
i_byteena_mask_reg_a_x <= 0;
|
| 1469 |
|
|
i_byteena_mask_reg_a_out_b <= {width_a{1'bx}};
|
| 1470 |
|
|
end
|
| 1471 |
|
|
|
| 1472 |
|
|
|
| 1473 |
|
|
// Port B
|
| 1474 |
|
|
|
| 1475 |
|
|
if (is_bidir_and_wrcontrol_addb_clk0)
|
| 1476 |
|
|
begin
|
| 1477 |
|
|
|
| 1478 |
|
|
if (i_core_clocken0_b)
|
| 1479 |
|
|
begin
|
| 1480 |
|
|
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1)
|
| 1481 |
|
|
begin
|
| 1482 |
|
|
good_to_go_b <= 1;
|
| 1483 |
|
|
|
| 1484 |
|
|
i_rden_reg_b <= rden_b;
|
| 1485 |
|
|
|
| 1486 |
|
|
if (i_wrcontrol_aclr_b)
|
| 1487 |
|
|
i_wren_reg_b <= 0;
|
| 1488 |
|
|
else
|
| 1489 |
|
|
begin
|
| 1490 |
|
|
i_wren_reg_b <= wren_b;
|
| 1491 |
|
|
end
|
| 1492 |
|
|
end
|
| 1493 |
|
|
|
| 1494 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1495 |
|
|
|
| 1496 |
|
|
if (is_write_positive_edge_reg)
|
| 1497 |
|
|
begin
|
| 1498 |
|
|
if (i_wren_reg_b || wren_b)
|
| 1499 |
|
|
begin
|
| 1500 |
|
|
i_write_flag_b <= ~ i_write_flag_b;
|
| 1501 |
|
|
end
|
| 1502 |
|
|
i_nmram_write_b <= 1'b0;
|
| 1503 |
|
|
end
|
| 1504 |
|
|
else
|
| 1505 |
|
|
i_nmram_write_b <= 1'b1;
|
| 1506 |
|
|
|
| 1507 |
|
|
end
|
| 1508 |
|
|
else
|
| 1509 |
|
|
i_nmram_write_b <= 1'b0;
|
| 1510 |
|
|
|
| 1511 |
|
|
|
| 1512 |
|
|
if ((clock_enable_input_b == "BYPASS") ||
|
| 1513 |
|
|
((clock_enable_input_b == "NORMAL") && clocken0) ||
|
| 1514 |
|
|
((clock_enable_input_b == "ALTERNATE") && clocken2))
|
| 1515 |
|
|
begin
|
| 1516 |
|
|
|
| 1517 |
|
|
// Port B inputs
|
| 1518 |
|
|
|
| 1519 |
|
|
if (i_indata_aclr_b)
|
| 1520 |
|
|
i_data_reg_b <= 0;
|
| 1521 |
|
|
else
|
| 1522 |
|
|
i_data_reg_b <= data_b;
|
| 1523 |
|
|
|
| 1524 |
|
|
|
| 1525 |
|
|
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0)
|
| 1526 |
|
|
begin
|
| 1527 |
|
|
good_to_go_b <= 1;
|
| 1528 |
|
|
|
| 1529 |
|
|
i_rden_reg_b <= rden_b;
|
| 1530 |
|
|
|
| 1531 |
|
|
if (i_wrcontrol_aclr_b)
|
| 1532 |
|
|
i_wren_reg_b <= 0;
|
| 1533 |
|
|
else
|
| 1534 |
|
|
begin
|
| 1535 |
|
|
i_wren_reg_b <= wren_b;
|
| 1536 |
|
|
end
|
| 1537 |
|
|
end
|
| 1538 |
|
|
|
| 1539 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1540 |
|
|
i_address_reg_b <= 0;
|
| 1541 |
|
|
else if (!addressstall_b)
|
| 1542 |
|
|
i_address_reg_b <= address_b;
|
| 1543 |
|
|
|
| 1544 |
|
|
if (i_byteena_aclr_b)
|
| 1545 |
|
|
begin
|
| 1546 |
|
|
i_byteena_mask_reg_b <= {width_b{1'b1}};
|
| 1547 |
|
|
i_byteena_mask_reg_b_out <= 0;
|
| 1548 |
|
|
i_byteena_mask_reg_b_x <= 0;
|
| 1549 |
|
|
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
|
| 1550 |
|
|
end
|
| 1551 |
|
|
else
|
| 1552 |
|
|
begin
|
| 1553 |
|
|
|
| 1554 |
|
|
if (width_byteena_b == 1)
|
| 1555 |
|
|
begin
|
| 1556 |
|
|
i_byteena_mask_reg_b <= {width_b{i_byteena_b[0]}};
|
| 1557 |
|
|
i_byteena_mask_reg_b_out_a <= (i_byteena_b[0])? {width_b{1'bx}} : {width_b{1'b0}};
|
| 1558 |
|
|
i_byteena_mask_reg_b_out <= (i_byteena_b[0])? {width_b{1'b0}} : {width_b{1'bx}};
|
| 1559 |
|
|
i_byteena_mask_reg_b_x <= ((i_byteena_b[0]) || (i_byteena_b[0] == 1'b0))? {width_b{1'b0}} : {width_b{1'bx}};
|
| 1560 |
|
|
end
|
| 1561 |
|
|
else
|
| 1562 |
|
|
for (k2 = 0; k2 < width_b; k2 = k2 + 1)
|
| 1563 |
|
|
begin
|
| 1564 |
|
|
i_byteena_mask_reg_b[k2] <= i_byteena_b[k2/i_byte_size];
|
| 1565 |
|
|
i_byteena_mask_reg_b_out_a[k2] <= (i_byteena_b[k2/i_byte_size])? 1'bx : 1'b0;
|
| 1566 |
|
|
i_byteena_mask_reg_b_out[k2] <= (i_byteena_b[k2/i_byte_size])? 1'b0 : 1'bx;
|
| 1567 |
|
|
i_byteena_mask_reg_b_x[k2] <= ((i_byteena_b[k2/i_byte_size]) || (i_byteena_b[k2/i_byte_size] == 1'b0))? 1'b0 : 1'bx;
|
| 1568 |
|
|
end
|
| 1569 |
|
|
|
| 1570 |
|
|
end
|
| 1571 |
|
|
|
| 1572 |
|
|
end
|
| 1573 |
|
|
|
| 1574 |
|
|
|
| 1575 |
|
|
if (i_indata_aclr_b)
|
| 1576 |
|
|
i_data_reg_b <= 0;
|
| 1577 |
|
|
|
| 1578 |
|
|
if (i_wrcontrol_aclr_b)
|
| 1579 |
|
|
i_wren_reg_b <= 0;
|
| 1580 |
|
|
|
| 1581 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1582 |
|
|
i_address_reg_b <= 0;
|
| 1583 |
|
|
|
| 1584 |
|
|
if (i_byteena_aclr_b)
|
| 1585 |
|
|
begin
|
| 1586 |
|
|
i_byteena_mask_reg_b <= {width_b{1'b1}};
|
| 1587 |
|
|
i_byteena_mask_reg_b_out <= 0;
|
| 1588 |
|
|
i_byteena_mask_reg_b_x <= 0;
|
| 1589 |
|
|
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
|
| 1590 |
|
|
end
|
| 1591 |
|
|
end
|
| 1592 |
|
|
|
| 1593 |
|
|
if (dual_port_addreg_b_clk0)
|
| 1594 |
|
|
begin
|
| 1595 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1596 |
|
|
i_address_reg_b <= 0;
|
| 1597 |
|
|
|
| 1598 |
|
|
if (i_core_clocken0_b)
|
| 1599 |
|
|
begin
|
| 1600 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) && !is_lutram)
|
| 1601 |
|
|
begin
|
| 1602 |
|
|
good_to_go_b <= 1;
|
| 1603 |
|
|
|
| 1604 |
|
|
if (i_rdcontrol_aclr_b)
|
| 1605 |
|
|
i_rden_reg_b <= 1'b1;
|
| 1606 |
|
|
else
|
| 1607 |
|
|
i_rden_reg_b <= rden_b;
|
| 1608 |
|
|
end
|
| 1609 |
|
|
|
| 1610 |
|
|
i_read_flag_b <= ~ i_read_flag_b;
|
| 1611 |
|
|
end
|
| 1612 |
|
|
|
| 1613 |
|
|
if ((clock_enable_input_b == "BYPASS") ||
|
| 1614 |
|
|
((clock_enable_input_b == "NORMAL") && clocken0) ||
|
| 1615 |
|
|
((clock_enable_input_b == "ALTERNATE") && clocken2))
|
| 1616 |
|
|
begin
|
| 1617 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0) || is_lutram)
|
| 1618 |
|
|
begin
|
| 1619 |
|
|
good_to_go_b <= 1;
|
| 1620 |
|
|
|
| 1621 |
|
|
if (i_rdcontrol_aclr_b)
|
| 1622 |
|
|
i_rden_reg_b <= 1'b1;
|
| 1623 |
|
|
else
|
| 1624 |
|
|
i_rden_reg_b <= rden_b;
|
| 1625 |
|
|
end
|
| 1626 |
|
|
|
| 1627 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1628 |
|
|
i_address_reg_b <= 0;
|
| 1629 |
|
|
else if (!addressstall_b)
|
| 1630 |
|
|
i_address_reg_b <= address_b;
|
| 1631 |
|
|
|
| 1632 |
|
|
end
|
| 1633 |
|
|
|
| 1634 |
|
|
|
| 1635 |
|
|
if (i_rdcontrol_aclr_b)
|
| 1636 |
|
|
i_rden_reg_b <= 1'b1;
|
| 1637 |
|
|
|
| 1638 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1639 |
|
|
i_address_reg_b <= 0;
|
| 1640 |
|
|
|
| 1641 |
|
|
end
|
| 1642 |
|
|
|
| 1643 |
|
|
end
|
| 1644 |
|
|
|
| 1645 |
|
|
|
| 1646 |
|
|
always @(negedge clock0)
|
| 1647 |
|
|
begin
|
| 1648 |
|
|
|
| 1649 |
|
|
if (clock1)
|
| 1650 |
|
|
same_clock_pulse0 <= 1'b0;
|
| 1651 |
|
|
|
| 1652 |
|
|
if (!is_write_positive_edge_reg)
|
| 1653 |
|
|
begin
|
| 1654 |
|
|
if (i_nmram_write_a == 1'b1)
|
| 1655 |
|
|
begin
|
| 1656 |
|
|
i_write_flag_a <= ~ i_write_flag_a;
|
| 1657 |
|
|
|
| 1658 |
|
|
if (is_lutram)
|
| 1659 |
|
|
i_read_flag_a <= ~i_read_flag_a;
|
| 1660 |
|
|
end
|
| 1661 |
|
|
|
| 1662 |
|
|
|
| 1663 |
|
|
if (is_bidir_and_wrcontrol_addb_clk0)
|
| 1664 |
|
|
begin
|
| 1665 |
|
|
if (i_nmram_write_b == 1'b1)
|
| 1666 |
|
|
i_write_flag_b <= ~ i_write_flag_b;
|
| 1667 |
|
|
end
|
| 1668 |
|
|
end
|
| 1669 |
|
|
|
| 1670 |
|
|
if (i_core_clocken0_b && i_lutram_dual_port_fast_read && (dual_port_addreg_b_clk0 == 1))
|
| 1671 |
|
|
begin
|
| 1672 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1673 |
|
|
end
|
| 1674 |
|
|
|
| 1675 |
|
|
end
|
| 1676 |
|
|
|
| 1677 |
|
|
|
| 1678 |
|
|
|
| 1679 |
|
|
always @(posedge clock1)
|
| 1680 |
|
|
begin
|
| 1681 |
|
|
i_core_clocken1_b_reg <= i_core_clocken1_b;
|
| 1682 |
|
|
|
| 1683 |
|
|
if (i_force_reread_b && ((is_bidir_and_wrcontrol_addb_clk1 == 1) || (dual_port_addreg_b_clk1 == 1)))
|
| 1684 |
|
|
begin
|
| 1685 |
|
|
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
|
| 1686 |
|
|
i_force_reread_b <= 0;
|
| 1687 |
|
|
end
|
| 1688 |
|
|
|
| 1689 |
|
|
if (clock0)
|
| 1690 |
|
|
same_clock_pulse1 <= 1'b1;
|
| 1691 |
|
|
else
|
| 1692 |
|
|
same_clock_pulse1 <= 1'b0;
|
| 1693 |
|
|
|
| 1694 |
|
|
if (i_core_clocken_b)
|
| 1695 |
|
|
i_address_aclr_b_flag <= 0;
|
| 1696 |
|
|
|
| 1697 |
|
|
if (is_bidir_and_wrcontrol_addb_clk1)
|
| 1698 |
|
|
begin
|
| 1699 |
|
|
|
| 1700 |
|
|
if (i_core_clocken1_b)
|
| 1701 |
|
|
begin
|
| 1702 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1703 |
|
|
|
| 1704 |
|
|
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1)
|
| 1705 |
|
|
begin
|
| 1706 |
|
|
good_to_go_b <= 1;
|
| 1707 |
|
|
|
| 1708 |
|
|
i_rden_reg_b <= rden_b;
|
| 1709 |
|
|
|
| 1710 |
|
|
if (i_wrcontrol_aclr_b)
|
| 1711 |
|
|
i_wren_reg_b <= 0;
|
| 1712 |
|
|
else
|
| 1713 |
|
|
begin
|
| 1714 |
|
|
i_wren_reg_b <= wren_b;
|
| 1715 |
|
|
end
|
| 1716 |
|
|
end
|
| 1717 |
|
|
|
| 1718 |
|
|
if (is_write_positive_edge_reg)
|
| 1719 |
|
|
begin
|
| 1720 |
|
|
if (i_wren_reg_b || wren_b)
|
| 1721 |
|
|
begin
|
| 1722 |
|
|
i_write_flag_b <= ~ i_write_flag_b;
|
| 1723 |
|
|
end
|
| 1724 |
|
|
i_nmram_write_b <= 1'b0;
|
| 1725 |
|
|
end
|
| 1726 |
|
|
else
|
| 1727 |
|
|
i_nmram_write_b <= 1'b1;
|
| 1728 |
|
|
end
|
| 1729 |
|
|
else
|
| 1730 |
|
|
i_nmram_write_b <= 1'b0;
|
| 1731 |
|
|
|
| 1732 |
|
|
|
| 1733 |
|
|
if ((clock_enable_input_b == "BYPASS") ||
|
| 1734 |
|
|
((clock_enable_input_b == "NORMAL") && clocken1) ||
|
| 1735 |
|
|
((clock_enable_input_b == "ALTERNATE") && clocken3))
|
| 1736 |
|
|
begin
|
| 1737 |
|
|
|
| 1738 |
|
|
// Port B inputs
|
| 1739 |
|
|
|
| 1740 |
|
|
if (address_reg_b == "CLOCK1")
|
| 1741 |
|
|
begin
|
| 1742 |
|
|
if (i_indata_aclr_b)
|
| 1743 |
|
|
i_data_reg_b <= 0;
|
| 1744 |
|
|
else
|
| 1745 |
|
|
i_data_reg_b <= data_b;
|
| 1746 |
|
|
end
|
| 1747 |
|
|
|
| 1748 |
|
|
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0)
|
| 1749 |
|
|
begin
|
| 1750 |
|
|
good_to_go_b <= 1;
|
| 1751 |
|
|
|
| 1752 |
|
|
i_rden_reg_b <= rden_b;
|
| 1753 |
|
|
|
| 1754 |
|
|
if (i_wrcontrol_aclr_b)
|
| 1755 |
|
|
i_wren_reg_b <= 0;
|
| 1756 |
|
|
else
|
| 1757 |
|
|
begin
|
| 1758 |
|
|
i_wren_reg_b <= wren_b;
|
| 1759 |
|
|
end
|
| 1760 |
|
|
end
|
| 1761 |
|
|
|
| 1762 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1763 |
|
|
i_address_reg_b <= 0;
|
| 1764 |
|
|
else if (!addressstall_b)
|
| 1765 |
|
|
i_address_reg_b <= address_b;
|
| 1766 |
|
|
|
| 1767 |
|
|
if (i_byteena_aclr_b)
|
| 1768 |
|
|
begin
|
| 1769 |
|
|
i_byteena_mask_reg_b <= {width_b{1'b1}};
|
| 1770 |
|
|
i_byteena_mask_reg_b_out <= 0;
|
| 1771 |
|
|
i_byteena_mask_reg_b_x <= 0;
|
| 1772 |
|
|
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
|
| 1773 |
|
|
end
|
| 1774 |
|
|
else
|
| 1775 |
|
|
begin
|
| 1776 |
|
|
if (width_byteena_b == 1)
|
| 1777 |
|
|
begin
|
| 1778 |
|
|
i_byteena_mask_reg_b <= {width_b{i_byteena_b[0]}};
|
| 1779 |
|
|
i_byteena_mask_reg_b_out_a <= (i_byteena_b[0])? {width_b{1'bx}} : {width_b{1'b0}};
|
| 1780 |
|
|
i_byteena_mask_reg_b_out <= (i_byteena_b[0])? {width_b{1'b0}} : {width_b{1'bx}};
|
| 1781 |
|
|
i_byteena_mask_reg_b_x <= ((i_byteena_b[0]) || (i_byteena_b[0] == 1'b0))? {width_b{1'b0}} : {width_b{1'bx}};
|
| 1782 |
|
|
end
|
| 1783 |
|
|
else
|
| 1784 |
|
|
for (k2 = 0; k2 < width_b; k2 = k2 + 1)
|
| 1785 |
|
|
begin
|
| 1786 |
|
|
i_byteena_mask_reg_b[k2] <= i_byteena_b[k2/i_byte_size];
|
| 1787 |
|
|
i_byteena_mask_reg_b_out_a[k2] <= (i_byteena_b[k2/i_byte_size])? 1'bx : 1'b0;
|
| 1788 |
|
|
i_byteena_mask_reg_b_out[k2] <= (i_byteena_b[k2/i_byte_size])? 1'b0 : 1'bx;
|
| 1789 |
|
|
i_byteena_mask_reg_b_x[k2] <= ((i_byteena_b[k2/i_byte_size]) || (i_byteena_b[k2/i_byte_size] == 1'b0))? 1'b0 : 1'bx;
|
| 1790 |
|
|
end
|
| 1791 |
|
|
|
| 1792 |
|
|
end
|
| 1793 |
|
|
|
| 1794 |
|
|
end
|
| 1795 |
|
|
|
| 1796 |
|
|
|
| 1797 |
|
|
if (i_indata_aclr_b)
|
| 1798 |
|
|
i_data_reg_b <= 0;
|
| 1799 |
|
|
|
| 1800 |
|
|
if (i_wrcontrol_aclr_b)
|
| 1801 |
|
|
i_wren_reg_b <= 0;
|
| 1802 |
|
|
|
| 1803 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1804 |
|
|
i_address_reg_b <= 0;
|
| 1805 |
|
|
|
| 1806 |
|
|
if (i_byteena_aclr_b)
|
| 1807 |
|
|
begin
|
| 1808 |
|
|
i_byteena_mask_reg_b <= {width_b{1'b1}};
|
| 1809 |
|
|
i_byteena_mask_reg_b_out <= 0;
|
| 1810 |
|
|
i_byteena_mask_reg_b_x <= 0;
|
| 1811 |
|
|
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
|
| 1812 |
|
|
end
|
| 1813 |
|
|
end
|
| 1814 |
|
|
|
| 1815 |
|
|
if (dual_port_addreg_b_clk1)
|
| 1816 |
|
|
begin
|
| 1817 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1818 |
|
|
i_address_reg_b <= 0;
|
| 1819 |
|
|
|
| 1820 |
|
|
if (i_core_clocken1_b)
|
| 1821 |
|
|
begin
|
| 1822 |
|
|
if (i_force_reread_b1)
|
| 1823 |
|
|
begin
|
| 1824 |
|
|
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
|
| 1825 |
|
|
i_force_reread_b1 <= 0;
|
| 1826 |
|
|
end
|
| 1827 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) && !is_lutram)
|
| 1828 |
|
|
begin
|
| 1829 |
|
|
good_to_go_b <= 1;
|
| 1830 |
|
|
|
| 1831 |
|
|
if (i_rdcontrol_aclr_b)
|
| 1832 |
|
|
begin
|
| 1833 |
|
|
i_rden_reg_b <= 1'b1;
|
| 1834 |
|
|
end
|
| 1835 |
|
|
else
|
| 1836 |
|
|
begin
|
| 1837 |
|
|
i_rden_reg_b <= rden_b;
|
| 1838 |
|
|
end
|
| 1839 |
|
|
end
|
| 1840 |
|
|
|
| 1841 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1842 |
|
|
end
|
| 1843 |
|
|
|
| 1844 |
|
|
if ((clock_enable_input_b == "BYPASS") ||
|
| 1845 |
|
|
((clock_enable_input_b == "NORMAL") && clocken1) ||
|
| 1846 |
|
|
((clock_enable_input_b == "ALTERNATE") && clocken3))
|
| 1847 |
|
|
begin
|
| 1848 |
|
|
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0) || is_lutram)
|
| 1849 |
|
|
begin
|
| 1850 |
|
|
good_to_go_b <= 1;
|
| 1851 |
|
|
|
| 1852 |
|
|
if (i_rdcontrol_aclr_b)
|
| 1853 |
|
|
begin
|
| 1854 |
|
|
i_rden_reg_b <= 1'b1;
|
| 1855 |
|
|
end
|
| 1856 |
|
|
else
|
| 1857 |
|
|
begin
|
| 1858 |
|
|
i_rden_reg_b <= rden_b;
|
| 1859 |
|
|
end
|
| 1860 |
|
|
end
|
| 1861 |
|
|
|
| 1862 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1863 |
|
|
i_address_reg_b <= 0;
|
| 1864 |
|
|
else if (!addressstall_b)
|
| 1865 |
|
|
i_address_reg_b <= address_b;
|
| 1866 |
|
|
|
| 1867 |
|
|
end
|
| 1868 |
|
|
|
| 1869 |
|
|
|
| 1870 |
|
|
if (i_rdcontrol_aclr_b)
|
| 1871 |
|
|
i_rden_reg_b <= 1'b1;
|
| 1872 |
|
|
|
| 1873 |
|
|
if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 1874 |
|
|
i_address_reg_b <= 0;
|
| 1875 |
|
|
|
| 1876 |
|
|
end
|
| 1877 |
|
|
|
| 1878 |
|
|
end
|
| 1879 |
|
|
|
| 1880 |
|
|
always @(negedge clock1)
|
| 1881 |
|
|
begin
|
| 1882 |
|
|
|
| 1883 |
|
|
if (clock0)
|
| 1884 |
|
|
same_clock_pulse1 <= 1'b0;
|
| 1885 |
|
|
|
| 1886 |
|
|
if (!is_write_positive_edge_reg)
|
| 1887 |
|
|
begin
|
| 1888 |
|
|
|
| 1889 |
|
|
if (is_bidir_and_wrcontrol_addb_clk1)
|
| 1890 |
|
|
begin
|
| 1891 |
|
|
if (i_nmram_write_b == 1'b1)
|
| 1892 |
|
|
i_write_flag_b <= ~ i_write_flag_b;
|
| 1893 |
|
|
end
|
| 1894 |
|
|
end
|
| 1895 |
|
|
|
| 1896 |
|
|
if (i_core_clocken1_b && i_lutram_dual_port_fast_read && (dual_port_addreg_b_clk1 ==1))
|
| 1897 |
|
|
begin
|
| 1898 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1899 |
|
|
end
|
| 1900 |
|
|
|
| 1901 |
|
|
end
|
| 1902 |
|
|
|
| 1903 |
|
|
always @(posedge i_address_aclr_b)
|
| 1904 |
|
|
begin
|
| 1905 |
|
|
if ((is_lutram == 1) && (operation_mode == "DUAL_PORT") && (~i_address_aclr_family_b))
|
| 1906 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1907 |
|
|
end
|
| 1908 |
|
|
|
| 1909 |
|
|
always @(posedge i_address_aclr_a)
|
| 1910 |
|
|
begin
|
| 1911 |
|
|
if ((is_lutram == 1) && (operation_mode == "ROM") && (~i_address_aclr_family_a))
|
| 1912 |
|
|
i_read_flag_a <= ~i_read_flag_a;
|
| 1913 |
|
|
end
|
| 1914 |
|
|
|
| 1915 |
|
|
always @(posedge i_outdata_aclr_a)
|
| 1916 |
|
|
begin
|
| 1917 |
|
|
if ((dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
|
| 1918 |
|
|
((outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1")))
|
| 1919 |
|
|
i_read_flag_a <= ~i_read_flag_a;
|
| 1920 |
|
|
end
|
| 1921 |
|
|
|
| 1922 |
|
|
always @(posedge i_outdata_aclr_b)
|
| 1923 |
|
|
begin
|
| 1924 |
|
|
if ((dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
|
| 1925 |
|
|
((outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1")))
|
| 1926 |
|
|
i_read_flag_b <= ~i_read_flag_b;
|
| 1927 |
|
|
end
|
| 1928 |
|
|
|
| 1929 |
|
|
// Port A writting -------------------------------------------------------------
|
| 1930 |
|
|
|
| 1931 |
|
|
always @(posedge i_write_flag_a or negedge i_write_flag_a)
|
| 1932 |
|
|
begin
|
| 1933 |
|
|
if ((operation_mode == "BIDIR_DUAL_PORT") ||
|
| 1934 |
|
|
(operation_mode == "DUAL_PORT") ||
|
| 1935 |
|
|
(operation_mode == "SINGLE_PORT"))
|
| 1936 |
|
|
begin
|
| 1937 |
|
|
|
| 1938 |
|
|
if ((i_wren_reg_a) && (i_good_to_write_a))
|
| 1939 |
|
|
begin
|
| 1940 |
|
|
i_aclr_flag_a = 0;
|
| 1941 |
|
|
|
| 1942 |
|
|
if (i_indata_aclr_a)
|
| 1943 |
|
|
begin
|
| 1944 |
|
|
if (i_data_reg_a != 0)
|
| 1945 |
|
|
begin
|
| 1946 |
|
|
mem_data[i_address_reg_a] = {width_a{1'bx}};
|
| 1947 |
|
|
|
| 1948 |
|
|
if (enable_mem_data_b_reading)
|
| 1949 |
|
|
begin
|
| 1950 |
|
|
j3 = i_address_reg_a * width_a;
|
| 1951 |
|
|
for (i5 = 0; i5 < width_a; i5 = i5+1)
|
| 1952 |
|
|
begin
|
| 1953 |
|
|
j3_plus_i5 = j3 + i5;
|
| 1954 |
|
|
temp_wb = mem_data_b[j3_plus_i5 / width_b];
|
| 1955 |
|
|
temp_wb[j3_plus_i5 % width_b] = {1'bx};
|
| 1956 |
|
|
mem_data_b[j3_plus_i5 / width_b] = temp_wb;
|
| 1957 |
|
|
end
|
| 1958 |
|
|
end
|
| 1959 |
|
|
i_aclr_flag_a = 1;
|
| 1960 |
|
|
end
|
| 1961 |
|
|
end
|
| 1962 |
|
|
else if (i_byteena_aclr_a)
|
| 1963 |
|
|
begin
|
| 1964 |
|
|
if (i_byteena_mask_reg_a != {width_a{1'b1}})
|
| 1965 |
|
|
begin
|
| 1966 |
|
|
mem_data[i_address_reg_a] = {width_a{1'bx}};
|
| 1967 |
|
|
|
| 1968 |
|
|
if (enable_mem_data_b_reading)
|
| 1969 |
|
|
begin
|
| 1970 |
|
|
j3 = i_address_reg_a * width_a;
|
| 1971 |
|
|
for (i5 = 0; i5 < width_a; i5 = i5+1)
|
| 1972 |
|
|
begin
|
| 1973 |
|
|
j3_plus_i5 = j3 + i5;
|
| 1974 |
|
|
temp_wb = mem_data_b[j3_plus_i5 / width_b];
|
| 1975 |
|
|
temp_wb[j3_plus_i5 % width_b] = {1'bx};
|
| 1976 |
|
|
mem_data_b[j3_plus_i5 / width_b] = temp_wb;
|
| 1977 |
|
|
end
|
| 1978 |
|
|
end
|
| 1979 |
|
|
i_aclr_flag_a = 1;
|
| 1980 |
|
|
end
|
| 1981 |
|
|
end
|
| 1982 |
|
|
else if (i_address_aclr_a && (~i_address_aclr_family_a))
|
| 1983 |
|
|
begin
|
| 1984 |
|
|
if (i_address_reg_a != 0)
|
| 1985 |
|
|
begin
|
| 1986 |
|
|
wa_mult_x_ii = {width_a{1'bx}};
|
| 1987 |
|
|
for (i4 = 0; i4 < i_numwords_a; i4 = i4 + 1)
|
| 1988 |
|
|
mem_data[i4] = wa_mult_x_ii;
|
| 1989 |
|
|
|
| 1990 |
|
|
if (enable_mem_data_b_reading)
|
| 1991 |
|
|
begin
|
| 1992 |
|
|
for (i4 = 0; i4 < i_numwords_b; i4 = i4 + 1)
|
| 1993 |
|
|
mem_data_b[i4] = {width_b{1'bx}};
|
| 1994 |
|
|
end
|
| 1995 |
|
|
|
| 1996 |
|
|
i_aclr_flag_a = 1;
|
| 1997 |
|
|
end
|
| 1998 |
|
|
end
|
| 1999 |
|
|
|
| 2000 |
|
|
if (i_aclr_flag_a == 0)
|
| 2001 |
|
|
begin
|
| 2002 |
|
|
i_original_data_a = mem_data[i_address_reg_a];
|
| 2003 |
|
|
i_original_address_a = i_address_reg_a;
|
| 2004 |
|
|
i_data_write_time_a = $time;
|
| 2005 |
|
|
temp_wa = mem_data[i_address_reg_a];
|
| 2006 |
|
|
|
| 2007 |
|
|
port_a_bit_count_low = i_address_reg_a * width_a;
|
| 2008 |
|
|
port_b_bit_count_low = i_address_reg_b * width_b;
|
| 2009 |
|
|
port_b_bit_count_high = port_b_bit_count_low + width_b;
|
| 2010 |
|
|
|
| 2011 |
|
|
for (i5 = 0; i5 < width_a; i5 = i5 + 1)
|
| 2012 |
|
|
begin
|
| 2013 |
|
|
i_byteena_count = port_a_bit_count_low % width_b;
|
| 2014 |
|
|
|
| 2015 |
|
|
if ((port_a_bit_count_low >= port_b_bit_count_low) && (port_a_bit_count_low < port_b_bit_count_high) &&
|
| 2016 |
|
|
((i_core_clocken0_b_reg && (is_bidir_and_wrcontrol_addb_clk0 == 1)) || (i_core_clocken1_b_reg && (is_bidir_and_wrcontrol_addb_clk1 == 1))) &&
|
| 2017 |
|
|
(i_wren_reg_b) && ((same_clock_pulse0 && same_clock_pulse1) || (address_reg_b == "CLOCK0")) &&
|
| 2018 |
|
|
(i_byteena_mask_reg_b[i_byteena_count]) && (i_byteena_mask_reg_a[i5]))
|
| 2019 |
|
|
temp_wa[i5] = {1'bx};
|
| 2020 |
|
|
else if (i_byteena_mask_reg_a[i5])
|
| 2021 |
|
|
temp_wa[i5] = i_data_reg_a[i5];
|
| 2022 |
|
|
|
| 2023 |
|
|
if (enable_mem_data_b_reading)
|
| 2024 |
|
|
begin
|
| 2025 |
|
|
temp_wb = mem_data_b[port_a_bit_count_low / width_b];
|
| 2026 |
|
|
temp_wb[port_a_bit_count_low % width_b] = temp_wa[i5];
|
| 2027 |
|
|
mem_data_b[port_a_bit_count_low / width_b] = temp_wb;
|
| 2028 |
|
|
end
|
| 2029 |
|
|
|
| 2030 |
|
|
port_a_bit_count_low = port_a_bit_count_low + 1;
|
| 2031 |
|
|
end
|
| 2032 |
|
|
|
| 2033 |
|
|
mem_data[i_address_reg_a] = temp_wa;
|
| 2034 |
|
|
|
| 2035 |
|
|
if (((cread_during_write_mode_mixed_ports == "OLD_DATA") && (is_write_positive_edge_reg) && (address_reg_b == "CLOCK0")) ||
|
| 2036 |
|
|
((i_lutram_dual_port_fast_read == 1) && (operation_mode == "DUAL_PORT")))
|
| 2037 |
|
|
i_read_flag_b = ~i_read_flag_b;
|
| 2038 |
|
|
|
| 2039 |
|
|
if ((read_during_write_mode_port_a == "OLD_DATA") ||
|
| 2040 |
|
|
((is_lutram == 1) && (read_during_write_mode_port_a == "DONT_CARE")))
|
| 2041 |
|
|
i_read_flag_a = ~i_read_flag_a;
|
| 2042 |
|
|
end
|
| 2043 |
|
|
|
| 2044 |
|
|
end
|
| 2045 |
|
|
end
|
| 2046 |
|
|
end // Port A writting ----------------------------------------------------
|
| 2047 |
|
|
|
| 2048 |
|
|
|
| 2049 |
|
|
// Port B writting -----------------------------------------------------------
|
| 2050 |
|
|
|
| 2051 |
|
|
always @(posedge i_write_flag_b or negedge i_write_flag_b)
|
| 2052 |
|
|
begin
|
| 2053 |
|
|
if (operation_mode == "BIDIR_DUAL_PORT")
|
| 2054 |
|
|
begin
|
| 2055 |
|
|
|
| 2056 |
|
|
if ((i_wren_reg_b) && (i_good_to_write_b))
|
| 2057 |
|
|
begin
|
| 2058 |
|
|
|
| 2059 |
|
|
i_aclr_flag_b = 0;
|
| 2060 |
|
|
|
| 2061 |
|
|
// RAM content is following width_a
|
| 2062 |
|
|
// if Port B is of different width, need to make some adjustments
|
| 2063 |
|
|
|
| 2064 |
|
|
if (i_indata_aclr_b)
|
| 2065 |
|
|
begin
|
| 2066 |
|
|
if (i_data_reg_b != 0)
|
| 2067 |
|
|
begin
|
| 2068 |
|
|
if (enable_mem_data_b_reading)
|
| 2069 |
|
|
mem_data_b[i_address_reg_b] = {width_b{1'bx}};
|
| 2070 |
|
|
|
| 2071 |
|
|
if (width_a == width_b)
|
| 2072 |
|
|
mem_data[i_address_reg_b] = {width_b{1'bx}};
|
| 2073 |
|
|
else
|
| 2074 |
|
|
begin
|
| 2075 |
|
|
j = i_address_reg_b * width_b;
|
| 2076 |
|
|
for (i2 = 0; i2 < width_b; i2 = i2+1)
|
| 2077 |
|
|
begin
|
| 2078 |
|
|
j_plus_i2 = j + i2;
|
| 2079 |
|
|
temp_wa = mem_data[j_plus_i2 / width_a];
|
| 2080 |
|
|
temp_wa[j_plus_i2 % width_a] = {1'bx};
|
| 2081 |
|
|
mem_data[j_plus_i2 / width_a] = temp_wa;
|
| 2082 |
|
|
end
|
| 2083 |
|
|
end
|
| 2084 |
|
|
i_aclr_flag_b = 1;
|
| 2085 |
|
|
end
|
| 2086 |
|
|
end
|
| 2087 |
|
|
else if (i_byteena_aclr_b)
|
| 2088 |
|
|
begin
|
| 2089 |
|
|
if (i_byteena_mask_reg_b != {width_b{1'b1}})
|
| 2090 |
|
|
begin
|
| 2091 |
|
|
if (enable_mem_data_b_reading)
|
| 2092 |
|
|
mem_data_b[i_address_reg_b] = {width_b{1'bx}};
|
| 2093 |
|
|
|
| 2094 |
|
|
if (width_a == width_b)
|
| 2095 |
|
|
mem_data[i_address_reg_b] = {width_b{1'bx}};
|
| 2096 |
|
|
else
|
| 2097 |
|
|
begin
|
| 2098 |
|
|
j = i_address_reg_b * width_b;
|
| 2099 |
|
|
for (i2 = 0; i2 < width_b; i2 = i2+1)
|
| 2100 |
|
|
begin
|
| 2101 |
|
|
j_plus_i2 = j + i2;
|
| 2102 |
|
|
j_plus_i2_div_a = j_plus_i2 / width_a;
|
| 2103 |
|
|
temp_wa = mem_data[j_plus_i2_div_a];
|
| 2104 |
|
|
temp_wa[j_plus_i2 % width_a] = {1'bx};
|
| 2105 |
|
|
mem_data[j_plus_i2_div_a] = temp_wa;
|
| 2106 |
|
|
end
|
| 2107 |
|
|
end
|
| 2108 |
|
|
i_aclr_flag_b = 1;
|
| 2109 |
|
|
end
|
| 2110 |
|
|
end
|
| 2111 |
|
|
else if (i_address_aclr_b && (~i_address_aclr_family_b))
|
| 2112 |
|
|
begin
|
| 2113 |
|
|
if (i_address_reg_b != 0)
|
| 2114 |
|
|
begin
|
| 2115 |
|
|
|
| 2116 |
|
|
if (enable_mem_data_b_reading)
|
| 2117 |
|
|
begin
|
| 2118 |
|
|
for (i2 = 0; i2 < i_numwords_b; i2 = i2 + 1)
|
| 2119 |
|
|
begin
|
| 2120 |
|
|
mem_data_b[i2] = {width_b{1'bx}};
|
| 2121 |
|
|
end
|
| 2122 |
|
|
end
|
| 2123 |
|
|
|
| 2124 |
|
|
wa_mult_x_iii = {width_a{1'bx}};
|
| 2125 |
|
|
for (i2 = 0; i2 < i_numwords_a; i2 = i2 + 1)
|
| 2126 |
|
|
begin
|
| 2127 |
|
|
mem_data[i2] = wa_mult_x_iii;
|
| 2128 |
|
|
end
|
| 2129 |
|
|
i_aclr_flag_b = 1;
|
| 2130 |
|
|
end
|
| 2131 |
|
|
end
|
| 2132 |
|
|
|
| 2133 |
|
|
if (i_aclr_flag_b == 0)
|
| 2134 |
|
|
begin
|
| 2135 |
|
|
port_b_bit_count_low = i_address_reg_b * width_b;
|
| 2136 |
|
|
port_a_bit_count_low = i_address_reg_a * width_a;
|
| 2137 |
|
|
port_a_bit_count_high = port_a_bit_count_low + width_a;
|
| 2138 |
|
|
|
| 2139 |
|
|
for (i2 = 0; i2 < width_b; i2 = i2 + 1)
|
| 2140 |
|
|
begin
|
| 2141 |
|
|
port_b_bit_count_high = port_b_bit_count_low + i2;
|
| 2142 |
|
|
temp_wa = mem_data[port_b_bit_count_high / width_a];
|
| 2143 |
|
|
i_original_data_b[i2] = temp_wa[port_b_bit_count_high % width_a];
|
| 2144 |
|
|
|
| 2145 |
|
|
if ((port_b_bit_count_high >= port_a_bit_count_low) && (port_b_bit_count_high < port_a_bit_count_high) &&
|
| 2146 |
|
|
((same_clock_pulse0 && same_clock_pulse1) || (address_reg_b == "CLOCK0")) &&
|
| 2147 |
|
|
(i_core_clocken_a_reg) && (i_wren_reg_a) &&
|
| 2148 |
|
|
(i_byteena_mask_reg_a[port_b_bit_count_high % width_a]) && (i_byteena_mask_reg_b[i2]))
|
| 2149 |
|
|
temp_wa[port_b_bit_count_high % width_a] = {1'bx};
|
| 2150 |
|
|
else if (i_byteena_mask_reg_b[i2])
|
| 2151 |
|
|
temp_wa[port_b_bit_count_high % width_a] = i_data_reg_b[i2];
|
| 2152 |
|
|
|
| 2153 |
|
|
mem_data[port_b_bit_count_high / width_a] = temp_wa;
|
| 2154 |
|
|
temp_wb[i2] = temp_wa[port_b_bit_count_high % width_a];
|
| 2155 |
|
|
end
|
| 2156 |
|
|
|
| 2157 |
|
|
if (enable_mem_data_b_reading)
|
| 2158 |
|
|
mem_data_b[i_address_reg_b] = temp_wb;
|
| 2159 |
|
|
|
| 2160 |
|
|
if ((read_during_write_mode_port_b == "OLD_DATA") && is_write_positive_edge_reg)
|
| 2161 |
|
|
i_read_flag_b = ~i_read_flag_b;
|
| 2162 |
|
|
|
| 2163 |
|
|
if ((cread_during_write_mode_mixed_ports == "OLD_DATA")&& (address_reg_b == "CLOCK0") && is_write_positive_edge_reg)
|
| 2164 |
|
|
i_read_flag_a = ~i_read_flag_a;
|
| 2165 |
|
|
|
| 2166 |
|
|
end
|
| 2167 |
|
|
|
| 2168 |
|
|
end
|
| 2169 |
|
|
|
| 2170 |
|
|
end
|
| 2171 |
|
|
end
|
| 2172 |
|
|
|
| 2173 |
|
|
|
| 2174 |
|
|
// Port A reading
|
| 2175 |
|
|
|
| 2176 |
|
|
always @(posedge i_read_flag_a or negedge i_read_flag_a)
|
| 2177 |
|
|
begin
|
| 2178 |
|
|
if ((operation_mode == "BIDIR_DUAL_PORT") ||
|
| 2179 |
|
|
(operation_mode == "SINGLE_PORT") ||
|
| 2180 |
|
|
(operation_mode == "ROM"))
|
| 2181 |
|
|
begin
|
| 2182 |
|
|
if (~good_to_go_a && (is_lutram == 0))
|
| 2183 |
|
|
begin
|
| 2184 |
|
|
|
| 2185 |
|
|
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM") ||
|
| 2186 |
|
|
((i_ram_block_type == "AUTO") && (cread_during_write_mode_mixed_ports == "DONT_CARE"))) &&
|
| 2187 |
|
|
(operation_mode != "ROM") &&
|
| 2188 |
|
|
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0))
|
| 2189 |
|
|
i_q_tmp2_a = {width_a{1'bx}};
|
| 2190 |
|
|
else
|
| 2191 |
|
|
i_q_tmp2_a = 0;
|
| 2192 |
|
|
end
|
| 2193 |
|
|
else
|
| 2194 |
|
|
begin
|
| 2195 |
|
|
if (i_rden_reg_a)
|
| 2196 |
|
|
begin
|
| 2197 |
|
|
// read from RAM content or flow through for write cycle
|
| 2198 |
|
|
if (i_wren_reg_a)
|
| 2199 |
|
|
begin
|
| 2200 |
|
|
if (i_core_clocken_a)
|
| 2201 |
|
|
begin
|
| 2202 |
|
|
if (read_during_write_mode_port_a == "NEW_DATA_NO_NBE_READ")
|
| 2203 |
|
|
if (is_lutram && clock0)
|
| 2204 |
|
|
i_q_tmp2_a = mem_data[i_address_reg_a];
|
| 2205 |
|
|
else
|
| 2206 |
|
|
i_q_tmp2_a = ((i_data_reg_a & i_byteena_mask_reg_a) |
|
| 2207 |
|
|
({width_a{1'bx}} & ~i_byteena_mask_reg_a));
|
| 2208 |
|
|
else if (read_during_write_mode_port_a == "NEW_DATA_WITH_NBE_READ")
|
| 2209 |
|
|
if (is_lutram && clock0)
|
| 2210 |
|
|
i_q_tmp2_a = mem_data[i_address_reg_a];
|
| 2211 |
|
|
else
|
| 2212 |
|
|
i_q_tmp2_a = (i_data_reg_a & i_byteena_mask_reg_a) | (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x;
|
| 2213 |
|
|
else if (read_during_write_mode_port_a == "OLD_DATA")
|
| 2214 |
|
|
i_q_tmp2_a = i_original_data_a;
|
| 2215 |
|
|
else
|
| 2216 |
|
|
if (!i_lutram_single_port_fast_read && (i_ram_block_type != "AUTO"))
|
| 2217 |
|
|
begin
|
| 2218 |
|
|
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
|
| 2219 |
|
|
i_q_tmp2_a = {width_a{1'bx}};
|
| 2220 |
|
|
else
|
| 2221 |
|
|
i_q_tmp2_a = i_original_data_a;
|
| 2222 |
|
|
end
|
| 2223 |
|
|
else
|
| 2224 |
|
|
if (is_lutram)
|
| 2225 |
|
|
i_q_tmp2_a = mem_data[i_address_reg_a];
|
| 2226 |
|
|
else
|
| 2227 |
|
|
i_q_tmp2_a = i_data_reg_a ^ i_byteena_mask_reg_a_out;
|
| 2228 |
|
|
end
|
| 2229 |
|
|
else
|
| 2230 |
|
|
i_q_tmp2_a = mem_data[i_address_reg_a];
|
| 2231 |
|
|
end
|
| 2232 |
|
|
else
|
| 2233 |
|
|
i_q_tmp2_a = mem_data[i_address_reg_a];
|
| 2234 |
|
|
|
| 2235 |
|
|
if (is_write_positive_edge_reg)
|
| 2236 |
|
|
begin
|
| 2237 |
|
|
|
| 2238 |
|
|
if (is_bidir_and_wrcontrol_addb_clk0 || (same_clock_pulse0 && same_clock_pulse1))
|
| 2239 |
|
|
begin
|
| 2240 |
|
|
// B write, A read
|
| 2241 |
|
|
if ((i_wren_reg_b & ~i_wren_reg_a) &
|
| 2242 |
|
|
((((is_bidir_and_wrcontrol_addb_clk0 & i_clocken0_b) ||
|
| 2243 |
|
|
(is_bidir_and_wrcontrol_addb_clk1 & i_clocken1_b)) && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0)) ||
|
| 2244 |
|
|
(((is_bidir_and_wrcontrol_addb_clk0 & i_core_clocken0_b) ||
|
| 2245 |
|
|
(is_bidir_and_wrcontrol_addb_clk1 & i_core_clocken1_b)) && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))))
|
| 2246 |
|
|
begin
|
| 2247 |
|
|
add_reg_a_mult_wa = i_address_reg_a * width_a;
|
| 2248 |
|
|
add_reg_b_mult_wb = i_address_reg_b * width_b;
|
| 2249 |
|
|
add_reg_a_mult_wa_pl_wa = add_reg_a_mult_wa + width_a;
|
| 2250 |
|
|
add_reg_b_mult_wb_pl_wb = add_reg_b_mult_wb + width_b;
|
| 2251 |
|
|
|
| 2252 |
|
|
if (
|
| 2253 |
|
|
((add_reg_a_mult_wa >=
|
| 2254 |
|
|
add_reg_b_mult_wb) &&
|
| 2255 |
|
|
(add_reg_a_mult_wa <=
|
| 2256 |
|
|
(add_reg_b_mult_wb_pl_wb - 1)))
|
| 2257 |
|
|
|
| 2258 |
|
|
||
|
| 2259 |
|
|
|
| 2260 |
|
|
(((add_reg_a_mult_wa_pl_wa - 1) >=
|
| 2261 |
|
|
add_reg_b_mult_wb) &&
|
| 2262 |
|
|
((add_reg_a_mult_wa_pl_wa - 1) <=
|
| 2263 |
|
|
(add_reg_b_mult_wb_pl_wb - 1)))
|
| 2264 |
|
|
)
|
| 2265 |
|
|
for (i3 = add_reg_a_mult_wa;
|
| 2266 |
|
|
i3 < add_reg_a_mult_wa_pl_wa;
|
| 2267 |
|
|
i3 = i3 + 1)
|
| 2268 |
|
|
begin
|
| 2269 |
|
|
if ((i3 >= add_reg_b_mult_wb) &&
|
| 2270 |
|
|
(i3 <= (add_reg_b_mult_wb_pl_wb - 1)))
|
| 2271 |
|
|
begin
|
| 2272 |
|
|
|
| 2273 |
|
|
if (read_during_write_mode_mixed_ports == "OLD_DATA")
|
| 2274 |
|
|
begin
|
| 2275 |
|
|
i_byteena_count = i3 - add_reg_b_mult_wb;
|
| 2276 |
|
|
i_q_tmp2_a_idx = (i3 - add_reg_a_mult_wa);
|
| 2277 |
|
|
i_q_tmp2_a[i_q_tmp2_a_idx] = i_original_data_b[i_byteena_count];
|
| 2278 |
|
|
end
|
| 2279 |
|
|
else
|
| 2280 |
|
|
begin
|
| 2281 |
|
|
i_byteena_count = i3 - add_reg_b_mult_wb;
|
| 2282 |
|
|
i_q_tmp2_a_idx = (i3 - add_reg_a_mult_wa);
|
| 2283 |
|
|
i_q_tmp2_a[i_q_tmp2_a_idx] = i_q_tmp2_a[i_q_tmp2_a_idx] ^ i_byteena_mask_reg_b_out_a[i_byteena_count];
|
| 2284 |
|
|
end
|
| 2285 |
|
|
|
| 2286 |
|
|
end
|
| 2287 |
|
|
end
|
| 2288 |
|
|
end
|
| 2289 |
|
|
end
|
| 2290 |
|
|
end
|
| 2291 |
|
|
end
|
| 2292 |
|
|
|
| 2293 |
|
|
if ((is_lutram == 1) && i_address_aclr_a && (~i_address_aclr_family_a) && (operation_mode == "ROM"))
|
| 2294 |
|
|
i_q_tmp2_a = mem_data[0];
|
| 2295 |
|
|
|
| 2296 |
|
|
if ((dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
|
| 2297 |
|
|
(is_lutram != 1) &&
|
| 2298 |
|
|
(i_outdata_aclr_a) &&
|
| 2299 |
|
|
(outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1"))
|
| 2300 |
|
|
i_q_tmp2_a = {width_a{1'b0}};
|
| 2301 |
|
|
end // end good_to_go_a
|
| 2302 |
|
|
end
|
| 2303 |
|
|
end
|
| 2304 |
|
|
|
| 2305 |
|
|
|
| 2306 |
|
|
// assigning the correct output values for i_q_tmp_a (non-registered output)
|
| 2307 |
|
|
always @(i_q_tmp2_a or i_wren_reg_a or i_data_reg_a or i_address_aclr_a or
|
| 2308 |
|
|
i_address_reg_a or i_byteena_mask_reg_a_out or i_numwords_a or i_outdata_aclr_a or i_force_reread_a_signal or i_original_data_a)
|
| 2309 |
|
|
begin
|
| 2310 |
|
|
if (i_address_reg_a >= i_numwords_a)
|
| 2311 |
|
|
begin
|
| 2312 |
|
|
if (i_wren_reg_a && i_core_clocken_a)
|
| 2313 |
|
|
i_q_tmp_a <= i_q_tmp2_a;
|
| 2314 |
|
|
else
|
| 2315 |
|
|
i_q_tmp_a <= {width_a{1'bx}};
|
| 2316 |
|
|
if (i_rden_reg_a == 1)
|
| 2317 |
|
|
begin
|
| 2318 |
|
|
$display("Warning : Address pointed at port A is out of bound!");
|
| 2319 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 2320 |
|
|
end
|
| 2321 |
|
|
end
|
| 2322 |
|
|
else
|
| 2323 |
|
|
begin
|
| 2324 |
|
|
if (i_outdata_aclr_a_prev && ~ i_outdata_aclr_a &&
|
| 2325 |
|
|
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) &&
|
| 2326 |
|
|
(is_lutram != 1))
|
| 2327 |
|
|
begin
|
| 2328 |
|
|
i_outdata_aclr_a_prev = i_outdata_aclr_a;
|
| 2329 |
|
|
i_force_reread_a <= 1;
|
| 2330 |
|
|
end
|
| 2331 |
|
|
else if (~i_address_aclr_a_prev && i_address_aclr_a && (~i_address_aclr_family_a) && s3_address_aclr_a)
|
| 2332 |
|
|
begin
|
| 2333 |
|
|
if (i_rden_reg_a)
|
| 2334 |
|
|
i_q_tmp_a <= {width_a{1'bx}};
|
| 2335 |
|
|
i_force_reread_a1 <= 1;
|
| 2336 |
|
|
end
|
| 2337 |
|
|
else if ((i_force_reread_a1 == 0) && !(i_address_aclr_a_prev && ~i_address_aclr_a && (~i_address_aclr_family_a) && s3_address_aclr_a))
|
| 2338 |
|
|
begin
|
| 2339 |
|
|
i_q_tmp_a <= i_q_tmp2_a;
|
| 2340 |
|
|
end
|
| 2341 |
|
|
end
|
| 2342 |
|
|
if ((i_outdata_aclr_a) && (s3_address_aclr_a))
|
| 2343 |
|
|
begin
|
| 2344 |
|
|
i_q_tmp_a <= {width_a{1'b0}};
|
| 2345 |
|
|
i_outdata_aclr_a_prev <= i_outdata_aclr_a;
|
| 2346 |
|
|
end
|
| 2347 |
|
|
i_address_aclr_a_prev <= i_address_aclr_a;
|
| 2348 |
|
|
end
|
| 2349 |
|
|
|
| 2350 |
|
|
|
| 2351 |
|
|
// Port A outdata output registered
|
| 2352 |
|
|
always @(posedge i_outdata_clk_a or posedge i_outdata_aclr_a)
|
| 2353 |
|
|
begin
|
| 2354 |
|
|
if (i_outdata_aclr_a)
|
| 2355 |
|
|
i_q_reg_a <= 0;
|
| 2356 |
|
|
else if (i_outdata_clken_a)
|
| 2357 |
|
|
begin
|
| 2358 |
|
|
if ((i_address_aclr_a_flag == 1) &&
|
| 2359 |
|
|
(dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) &&
|
| 2360 |
|
|
(outdata_reg_a == "CLOCK0") && (is_lutram != 1))
|
| 2361 |
|
|
i_q_reg_a <= 'bx;
|
| 2362 |
|
|
else
|
| 2363 |
|
|
i_q_reg_a <= i_q_tmp_a;
|
| 2364 |
|
|
if (i_core_clocken_a)
|
| 2365 |
|
|
i_address_aclr_a_flag <= 0;
|
| 2366 |
|
|
end
|
| 2367 |
|
|
else if (i_core_clocken_a)
|
| 2368 |
|
|
i_address_aclr_a_flag <= 0;
|
| 2369 |
|
|
end
|
| 2370 |
|
|
|
| 2371 |
|
|
// Latch for address aclr till outclock enabled
|
| 2372 |
|
|
always @(posedge i_address_aclr_a or posedge i_outdata_aclr_a)
|
| 2373 |
|
|
if (i_outdata_aclr_a)
|
| 2374 |
|
|
i_address_aclr_a_flag <= 0;
|
| 2375 |
|
|
else
|
| 2376 |
|
|
if (i_rden_reg_a && (~i_address_aclr_family_a))
|
| 2377 |
|
|
i_address_aclr_a_flag <= 1;
|
| 2378 |
|
|
|
| 2379 |
|
|
// Port A : assigning the correct output values for q_a
|
| 2380 |
|
|
assign q_a = (operation_mode == "DUAL_PORT") ?
|
| 2381 |
|
|
{width_a{1'b0}} : (((outdata_reg_a == "CLOCK0") ||
|
| 2382 |
|
|
(outdata_reg_a == "CLOCK1")) ?
|
| 2383 |
|
|
i_q_reg_a : i_q_tmp_a);
|
| 2384 |
|
|
|
| 2385 |
|
|
|
| 2386 |
|
|
// Port B reading
|
| 2387 |
|
|
always @(posedge i_read_flag_b or negedge i_read_flag_b)
|
| 2388 |
|
|
begin
|
| 2389 |
|
|
if ((operation_mode == "BIDIR_DUAL_PORT") ||
|
| 2390 |
|
|
(operation_mode == "DUAL_PORT"))
|
| 2391 |
|
|
begin
|
| 2392 |
|
|
if (~good_to_go_b && (is_lutram == 0))
|
| 2393 |
|
|
begin
|
| 2394 |
|
|
|
| 2395 |
|
|
if ((check_simultaneous_read_write == 1) &&
|
| 2396 |
|
|
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0) &&
|
| 2397 |
|
|
(dev.FEATURE_FAMILY_CYCLONEII(intended_device_family) == 0))
|
| 2398 |
|
|
i_q_tmp2_b = {width_b{1'bx}};
|
| 2399 |
|
|
else
|
| 2400 |
|
|
i_q_tmp2_b = 0;
|
| 2401 |
|
|
end
|
| 2402 |
|
|
else
|
| 2403 |
|
|
begin
|
| 2404 |
|
|
if (i_rden_reg_b)
|
| 2405 |
|
|
begin
|
| 2406 |
|
|
//If width_a is equal to b, no address calculation is needed
|
| 2407 |
|
|
if (width_a == width_b)
|
| 2408 |
|
|
begin
|
| 2409 |
|
|
|
| 2410 |
|
|
// read from memory or flow through for write cycle
|
| 2411 |
|
|
if (i_wren_reg_b && (((is_bidir_and_wrcontrol_addb_clk0 == 1) && i_core_clocken0_b) ||
|
| 2412 |
|
|
((is_bidir_and_wrcontrol_addb_clk1 == 1) && i_core_clocken1_b)))
|
| 2413 |
|
|
begin
|
| 2414 |
|
|
if (read_during_write_mode_port_b == "NEW_DATA_NO_NBE_READ")
|
| 2415 |
|
|
temp_wb = ((i_data_reg_b & i_byteena_mask_reg_b) |
|
| 2416 |
|
|
({width_b{1'bx}} & ~i_byteena_mask_reg_b));
|
| 2417 |
|
|
else if (read_during_write_mode_port_b == "NEW_DATA_WITH_NBE_READ")
|
| 2418 |
|
|
temp_wb = (i_data_reg_b & i_byteena_mask_reg_b) | (mem_data[i_address_reg_b] & ~i_byteena_mask_reg_b) ^ i_byteena_mask_reg_b_x;
|
| 2419 |
|
|
else if (read_during_write_mode_port_b == "OLD_DATA")
|
| 2420 |
|
|
temp_wb = i_original_data_b;
|
| 2421 |
|
|
else
|
| 2422 |
|
|
temp_wb = {width_b{1'bx}};
|
| 2423 |
|
|
end
|
| 2424 |
|
|
else if ((i_data_write_time_a == $time) && (operation_mode == "DUAL_PORT") &&
|
| 2425 |
|
|
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0))
|
| 2426 |
|
|
begin
|
| 2427 |
|
|
// if A write to the same Ram address B is reading from
|
| 2428 |
|
|
if ((i_address_reg_b == i_address_reg_a) && (i_original_address_a == i_address_reg_a))
|
| 2429 |
|
|
begin
|
| 2430 |
|
|
if (address_reg_b != "CLOCK0")
|
| 2431 |
|
|
temp_wb = mem_data[i_address_reg_b] ^ i_byteena_mask_reg_a_out_b;
|
| 2432 |
|
|
else if (cread_during_write_mode_mixed_ports == "OLD_DATA")
|
| 2433 |
|
|
begin
|
| 2434 |
|
|
if (mem_data[i_address_reg_b] == ((i_data_reg_a & i_byteena_mask_reg_a) | (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x))
|
| 2435 |
|
|
temp_wb = i_original_data_a;
|
| 2436 |
|
|
else
|
| 2437 |
|
|
temp_wb = mem_data[i_address_reg_b];
|
| 2438 |
|
|
end
|
| 2439 |
|
|
else if (cread_during_write_mode_mixed_ports == "DONT_CARE")
|
| 2440 |
|
|
temp_wb = mem_data[i_address_reg_b] ^ i_byteena_mask_reg_a_out_b;
|
| 2441 |
|
|
else
|
| 2442 |
|
|
temp_wb = mem_data[i_address_reg_b];
|
| 2443 |
|
|
end
|
| 2444 |
|
|
else
|
| 2445 |
|
|
temp_wb = mem_data[i_address_reg_b];
|
| 2446 |
|
|
end
|
| 2447 |
|
|
else
|
| 2448 |
|
|
temp_wb = mem_data[i_address_reg_b];
|
| 2449 |
|
|
|
| 2450 |
|
|
if (is_write_positive_edge_reg)
|
| 2451 |
|
|
begin
|
| 2452 |
|
|
if ((dual_port_addreg_b_clk0 == 1) ||
|
| 2453 |
|
|
(is_bidir_and_wrcontrol_addb_clk0 == 1) || (same_clock_pulse0 && same_clock_pulse1))
|
| 2454 |
|
|
begin
|
| 2455 |
|
|
// A write, B read
|
| 2456 |
|
|
if ((i_wren_reg_a & ~i_wren_reg_b) &&
|
| 2457 |
|
|
((i_clocken0 && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0)) ||
|
| 2458 |
|
|
(i_core_clocken_a && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))))
|
| 2459 |
|
|
begin
|
| 2460 |
|
|
// if A write to the same Ram address B is reading from
|
| 2461 |
|
|
if (i_address_reg_b == i_address_reg_a)
|
| 2462 |
|
|
begin
|
| 2463 |
|
|
if (i_lutram_dual_port_fast_read)
|
| 2464 |
|
|
temp_wb = (i_data_reg_a & i_byteena_mask_reg_a) | (i_q_tmp2_a & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x;
|
| 2465 |
|
|
else
|
| 2466 |
|
|
if (cread_during_write_mode_mixed_ports == "OLD_DATA")
|
| 2467 |
|
|
if ((mem_data[i_address_reg_b] == ((i_data_reg_a & i_byteena_mask_reg_a) | (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x))
|
| 2468 |
|
|
&& (i_data_write_time_a == $time))
|
| 2469 |
|
|
temp_wb = i_original_data_a;
|
| 2470 |
|
|
else
|
| 2471 |
|
|
temp_wb = mem_data[i_address_reg_b];
|
| 2472 |
|
|
else
|
| 2473 |
|
|
temp_wb = mem_data[i_address_reg_b] ^ i_byteena_mask_reg_a_out_b;
|
| 2474 |
|
|
end
|
| 2475 |
|
|
end
|
| 2476 |
|
|
end
|
| 2477 |
|
|
end
|
| 2478 |
|
|
end
|
| 2479 |
|
|
else
|
| 2480 |
|
|
begin
|
| 2481 |
|
|
j2 = i_address_reg_b * width_b;
|
| 2482 |
|
|
|
| 2483 |
|
|
for (i5=0; i5<width_b; i5=i5+1)
|
| 2484 |
|
|
begin
|
| 2485 |
|
|
j2_plus_i5 = j2 + i5;
|
| 2486 |
|
|
temp_wa2b = mem_data[j2_plus_i5 / width_a];
|
| 2487 |
|
|
temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
|
| 2488 |
|
|
end
|
| 2489 |
|
|
|
| 2490 |
|
|
if (i_wren_reg_b && ((is_bidir_and_wrcontrol_addb_clk0 && i_core_clocken0_b) ||
|
| 2491 |
|
|
(is_bidir_and_wrcontrol_addb_clk1 && i_core_clocken1_b)))
|
| 2492 |
|
|
begin
|
| 2493 |
|
|
if (read_during_write_mode_port_b == "NEW_DATA_NO_NBE_READ")
|
| 2494 |
|
|
temp_wb = i_data_reg_b ^ i_byteena_mask_reg_b_out;
|
| 2495 |
|
|
else if (read_during_write_mode_port_b == "NEW_DATA_WITH_NBE_READ")
|
| 2496 |
|
|
temp_wb = (i_data_reg_b & i_byteena_mask_reg_b) | (temp_wb & ~i_byteena_mask_reg_b) ^ i_byteena_mask_reg_b_x;
|
| 2497 |
|
|
else if (read_during_write_mode_port_b == "OLD_DATA")
|
| 2498 |
|
|
temp_wb = i_original_data_b;
|
| 2499 |
|
|
else
|
| 2500 |
|
|
temp_wb = {width_b{1'bx}};
|
| 2501 |
|
|
end
|
| 2502 |
|
|
else if ((i_data_write_time_a == $time) && (operation_mode == "DUAL_PORT") &&
|
| 2503 |
|
|
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0))
|
| 2504 |
|
|
begin
|
| 2505 |
|
|
for (i5=0; i5<width_b; i5=i5+1)
|
| 2506 |
|
|
begin
|
| 2507 |
|
|
j2_plus_i5 = j2 + i5;
|
| 2508 |
|
|
j2_plus_i5_div_a = j2_plus_i5 / width_a;
|
| 2509 |
|
|
|
| 2510 |
|
|
// if A write to the same Ram address B is reading from
|
| 2511 |
|
|
if ((j2_plus_i5_div_a == i_address_reg_a) && (i_original_address_a == i_address_reg_a))
|
| 2512 |
|
|
begin
|
| 2513 |
|
|
if (address_reg_b != "CLOCK0")
|
| 2514 |
|
|
begin
|
| 2515 |
|
|
temp_wa2b = mem_data[j2_plus_i5_div_a];
|
| 2516 |
|
|
temp_wa2b = temp_wa2b ^ i_byteena_mask_reg_a_out_b;
|
| 2517 |
|
|
end
|
| 2518 |
|
|
else if (cread_during_write_mode_mixed_ports == "OLD_DATA")
|
| 2519 |
|
|
temp_wa2b = i_original_data_a;
|
| 2520 |
|
|
else if (cread_during_write_mode_mixed_ports == "DONT_CARE")
|
| 2521 |
|
|
begin
|
| 2522 |
|
|
temp_wa2b = mem_data[j2_plus_i5_div_a];
|
| 2523 |
|
|
temp_wa2b = temp_wa2b ^ i_byteena_mask_reg_a_out_b;
|
| 2524 |
|
|
end
|
| 2525 |
|
|
else
|
| 2526 |
|
|
temp_wa2b = mem_data[j2_plus_i5_div_a];
|
| 2527 |
|
|
end
|
| 2528 |
|
|
else
|
| 2529 |
|
|
temp_wa2b = mem_data[j2_plus_i5_div_a];
|
| 2530 |
|
|
|
| 2531 |
|
|
temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
|
| 2532 |
|
|
end
|
| 2533 |
|
|
end
|
| 2534 |
|
|
|
| 2535 |
|
|
if (is_write_positive_edge_reg)
|
| 2536 |
|
|
begin
|
| 2537 |
|
|
if (((address_reg_b == "CLOCK0") & dual_port_addreg_b_clk0) ||
|
| 2538 |
|
|
((wrcontrol_wraddress_reg_b == "CLOCK0") & is_bidir_and_wrcontrol_addb_clk0) || (same_clock_pulse0 && same_clock_pulse1))
|
| 2539 |
|
|
begin
|
| 2540 |
|
|
// A write, B read
|
| 2541 |
|
|
if ((i_wren_reg_a & ~i_wren_reg_b) &&
|
| 2542 |
|
|
((i_clocken0 && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0)) ||
|
| 2543 |
|
|
(i_core_clocken_a && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))))
|
| 2544 |
|
|
begin
|
| 2545 |
|
|
|
| 2546 |
|
|
for (i5=0; i5<width_b; i5=i5+1)
|
| 2547 |
|
|
begin
|
| 2548 |
|
|
j2_plus_i5 = j2 + i5;
|
| 2549 |
|
|
j2_plus_i5_div_a = j2_plus_i5 / width_a;
|
| 2550 |
|
|
|
| 2551 |
|
|
// if A write to the same Ram address B is reading from
|
| 2552 |
|
|
if (j2_plus_i5_div_a == i_address_reg_a)
|
| 2553 |
|
|
begin
|
| 2554 |
|
|
if (i_lutram_single_port_fast_read)
|
| 2555 |
|
|
temp_wa2b = (i_data_reg_a & i_byteena_mask_reg_a) | (i_q_tmp2_a & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x;
|
| 2556 |
|
|
else
|
| 2557 |
|
|
begin
|
| 2558 |
|
|
if ((cread_during_write_mode_mixed_ports == "OLD_DATA") && (i_data_write_time_a == $time))
|
| 2559 |
|
|
temp_wa2b = i_original_data_a;
|
| 2560 |
|
|
else
|
| 2561 |
|
|
begin
|
| 2562 |
|
|
temp_wa2b = mem_data[j2_plus_i5_div_a];
|
| 2563 |
|
|
temp_wa2b = temp_wa2b ^ i_byteena_mask_reg_a_out_b;
|
| 2564 |
|
|
end
|
| 2565 |
|
|
end
|
| 2566 |
|
|
|
| 2567 |
|
|
temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
|
| 2568 |
|
|
end
|
| 2569 |
|
|
|
| 2570 |
|
|
end
|
| 2571 |
|
|
end
|
| 2572 |
|
|
end
|
| 2573 |
|
|
end
|
| 2574 |
|
|
end
|
| 2575 |
|
|
//end of width_a != width_b
|
| 2576 |
|
|
|
| 2577 |
|
|
i_q_tmp2_b = temp_wb;
|
| 2578 |
|
|
|
| 2579 |
|
|
end
|
| 2580 |
|
|
|
| 2581 |
|
|
if ((is_lutram == 1) && i_address_aclr_b && (~i_address_aclr_family_b) && (operation_mode == "DUAL_PORT"))
|
| 2582 |
|
|
begin
|
| 2583 |
|
|
for (init_i = 0; init_i < width_b; init_i = init_i + 1)
|
| 2584 |
|
|
begin
|
| 2585 |
|
|
init_temp = mem_data[init_i / width_a];
|
| 2586 |
|
|
i_q_tmp_b[init_i] = init_temp[init_i % width_a];
|
| 2587 |
|
|
i_q_tmp2_b[init_i] = init_temp[init_i % width_a];
|
| 2588 |
|
|
end
|
| 2589 |
|
|
end
|
| 2590 |
|
|
else if ((is_lutram == 1) && (operation_mode == "DUAL_PORT"))
|
| 2591 |
|
|
begin
|
| 2592 |
|
|
j2 = i_address_reg_b * width_b;
|
| 2593 |
|
|
|
| 2594 |
|
|
for (i5=0; i5<width_b; i5=i5+1)
|
| 2595 |
|
|
begin
|
| 2596 |
|
|
j2_plus_i5 = j2 + i5;
|
| 2597 |
|
|
temp_wa2b = mem_data[j2_plus_i5 / width_a];
|
| 2598 |
|
|
i_q_tmp2_b[i5] = temp_wa2b[j2_plus_i5 % width_a];
|
| 2599 |
|
|
end
|
| 2600 |
|
|
end
|
| 2601 |
|
|
|
| 2602 |
|
|
if ((i_outdata_aclr_b) &&
|
| 2603 |
|
|
(dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
|
| 2604 |
|
|
(is_lutram != 1) &&
|
| 2605 |
|
|
(outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1"))
|
| 2606 |
|
|
i_q_tmp2_b = {width_b{1'b0}};
|
| 2607 |
|
|
end
|
| 2608 |
|
|
end
|
| 2609 |
|
|
end
|
| 2610 |
|
|
|
| 2611 |
|
|
|
| 2612 |
|
|
// assigning the correct output values for i_q_tmp_b (non-registered output)
|
| 2613 |
|
|
always @(i_q_tmp2_b or i_wren_reg_b or i_data_reg_b or i_address_aclr_b or
|
| 2614 |
|
|
i_address_reg_b or i_byteena_mask_reg_b_out or i_rden_reg_b or
|
| 2615 |
|
|
i_numwords_b or i_outdata_aclr_b or i_force_reread_b_signal)
|
| 2616 |
|
|
begin
|
| 2617 |
|
|
if (i_address_reg_b >= i_numwords_b)
|
| 2618 |
|
|
begin
|
| 2619 |
|
|
if (i_wren_reg_b && ((i_core_clocken0_b && (is_bidir_and_wrcontrol_addb_clk0 == 1)) || (i_core_clocken1_b && (is_bidir_and_wrcontrol_addb_clk1 == 1))))
|
| 2620 |
|
|
i_q_tmp_b <= i_q_tmp2_b;
|
| 2621 |
|
|
else
|
| 2622 |
|
|
i_q_tmp_b <= {width_b{1'bx}};
|
| 2623 |
|
|
if (i_rden_reg_b == 1)
|
| 2624 |
|
|
begin
|
| 2625 |
|
|
$display("Warning : Address pointed at port B is out of bound!");
|
| 2626 |
|
|
$display("Time: %0t Instance: %m", $time);
|
| 2627 |
|
|
end
|
| 2628 |
|
|
end
|
| 2629 |
|
|
else
|
| 2630 |
|
|
if (operation_mode == "BIDIR_DUAL_PORT")
|
| 2631 |
|
|
begin
|
| 2632 |
|
|
|
| 2633 |
|
|
if (i_outdata_aclr_b_prev && ~ i_outdata_aclr_b && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (is_lutram != 1))
|
| 2634 |
|
|
begin
|
| 2635 |
|
|
i_outdata_aclr_b_prev <= i_outdata_aclr_b;
|
| 2636 |
|
|
i_force_reread_b <= 1;
|
| 2637 |
|
|
end
|
| 2638 |
|
|
else
|
| 2639 |
|
|
begin
|
| 2640 |
|
|
i_q_tmp_b <= i_q_tmp2_b;
|
| 2641 |
|
|
end
|
| 2642 |
|
|
end
|
| 2643 |
|
|
else if (operation_mode == "DUAL_PORT")
|
| 2644 |
|
|
begin
|
| 2645 |
|
|
if (i_outdata_aclr_b_prev && ~ i_outdata_aclr_b && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (is_lutram != 1))
|
| 2646 |
|
|
begin
|
| 2647 |
|
|
i_outdata_aclr_b_prev <= i_outdata_aclr_b;
|
| 2648 |
|
|
i_force_reread_b <= 1;
|
| 2649 |
|
|
end
|
| 2650 |
|
|
else if (~i_address_aclr_b_prev && i_address_aclr_b && (~i_address_aclr_family_b) && s3_address_aclr_b)
|
| 2651 |
|
|
begin
|
| 2652 |
|
|
if (i_rden_reg_b)
|
| 2653 |
|
|
i_q_tmp_b <= {width_b{1'bx}};
|
| 2654 |
|
|
i_force_reread_b1 <= 1;
|
| 2655 |
|
|
end
|
| 2656 |
|
|
else if ((i_force_reread_b1 == 0) && !(i_address_aclr_b_prev && ~i_address_aclr_b && (~i_address_aclr_family_b) && s3_address_aclr_b))
|
| 2657 |
|
|
begin
|
| 2658 |
|
|
if (i_rden_reg_b || (is_lutram == 1))
|
| 2659 |
|
|
i_q_tmp_b <= i_q_tmp2_b;
|
| 2660 |
|
|
end
|
| 2661 |
|
|
end
|
| 2662 |
|
|
|
| 2663 |
|
|
if ((i_outdata_aclr_b) && (s3_address_aclr_b))
|
| 2664 |
|
|
begin
|
| 2665 |
|
|
i_q_tmp_b <= {width_b{1'b0}};
|
| 2666 |
|
|
i_outdata_aclr_b_prev <= i_outdata_aclr_b;
|
| 2667 |
|
|
end
|
| 2668 |
|
|
i_address_aclr_b_prev <= i_address_aclr_b;
|
| 2669 |
|
|
end
|
| 2670 |
|
|
|
| 2671 |
|
|
// output latch for lutram (only used when read_during_write_mode_mixed_ports == "OLD_DATA")
|
| 2672 |
|
|
always @(negedge i_outdata_clk_b)
|
| 2673 |
|
|
begin
|
| 2674 |
|
|
if (i_core_clocken_a)
|
| 2675 |
|
|
i_q_output_latch <= i_q_tmp2_b;
|
| 2676 |
|
|
end
|
| 2677 |
|
|
|
| 2678 |
|
|
// Port B outdata output registered
|
| 2679 |
|
|
always @(posedge i_outdata_clk_b or posedge i_outdata_aclr_b)
|
| 2680 |
|
|
begin
|
| 2681 |
|
|
if (i_outdata_aclr_b)
|
| 2682 |
|
|
i_q_reg_b <= 0;
|
| 2683 |
|
|
else if (i_outdata_clken_b)
|
| 2684 |
|
|
begin
|
| 2685 |
|
|
if ((is_lutram == 1) && (cread_during_write_mode_mixed_ports == "OLD_DATA") && (outdata_reg_b == "CLOCK0"))
|
| 2686 |
|
|
i_q_reg_b <= i_q_output_latch;
|
| 2687 |
|
|
else
|
| 2688 |
|
|
begin
|
| 2689 |
|
|
if ((i_address_aclr_b_flag == 1) && (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) &&
|
| 2690 |
|
|
(is_lutram != 1))
|
| 2691 |
|
|
i_q_reg_b <= 'bx;
|
| 2692 |
|
|
else
|
| 2693 |
|
|
i_q_reg_b <= i_q_tmp_b;
|
| 2694 |
|
|
end
|
| 2695 |
|
|
end
|
| 2696 |
|
|
end
|
| 2697 |
|
|
|
| 2698 |
|
|
// Latch for address aclr till outclock enabled
|
| 2699 |
|
|
always @(posedge i_address_aclr_b or posedge i_outdata_aclr_b)
|
| 2700 |
|
|
if (i_outdata_aclr_b)
|
| 2701 |
|
|
i_address_aclr_b_flag <= 0;
|
| 2702 |
|
|
else
|
| 2703 |
|
|
begin
|
| 2704 |
|
|
if (i_rden_reg_b)
|
| 2705 |
|
|
i_address_aclr_b_flag <= 1;
|
| 2706 |
|
|
end
|
| 2707 |
|
|
|
| 2708 |
|
|
// Port B : assigning the correct output values for q_b
|
| 2709 |
|
|
assign q_b = ((operation_mode == "SINGLE_PORT") ||
|
| 2710 |
|
|
(operation_mode == "ROM")) ?
|
| 2711 |
|
|
{width_b{1'b0}} : (((outdata_reg_b == "CLOCK0") ||
|
| 2712 |
|
|
(outdata_reg_b == "CLOCK1")) ?
|
| 2713 |
|
|
i_q_reg_b : i_q_tmp_b);
|
| 2714 |
|
|
|
| 2715 |
|
|
|
| 2716 |
|
|
// ECC status
|
| 2717 |
|
|
assign eccstatus = {3'b000};
|
| 2718 |
|
|
|
| 2719 |
|
|
endmodule // ALTSYNCRAM
|
| 2720 |
|
|
|
| 2721 |
|
|
// END OF MODULE
|
| 2722 |
|
|
|
| 2723 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
| 2724 |
|
|
//
|
| 2725 |
|
|
// Module Name : ALTERA_DEVICE_FAMILIES
|
| 2726 |
|
|
//
|
| 2727 |
|
|
// Description : Common Altera device families comparison
|
| 2728 |
|
|
//
|
| 2729 |
|
|
// Limitation :
|
| 2730 |
|
|
//
|
| 2731 |
|
|
// Results expected:
|
| 2732 |
|
|
//
|
| 2733 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
| 2734 |
|
|
|
| 2735 |
|
|
// BEGINNING OF MODULE
|
| 2736 |
|
|
`timescale 1 ps / 1 ps
|
| 2737 |
|
|
|
| 2738 |
|
|
// MODULE DECLARATION
|
| 2739 |
|
|
module ALTERA_DEVICE_FAMILIES;
|
| 2740 |
|
|
|
| 2741 |
|
|
function IS_FAMILY_ACEX1K;
|
| 2742 |
|
|
input[8*20:1] device;
|
| 2743 |
|
|
reg is_acex1k;
|
| 2744 |
|
|
begin
|
| 2745 |
|
|
if ((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k"))
|
| 2746 |
|
|
is_acex1k = 1;
|
| 2747 |
|
|
else
|
| 2748 |
|
|
is_acex1k = 0;
|
| 2749 |
|
|
|
| 2750 |
|
|
IS_FAMILY_ACEX1K = is_acex1k;
|
| 2751 |
|
|
end
|
| 2752 |
|
|
endfunction //IS_FAMILY_ACEX1K
|
| 2753 |
|
|
|
| 2754 |
|
|
function IS_FAMILY_APEX20K;
|
| 2755 |
|
|
input[8*20:1] device;
|
| 2756 |
|
|
reg is_apex20k;
|
| 2757 |
|
|
begin
|
| 2758 |
|
|
if ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael"))
|
| 2759 |
|
|
is_apex20k = 1;
|
| 2760 |
|
|
else
|
| 2761 |
|
|
is_apex20k = 0;
|
| 2762 |
|
|
|
| 2763 |
|
|
IS_FAMILY_APEX20K = is_apex20k;
|
| 2764 |
|
|
end
|
| 2765 |
|
|
endfunction //IS_FAMILY_APEX20K
|
| 2766 |
|
|
|
| 2767 |
|
|
function IS_FAMILY_APEX20KC;
|
| 2768 |
|
|
input[8*20:1] device;
|
| 2769 |
|
|
reg is_apex20kc;
|
| 2770 |
|
|
begin
|
| 2771 |
|
|
if ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc"))
|
| 2772 |
|
|
is_apex20kc = 1;
|
| 2773 |
|
|
else
|
| 2774 |
|
|
is_apex20kc = 0;
|
| 2775 |
|
|
|
| 2776 |
|
|
IS_FAMILY_APEX20KC = is_apex20kc;
|
| 2777 |
|
|
end
|
| 2778 |
|
|
endfunction //IS_FAMILY_APEX20KC
|
| 2779 |
|
|
|
| 2780 |
|
|
function IS_FAMILY_APEX20KE;
|
| 2781 |
|
|
input[8*20:1] device;
|
| 2782 |
|
|
reg is_apex20ke;
|
| 2783 |
|
|
begin
|
| 2784 |
|
|
if ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke"))
|
| 2785 |
|
|
is_apex20ke = 1;
|
| 2786 |
|
|
else
|
| 2787 |
|
|
is_apex20ke = 0;
|
| 2788 |
|
|
|
| 2789 |
|
|
IS_FAMILY_APEX20KE = is_apex20ke;
|
| 2790 |
|
|
end
|
| 2791 |
|
|
endfunction //IS_FAMILY_APEX20KE
|
| 2792 |
|
|
|
| 2793 |
|
|
function IS_FAMILY_APEXII;
|
| 2794 |
|
|
input[8*20:1] device;
|
| 2795 |
|
|
reg is_apexii;
|
| 2796 |
|
|
begin
|
| 2797 |
|
|
if ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf"))
|
| 2798 |
|
|
is_apexii = 1;
|
| 2799 |
|
|
else
|
| 2800 |
|
|
is_apexii = 0;
|
| 2801 |
|
|
|
| 2802 |
|
|
IS_FAMILY_APEXII = is_apexii;
|
| 2803 |
|
|
end
|
| 2804 |
|
|
endfunction //IS_FAMILY_APEXII
|
| 2805 |
|
|
|
| 2806 |
|
|
function IS_FAMILY_EXCALIBUR_ARM;
|
| 2807 |
|
|
input[8*20:1] device;
|
| 2808 |
|
|
reg is_excalibur_arm;
|
| 2809 |
|
|
begin
|
| 2810 |
|
|
if ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur"))
|
| 2811 |
|
|
is_excalibur_arm = 1;
|
| 2812 |
|
|
else
|
| 2813 |
|
|
is_excalibur_arm = 0;
|
| 2814 |
|
|
|
| 2815 |
|
|
IS_FAMILY_EXCALIBUR_ARM = is_excalibur_arm;
|
| 2816 |
|
|
end
|
| 2817 |
|
|
endfunction //IS_FAMILY_EXCALIBUR_ARM
|
| 2818 |
|
|
|
| 2819 |
|
|
function IS_FAMILY_FLEX10KE;
|
| 2820 |
|
|
input[8*20:1] device;
|
| 2821 |
|
|
reg is_flex10ke;
|
| 2822 |
|
|
begin
|
| 2823 |
|
|
if ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke"))
|
| 2824 |
|
|
is_flex10ke = 1;
|
| 2825 |
|
|
else
|
| 2826 |
|
|
is_flex10ke = 0;
|
| 2827 |
|
|
|
| 2828 |
|
|
IS_FAMILY_FLEX10KE = is_flex10ke;
|
| 2829 |
|
|
end
|
| 2830 |
|
|
endfunction //IS_FAMILY_FLEX10KE
|
| 2831 |
|
|
|
| 2832 |
|
|
function IS_FAMILY_STRATIX;
|
| 2833 |
|
|
input[8*20:1] device;
|
| 2834 |
|
|
reg is_stratix;
|
| 2835 |
|
|
begin
|
| 2836 |
|
|
if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|
| 2837 |
|
|
is_stratix = 1;
|
| 2838 |
|
|
else
|
| 2839 |
|
|
is_stratix = 0;
|
| 2840 |
|
|
|
| 2841 |
|
|
IS_FAMILY_STRATIX = is_stratix;
|
| 2842 |
|
|
end
|
| 2843 |
|
|
endfunction //IS_FAMILY_STRATIX
|
| 2844 |
|
|
|
| 2845 |
|
|
function IS_FAMILY_STRATIXGX;
|
| 2846 |
|
|
input[8*20:1] device;
|
| 2847 |
|
|
reg is_stratixgx;
|
| 2848 |
|
|
begin
|
| 2849 |
|
|
if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|
| 2850 |
|
|
is_stratixgx = 1;
|
| 2851 |
|
|
else
|
| 2852 |
|
|
is_stratixgx = 0;
|
| 2853 |
|
|
|
| 2854 |
|
|
IS_FAMILY_STRATIXGX = is_stratixgx;
|
| 2855 |
|
|
end
|
| 2856 |
|
|
endfunction //IS_FAMILY_STRATIXGX
|
| 2857 |
|
|
|
| 2858 |
|
|
function IS_FAMILY_CYCLONE;
|
| 2859 |
|
|
input[8*20:1] device;
|
| 2860 |
|
|
reg is_cyclone;
|
| 2861 |
|
|
begin
|
| 2862 |
|
|
if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|
| 2863 |
|
|
is_cyclone = 1;
|
| 2864 |
|
|
else
|
| 2865 |
|
|
is_cyclone = 0;
|
| 2866 |
|
|
|
| 2867 |
|
|
IS_FAMILY_CYCLONE = is_cyclone;
|
| 2868 |
|
|
end
|
| 2869 |
|
|
endfunction //IS_FAMILY_CYCLONE
|
| 2870 |
|
|
|
| 2871 |
|
|
function IS_FAMILY_MAXII;
|
| 2872 |
|
|
input[8*20:1] device;
|
| 2873 |
|
|
reg is_maxii;
|
| 2874 |
|
|
begin
|
| 2875 |
|
|
if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|
| 2876 |
|
|
is_maxii = 1;
|
| 2877 |
|
|
else
|
| 2878 |
|
|
is_maxii = 0;
|
| 2879 |
|
|
|
| 2880 |
|
|
IS_FAMILY_MAXII = is_maxii;
|
| 2881 |
|
|
end
|
| 2882 |
|
|
endfunction //IS_FAMILY_MAXII
|
| 2883 |
|
|
|
| 2884 |
|
|
function IS_FAMILY_HARDCOPYSTRATIX;
|
| 2885 |
|
|
input[8*20:1] device;
|
| 2886 |
|
|
reg is_hardcopystratix;
|
| 2887 |
|
|
begin
|
| 2888 |
|
|
if ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix"))
|
| 2889 |
|
|
is_hardcopystratix = 1;
|
| 2890 |
|
|
else
|
| 2891 |
|
|
is_hardcopystratix = 0;
|
| 2892 |
|
|
|
| 2893 |
|
|
IS_FAMILY_HARDCOPYSTRATIX = is_hardcopystratix;
|
| 2894 |
|
|
end
|
| 2895 |
|
|
endfunction //IS_FAMILY_HARDCOPYSTRATIX
|
| 2896 |
|
|
|
| 2897 |
|
|
function IS_FAMILY_STRATIXII;
|
| 2898 |
|
|
input[8*20:1] device;
|
| 2899 |
|
|
reg is_stratixii;
|
| 2900 |
|
|
begin
|
| 2901 |
|
|
if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|
| 2902 |
|
|
is_stratixii = 1;
|
| 2903 |
|
|
else
|
| 2904 |
|
|
is_stratixii = 0;
|
| 2905 |
|
|
|
| 2906 |
|
|
IS_FAMILY_STRATIXII = is_stratixii;
|
| 2907 |
|
|
end
|
| 2908 |
|
|
endfunction //IS_FAMILY_STRATIXII
|
| 2909 |
|
|
|
| 2910 |
|
|
function IS_FAMILY_STRATIXIIGX;
|
| 2911 |
|
|
input[8*20:1] device;
|
| 2912 |
|
|
reg is_stratixiigx;
|
| 2913 |
|
|
begin
|
| 2914 |
|
|
if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|
| 2915 |
|
|
is_stratixiigx = 1;
|
| 2916 |
|
|
else
|
| 2917 |
|
|
is_stratixiigx = 0;
|
| 2918 |
|
|
|
| 2919 |
|
|
IS_FAMILY_STRATIXIIGX = is_stratixiigx;
|
| 2920 |
|
|
end
|
| 2921 |
|
|
endfunction //IS_FAMILY_STRATIXIIGX
|
| 2922 |
|
|
|
| 2923 |
|
|
function IS_FAMILY_ARRIAGX;
|
| 2924 |
|
|
input[8*20:1] device;
|
| 2925 |
|
|
reg is_arriagx;
|
| 2926 |
|
|
begin
|
| 2927 |
|
|
if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|
| 2928 |
|
|
is_arriagx = 1;
|
| 2929 |
|
|
else
|
| 2930 |
|
|
is_arriagx = 0;
|
| 2931 |
|
|
|
| 2932 |
|
|
IS_FAMILY_ARRIAGX = is_arriagx;
|
| 2933 |
|
|
end
|
| 2934 |
|
|
endfunction //IS_FAMILY_ARRIAGX
|
| 2935 |
|
|
|
| 2936 |
|
|
function IS_FAMILY_CYCLONEII;
|
| 2937 |
|
|
input[8*20:1] device;
|
| 2938 |
|
|
reg is_cycloneii;
|
| 2939 |
|
|
begin
|
| 2940 |
|
|
if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
|
| 2941 |
|
|
is_cycloneii = 1;
|
| 2942 |
|
|
else
|
| 2943 |
|
|
is_cycloneii = 0;
|
| 2944 |
|
|
|
| 2945 |
|
|
IS_FAMILY_CYCLONEII = is_cycloneii;
|
| 2946 |
|
|
end
|
| 2947 |
|
|
endfunction //IS_FAMILY_CYCLONEII
|
| 2948 |
|
|
|
| 2949 |
|
|
function IS_FAMILY_HARDCOPYII;
|
| 2950 |
|
|
input[8*20:1] device;
|
| 2951 |
|
|
reg is_hardcopyii;
|
| 2952 |
|
|
begin
|
| 2953 |
|
|
if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|
| 2954 |
|
|
is_hardcopyii = 1;
|
| 2955 |
|
|
else
|
| 2956 |
|
|
is_hardcopyii = 0;
|
| 2957 |
|
|
|
| 2958 |
|
|
IS_FAMILY_HARDCOPYII = is_hardcopyii;
|
| 2959 |
|
|
end
|
| 2960 |
|
|
endfunction //IS_FAMILY_HARDCOPYII
|
| 2961 |
|
|
|
| 2962 |
|
|
function IS_FAMILY_STRATIXIII;
|
| 2963 |
|
|
input[8*20:1] device;
|
| 2964 |
|
|
reg is_stratixiii;
|
| 2965 |
|
|
begin
|
| 2966 |
|
|
if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|
| 2967 |
|
|
is_stratixiii = 1;
|
| 2968 |
|
|
else
|
| 2969 |
|
|
is_stratixiii = 0;
|
| 2970 |
|
|
|
| 2971 |
|
|
IS_FAMILY_STRATIXIII = is_stratixiii;
|
| 2972 |
|
|
end
|
| 2973 |
|
|
endfunction //IS_FAMILY_STRATIXIII
|
| 2974 |
|
|
|
| 2975 |
|
|
function IS_FAMILY_CYCLONEIII;
|
| 2976 |
|
|
input[8*20:1] device;
|
| 2977 |
|
|
reg is_cycloneiii;
|
| 2978 |
|
|
begin
|
| 2979 |
|
|
if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|
| 2980 |
|
|
is_cycloneiii = 1;
|
| 2981 |
|
|
else
|
| 2982 |
|
|
is_cycloneiii = 0;
|
| 2983 |
|
|
|
| 2984 |
|
|
IS_FAMILY_CYCLONEIII = is_cycloneiii;
|
| 2985 |
|
|
end
|
| 2986 |
|
|
endfunction //IS_FAMILY_CYCLONEIII
|
| 2987 |
|
|
|
| 2988 |
|
|
function IS_FAMILY_STRATIXIV;
|
| 2989 |
|
|
input[8*20:1] device;
|
| 2990 |
|
|
reg is_stratixiv;
|
| 2991 |
|
|
begin
|
| 2992 |
|
|
if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|
| 2993 |
|
|
is_stratixiv = 1;
|
| 2994 |
|
|
else
|
| 2995 |
|
|
is_stratixiv = 0;
|
| 2996 |
|
|
|
| 2997 |
|
|
IS_FAMILY_STRATIXIV = is_stratixiv;
|
| 2998 |
|
|
end
|
| 2999 |
|
|
endfunction //IS_FAMILY_STRATIXIV
|
| 3000 |
|
|
|
| 3001 |
|
|
function IS_FAMILY_ARRIAIIGXGX;
|
| 3002 |
|
|
input[8*20:1] device;
|
| 3003 |
|
|
reg is_arriaiigx;
|
| 3004 |
|
|
begin
|
| 3005 |
|
|
if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|
| 3006 |
|
|
is_arriaiigx = 1;
|
| 3007 |
|
|
else
|
| 3008 |
|
|
is_arriaiigx = 0;
|
| 3009 |
|
|
|
| 3010 |
|
|
IS_FAMILY_ARRIAIIGXGX = is_arriaiigx;
|
| 3011 |
|
|
end
|
| 3012 |
|
|
endfunction //IS_FAMILY_ARRIAIIGXGX
|
| 3013 |
|
|
|
| 3014 |
|
|
function IS_FAMILY_HARDCOPYIII;
|
| 3015 |
|
|
input[8*20:1] device;
|
| 3016 |
|
|
reg is_hardcopyiii;
|
| 3017 |
|
|
begin
|
| 3018 |
|
|
if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|
| 3019 |
|
|
is_hardcopyiii = 1;
|
| 3020 |
|
|
else
|
| 3021 |
|
|
is_hardcopyiii = 0;
|
| 3022 |
|
|
|
| 3023 |
|
|
IS_FAMILY_HARDCOPYIII = is_hardcopyiii;
|
| 3024 |
|
|
end
|
| 3025 |
|
|
endfunction //IS_FAMILY_HARDCOPYIII
|
| 3026 |
|
|
|
| 3027 |
|
|
function IS_FAMILY_HARDCOPYIV;
|
| 3028 |
|
|
input[8*20:1] device;
|
| 3029 |
|
|
reg is_hardcopyiv;
|
| 3030 |
|
|
begin
|
| 3031 |
|
|
if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)"))
|
| 3032 |
|
|
is_hardcopyiv = 1;
|
| 3033 |
|
|
else
|
| 3034 |
|
|
is_hardcopyiv = 0;
|
| 3035 |
|
|
|
| 3036 |
|
|
IS_FAMILY_HARDCOPYIV = is_hardcopyiv;
|
| 3037 |
|
|
end
|
| 3038 |
|
|
endfunction //IS_FAMILY_HARDCOPYIV
|
| 3039 |
|
|
|
| 3040 |
|
|
function IS_FAMILY_CYCLONEIIILS;
|
| 3041 |
|
|
input[8*20:1] device;
|
| 3042 |
|
|
reg is_cycloneiiils;
|
| 3043 |
|
|
begin
|
| 3044 |
|
|
if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|
| 3045 |
|
|
is_cycloneiiils = 1;
|
| 3046 |
|
|
else
|
| 3047 |
|
|
is_cycloneiiils = 0;
|
| 3048 |
|
|
|
| 3049 |
|
|
IS_FAMILY_CYCLONEIIILS = is_cycloneiiils;
|
| 3050 |
|
|
end
|
| 3051 |
|
|
endfunction //IS_FAMILY_CYCLONEIIILS
|
| 3052 |
|
|
|
| 3053 |
|
|
function FEATURE_FAMILY_FLEX10KE;
|
| 3054 |
|
|
input[8*20:1] device;
|
| 3055 |
|
|
reg var_family_flex10ke;
|
| 3056 |
|
|
begin
|
| 3057 |
|
|
if (IS_FAMILY_FLEX10KE(device) || IS_FAMILY_ACEX1K(device) )
|
| 3058 |
|
|
var_family_flex10ke = 1;
|
| 3059 |
|
|
else
|
| 3060 |
|
|
var_family_flex10ke = 0;
|
| 3061 |
|
|
|
| 3062 |
|
|
FEATURE_FAMILY_FLEX10KE = var_family_flex10ke;
|
| 3063 |
|
|
end
|
| 3064 |
|
|
endfunction //FEATURE_FAMILY_FLEX10KE
|
| 3065 |
|
|
|
| 3066 |
|
|
function FEATURE_FAMILY_APEX20K;
|
| 3067 |
|
|
input[8*20:1] device;
|
| 3068 |
|
|
reg var_family_apex20k;
|
| 3069 |
|
|
begin
|
| 3070 |
|
|
if (IS_FAMILY_APEX20K(device) )
|
| 3071 |
|
|
var_family_apex20k = 1;
|
| 3072 |
|
|
else
|
| 3073 |
|
|
var_family_apex20k = 0;
|
| 3074 |
|
|
|
| 3075 |
|
|
FEATURE_FAMILY_APEX20K = var_family_apex20k;
|
| 3076 |
|
|
end
|
| 3077 |
|
|
endfunction //FEATURE_FAMILY_APEX20K
|
| 3078 |
|
|
|
| 3079 |
|
|
function FEATURE_FAMILY_APEX20KE;
|
| 3080 |
|
|
input[8*20:1] device;
|
| 3081 |
|
|
reg var_family_apex20ke;
|
| 3082 |
|
|
begin
|
| 3083 |
|
|
if (IS_FAMILY_APEX20KE(device) || IS_FAMILY_EXCALIBUR_ARM(device) || IS_FAMILY_APEX20KC(device) )
|
| 3084 |
|
|
var_family_apex20ke = 1;
|
| 3085 |
|
|
else
|
| 3086 |
|
|
var_family_apex20ke = 0;
|
| 3087 |
|
|
|
| 3088 |
|
|
FEATURE_FAMILY_APEX20KE = var_family_apex20ke;
|
| 3089 |
|
|
end
|
| 3090 |
|
|
endfunction //FEATURE_FAMILY_APEX20KE
|
| 3091 |
|
|
|
| 3092 |
|
|
function FEATURE_FAMILY_APEXII;
|
| 3093 |
|
|
input[8*20:1] device;
|
| 3094 |
|
|
reg var_family_apexii;
|
| 3095 |
|
|
begin
|
| 3096 |
|
|
if (IS_FAMILY_APEXII(device) || IS_FAMILY_APEXII(device) )
|
| 3097 |
|
|
var_family_apexii = 1;
|
| 3098 |
|
|
else
|
| 3099 |
|
|
var_family_apexii = 0;
|
| 3100 |
|
|
|
| 3101 |
|
|
FEATURE_FAMILY_APEXII = var_family_apexii;
|
| 3102 |
|
|
end
|
| 3103 |
|
|
endfunction //FEATURE_FAMILY_APEXII
|
| 3104 |
|
|
|
| 3105 |
|
|
function FEATURE_FAMILY_STRATIXGX;
|
| 3106 |
|
|
input[8*20:1] device;
|
| 3107 |
|
|
reg var_family_stratixgx;
|
| 3108 |
|
|
begin
|
| 3109 |
|
|
if (IS_FAMILY_STRATIXGX(device) )
|
| 3110 |
|
|
var_family_stratixgx = 1;
|
| 3111 |
|
|
else
|
| 3112 |
|
|
var_family_stratixgx = 0;
|
| 3113 |
|
|
|
| 3114 |
|
|
FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
|
| 3115 |
|
|
end
|
| 3116 |
|
|
endfunction //FEATURE_FAMILY_STRATIXGX
|
| 3117 |
|
|
|
| 3118 |
|
|
function FEATURE_FAMILY_CYCLONE;
|
| 3119 |
|
|
input[8*20:1] device;
|
| 3120 |
|
|
reg var_family_cyclone;
|
| 3121 |
|
|
begin
|
| 3122 |
|
|
if (IS_FAMILY_CYCLONE(device) )
|
| 3123 |
|
|
var_family_cyclone = 1;
|
| 3124 |
|
|
else
|
| 3125 |
|
|
var_family_cyclone = 0;
|
| 3126 |
|
|
|
| 3127 |
|
|
FEATURE_FAMILY_CYCLONE = var_family_cyclone;
|
| 3128 |
|
|
end
|
| 3129 |
|
|
endfunction //FEATURE_FAMILY_CYCLONE
|
| 3130 |
|
|
|
| 3131 |
|
|
function FEATURE_FAMILY_STRATIXIIGX;
|
| 3132 |
|
|
input[8*20:1] device;
|
| 3133 |
|
|
reg var_family_stratixiigx;
|
| 3134 |
|
|
begin
|
| 3135 |
|
|
if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) )
|
| 3136 |
|
|
var_family_stratixiigx = 1;
|
| 3137 |
|
|
else
|
| 3138 |
|
|
var_family_stratixiigx = 0;
|
| 3139 |
|
|
|
| 3140 |
|
|
FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx;
|
| 3141 |
|
|
end
|
| 3142 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIIGX
|
| 3143 |
|
|
|
| 3144 |
|
|
function FEATURE_FAMILY_STRATIXIII;
|
| 3145 |
|
|
input[8*20:1] device;
|
| 3146 |
|
|
reg var_family_stratixiii;
|
| 3147 |
|
|
begin
|
| 3148 |
|
|
if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) )
|
| 3149 |
|
|
var_family_stratixiii = 1;
|
| 3150 |
|
|
else
|
| 3151 |
|
|
var_family_stratixiii = 0;
|
| 3152 |
|
|
|
| 3153 |
|
|
FEATURE_FAMILY_STRATIXIII = var_family_stratixiii;
|
| 3154 |
|
|
end
|
| 3155 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIII
|
| 3156 |
|
|
|
| 3157 |
|
|
function FEATURE_FAMILY_STRATIXII;
|
| 3158 |
|
|
input[8*20:1] device;
|
| 3159 |
|
|
reg var_family_stratixii;
|
| 3160 |
|
|
begin
|
| 3161 |
|
|
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) )
|
| 3162 |
|
|
var_family_stratixii = 1;
|
| 3163 |
|
|
else
|
| 3164 |
|
|
var_family_stratixii = 0;
|
| 3165 |
|
|
|
| 3166 |
|
|
FEATURE_FAMILY_STRATIXII = var_family_stratixii;
|
| 3167 |
|
|
end
|
| 3168 |
|
|
endfunction //FEATURE_FAMILY_STRATIXII
|
| 3169 |
|
|
|
| 3170 |
|
|
function FEATURE_FAMILY_CYCLONEIII;
|
| 3171 |
|
|
input[8*20:1] device;
|
| 3172 |
|
|
reg var_family_cycloneiii;
|
| 3173 |
|
|
begin
|
| 3174 |
|
|
if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) )
|
| 3175 |
|
|
var_family_cycloneiii = 1;
|
| 3176 |
|
|
else
|
| 3177 |
|
|
var_family_cycloneiii = 0;
|
| 3178 |
|
|
|
| 3179 |
|
|
FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii;
|
| 3180 |
|
|
end
|
| 3181 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIII
|
| 3182 |
|
|
|
| 3183 |
|
|
function FEATURE_FAMILY_STRATIX_HC;
|
| 3184 |
|
|
input[8*20:1] device;
|
| 3185 |
|
|
reg var_family_stratix_hc;
|
| 3186 |
|
|
begin
|
| 3187 |
|
|
if (IS_FAMILY_HARDCOPYSTRATIX(device) )
|
| 3188 |
|
|
var_family_stratix_hc = 1;
|
| 3189 |
|
|
else
|
| 3190 |
|
|
var_family_stratix_hc = 0;
|
| 3191 |
|
|
|
| 3192 |
|
|
FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
|
| 3193 |
|
|
end
|
| 3194 |
|
|
endfunction //FEATURE_FAMILY_STRATIX_HC
|
| 3195 |
|
|
|
| 3196 |
|
|
function FEATURE_FAMILY_HARDCOPYII;
|
| 3197 |
|
|
input[8*20:1] device;
|
| 3198 |
|
|
reg var_family_hardcopyii;
|
| 3199 |
|
|
begin
|
| 3200 |
|
|
if (IS_FAMILY_HARDCOPYII(device) )
|
| 3201 |
|
|
var_family_hardcopyii = 1;
|
| 3202 |
|
|
else
|
| 3203 |
|
|
var_family_hardcopyii = 0;
|
| 3204 |
|
|
|
| 3205 |
|
|
FEATURE_FAMILY_HARDCOPYII = var_family_hardcopyii;
|
| 3206 |
|
|
end
|
| 3207 |
|
|
endfunction //FEATURE_FAMILY_HARDCOPYII
|
| 3208 |
|
|
|
| 3209 |
|
|
function FEATURE_FAMILY_STRATIX;
|
| 3210 |
|
|
input[8*20:1] device;
|
| 3211 |
|
|
reg var_family_stratix;
|
| 3212 |
|
|
begin
|
| 3213 |
|
|
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
|
| 3214 |
|
|
var_family_stratix = 1;
|
| 3215 |
|
|
else
|
| 3216 |
|
|
var_family_stratix = 0;
|
| 3217 |
|
|
|
| 3218 |
|
|
FEATURE_FAMILY_STRATIX = var_family_stratix;
|
| 3219 |
|
|
end
|
| 3220 |
|
|
endfunction //FEATURE_FAMILY_STRATIX
|
| 3221 |
|
|
|
| 3222 |
|
|
function FEATURE_FAMILY_MAXII;
|
| 3223 |
|
|
input[8*20:1] device;
|
| 3224 |
|
|
reg var_family_maxii;
|
| 3225 |
|
|
begin
|
| 3226 |
|
|
if (IS_FAMILY_MAXII(device) )
|
| 3227 |
|
|
var_family_maxii = 1;
|
| 3228 |
|
|
else
|
| 3229 |
|
|
var_family_maxii = 0;
|
| 3230 |
|
|
|
| 3231 |
|
|
FEATURE_FAMILY_MAXII = var_family_maxii;
|
| 3232 |
|
|
end
|
| 3233 |
|
|
endfunction //FEATURE_FAMILY_MAXII
|
| 3234 |
|
|
|
| 3235 |
|
|
function FEATURE_FAMILY_CYCLONEII;
|
| 3236 |
|
|
input[8*20:1] device;
|
| 3237 |
|
|
reg var_family_cycloneii;
|
| 3238 |
|
|
begin
|
| 3239 |
|
|
if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
|
| 3240 |
|
|
var_family_cycloneii = 1;
|
| 3241 |
|
|
else
|
| 3242 |
|
|
var_family_cycloneii = 0;
|
| 3243 |
|
|
|
| 3244 |
|
|
FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
|
| 3245 |
|
|
end
|
| 3246 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEII
|
| 3247 |
|
|
|
| 3248 |
|
|
function FEATURE_FAMILY_STRATIXIV;
|
| 3249 |
|
|
input[8*20:1] device;
|
| 3250 |
|
|
reg var_family_stratixiv;
|
| 3251 |
|
|
begin
|
| 3252 |
|
|
if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGXGX(device) || IS_FAMILY_HARDCOPYIV(device) )
|
| 3253 |
|
|
var_family_stratixiv = 1;
|
| 3254 |
|
|
else
|
| 3255 |
|
|
var_family_stratixiv = 0;
|
| 3256 |
|
|
|
| 3257 |
|
|
FEATURE_FAMILY_STRATIXIV = var_family_stratixiv;
|
| 3258 |
|
|
end
|
| 3259 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIV
|
| 3260 |
|
|
|
| 3261 |
|
|
function FEATURE_FAMILY_ARRIAIIGX;
|
| 3262 |
|
|
input[8*20:1] device;
|
| 3263 |
|
|
reg var_family_arriaiigx;
|
| 3264 |
|
|
begin
|
| 3265 |
|
|
if (IS_FAMILY_ARRIAIIGXGX(device) )
|
| 3266 |
|
|
var_family_arriaiigx = 1;
|
| 3267 |
|
|
else
|
| 3268 |
|
|
var_family_arriaiigx = 0;
|
| 3269 |
|
|
|
| 3270 |
|
|
FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx;
|
| 3271 |
|
|
end
|
| 3272 |
|
|
endfunction //FEATURE_FAMILY_ARRIAIIGX
|
| 3273 |
|
|
|
| 3274 |
|
|
function FEATURE_FAMILY_BASE_STRATIXII;
|
| 3275 |
|
|
input[8*20:1] device;
|
| 3276 |
|
|
reg var_family_base_stratixii;
|
| 3277 |
|
|
begin
|
| 3278 |
|
|
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
|
| 3279 |
|
|
var_family_base_stratixii = 1;
|
| 3280 |
|
|
else
|
| 3281 |
|
|
var_family_base_stratixii = 0;
|
| 3282 |
|
|
|
| 3283 |
|
|
FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii;
|
| 3284 |
|
|
end
|
| 3285 |
|
|
endfunction //FEATURE_FAMILY_BASE_STRATIXII
|
| 3286 |
|
|
|
| 3287 |
|
|
function FEATURE_FAMILY_BASE_STRATIX;
|
| 3288 |
|
|
input[8*20:1] device;
|
| 3289 |
|
|
reg var_family_base_stratix;
|
| 3290 |
|
|
begin
|
| 3291 |
|
|
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) || IS_FAMILY_HARDCOPYSTRATIX(device) )
|
| 3292 |
|
|
var_family_base_stratix = 1;
|
| 3293 |
|
|
else
|
| 3294 |
|
|
var_family_base_stratix = 0;
|
| 3295 |
|
|
|
| 3296 |
|
|
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
|
| 3297 |
|
|
end
|
| 3298 |
|
|
endfunction //FEATURE_FAMILY_BASE_STRATIX
|
| 3299 |
|
|
|
| 3300 |
|
|
function FEATURE_FAMILY_BASE_CYCLONEII;
|
| 3301 |
|
|
input[8*20:1] device;
|
| 3302 |
|
|
reg var_family_base_cycloneii;
|
| 3303 |
|
|
begin
|
| 3304 |
|
|
if (IS_FAMILY_CYCLONEII(device) )
|
| 3305 |
|
|
var_family_base_cycloneii = 1;
|
| 3306 |
|
|
else
|
| 3307 |
|
|
var_family_base_cycloneii = 0;
|
| 3308 |
|
|
|
| 3309 |
|
|
FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii;
|
| 3310 |
|
|
end
|
| 3311 |
|
|
endfunction //FEATURE_FAMILY_BASE_CYCLONEII
|
| 3312 |
|
|
|
| 3313 |
|
|
function FEATURE_FAMILY_BASE_CYCLONE;
|
| 3314 |
|
|
input[8*20:1] device;
|
| 3315 |
|
|
reg var_family_base_cyclone;
|
| 3316 |
|
|
begin
|
| 3317 |
|
|
if (IS_FAMILY_CYCLONE(device) )
|
| 3318 |
|
|
var_family_base_cyclone = 1;
|
| 3319 |
|
|
else
|
| 3320 |
|
|
var_family_base_cyclone = 0;
|
| 3321 |
|
|
|
| 3322 |
|
|
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
|
| 3323 |
|
|
end
|
| 3324 |
|
|
endfunction //FEATURE_FAMILY_BASE_CYCLONE
|
| 3325 |
|
|
|
| 3326 |
|
|
function FEATURE_FAMILY_HAS_MEGARAM;
|
| 3327 |
|
|
input[8*20:1] device;
|
| 3328 |
|
|
reg var_family_has_megaram;
|
| 3329 |
|
|
begin
|
| 3330 |
|
|
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_ARRIAIIGX(device) )
|
| 3331 |
|
|
var_family_has_megaram = 1;
|
| 3332 |
|
|
else
|
| 3333 |
|
|
var_family_has_megaram = 0;
|
| 3334 |
|
|
|
| 3335 |
|
|
FEATURE_FAMILY_HAS_MEGARAM = var_family_has_megaram;
|
| 3336 |
|
|
end
|
| 3337 |
|
|
endfunction //FEATURE_FAMILY_HAS_MEGARAM
|
| 3338 |
|
|
|
| 3339 |
|
|
function FEATURE_FAMILY_HAS_M512;
|
| 3340 |
|
|
input[8*20:1] device;
|
| 3341 |
|
|
reg var_family_has_m512;
|
| 3342 |
|
|
begin
|
| 3343 |
|
|
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || IS_FAMILY_STRATIXII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
|
| 3344 |
|
|
var_family_has_m512 = 1;
|
| 3345 |
|
|
else
|
| 3346 |
|
|
var_family_has_m512 = 0;
|
| 3347 |
|
|
|
| 3348 |
|
|
FEATURE_FAMILY_HAS_M512 = var_family_has_m512;
|
| 3349 |
|
|
end
|
| 3350 |
|
|
endfunction //FEATURE_FAMILY_HAS_M512
|
| 3351 |
|
|
|
| 3352 |
|
|
function FEATURE_FAMILY_HAS_LUTRAM;
|
| 3353 |
|
|
input[8*20:1] device;
|
| 3354 |
|
|
reg var_family_has_lutram;
|
| 3355 |
|
|
begin
|
| 3356 |
|
|
if (FEATURE_FAMILY_STRATIXIII(device) )
|
| 3357 |
|
|
var_family_has_lutram = 1;
|
| 3358 |
|
|
else
|
| 3359 |
|
|
var_family_has_lutram = 0;
|
| 3360 |
|
|
|
| 3361 |
|
|
FEATURE_FAMILY_HAS_LUTRAM = var_family_has_lutram;
|
| 3362 |
|
|
end
|
| 3363 |
|
|
endfunction //FEATURE_FAMILY_HAS_LUTRAM
|
| 3364 |
|
|
|
| 3365 |
|
|
function FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM;
|
| 3366 |
|
|
input[8*20:1] device;
|
| 3367 |
|
|
reg var_family_has_stratixi_style_ram;
|
| 3368 |
|
|
begin
|
| 3369 |
|
|
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) )
|
| 3370 |
|
|
var_family_has_stratixi_style_ram = 1;
|
| 3371 |
|
|
else
|
| 3372 |
|
|
var_family_has_stratixi_style_ram = 0;
|
| 3373 |
|
|
|
| 3374 |
|
|
FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM = var_family_has_stratixi_style_ram;
|
| 3375 |
|
|
end
|
| 3376 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM
|
| 3377 |
|
|
|
| 3378 |
|
|
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
|
| 3379 |
|
|
input[8*20:1] device;
|
| 3380 |
|
|
reg var_family_has_stratixii_style_ram;
|
| 3381 |
|
|
begin
|
| 3382 |
|
|
if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
|
| 3383 |
|
|
var_family_has_stratixii_style_ram = 1;
|
| 3384 |
|
|
else
|
| 3385 |
|
|
var_family_has_stratixii_style_ram = 0;
|
| 3386 |
|
|
|
| 3387 |
|
|
FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
|
| 3388 |
|
|
end
|
| 3389 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
|
| 3390 |
|
|
|
| 3391 |
|
|
function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM;
|
| 3392 |
|
|
input[8*20:1] device;
|
| 3393 |
|
|
reg var_family_has_stratixiii_style_ram;
|
| 3394 |
|
|
begin
|
| 3395 |
|
|
if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
|
| 3396 |
|
|
var_family_has_stratixiii_style_ram = 1;
|
| 3397 |
|
|
else
|
| 3398 |
|
|
var_family_has_stratixiii_style_ram = 0;
|
| 3399 |
|
|
|
| 3400 |
|
|
FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram;
|
| 3401 |
|
|
end
|
| 3402 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM
|
| 3403 |
|
|
|
| 3404 |
|
|
function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL;
|
| 3405 |
|
|
input[8*20:1] device;
|
| 3406 |
|
|
reg var_family_has_stratix_style_pll;
|
| 3407 |
|
|
begin
|
| 3408 |
|
|
if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) )
|
| 3409 |
|
|
var_family_has_stratix_style_pll = 1;
|
| 3410 |
|
|
else
|
| 3411 |
|
|
var_family_has_stratix_style_pll = 0;
|
| 3412 |
|
|
|
| 3413 |
|
|
FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll;
|
| 3414 |
|
|
end
|
| 3415 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL
|
| 3416 |
|
|
|
| 3417 |
|
|
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL;
|
| 3418 |
|
|
input[8*20:1] device;
|
| 3419 |
|
|
reg var_family_has_stratixii_style_pll;
|
| 3420 |
|
|
begin
|
| 3421 |
|
|
if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) )
|
| 3422 |
|
|
var_family_has_stratixii_style_pll = 1;
|
| 3423 |
|
|
else
|
| 3424 |
|
|
var_family_has_stratixii_style_pll = 0;
|
| 3425 |
|
|
|
| 3426 |
|
|
FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll;
|
| 3427 |
|
|
end
|
| 3428 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL
|
| 3429 |
|
|
|
| 3430 |
|
|
function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
|
| 3431 |
|
|
input[8*20:1] device;
|
| 3432 |
|
|
reg var_family_has_inverted_output_ddio;
|
| 3433 |
|
|
begin
|
| 3434 |
|
|
if (FEATURE_FAMILY_CYCLONEII(device) )
|
| 3435 |
|
|
var_family_has_inverted_output_ddio = 1;
|
| 3436 |
|
|
else
|
| 3437 |
|
|
var_family_has_inverted_output_ddio = 0;
|
| 3438 |
|
|
|
| 3439 |
|
|
FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
|
| 3440 |
|
|
end
|
| 3441 |
|
|
endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
|
| 3442 |
|
|
|
| 3443 |
|
|
function IS_VALID_FAMILY;
|
| 3444 |
|
|
input[8*20:1] device;
|
| 3445 |
|
|
reg is_valid;
|
| 3446 |
|
|
begin
|
| 3447 |
|
|
if (((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k"))
|
| 3448 |
|
|
|| ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael"))
|
| 3449 |
|
|
|| ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc"))
|
| 3450 |
|
|
|| ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke"))
|
| 3451 |
|
|
|| ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf"))
|
| 3452 |
|
|
|| ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur"))
|
| 3453 |
|
|
|| ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke"))
|
| 3454 |
|
|
|| ((device == "FLEX10K") || (device == "flex10k") || (device == "FLEX 10K") || (device == "flex 10k"))
|
| 3455 |
|
|
|| ((device == "FLEX10KA") || (device == "flex10ka") || (device == "FLEX 10KA") || (device == "flex 10ka"))
|
| 3456 |
|
|
|| ((device == "FLEX6000") || (device == "flex6000") || (device == "FLEX 6000") || (device == "flex 6000") || (device == "FLEX6K") || (device == "flex6k"))
|
| 3457 |
|
|
|| ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|
| 3458 |
|
|
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|
| 3459 |
|
|
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|
| 3460 |
|
|
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|
| 3461 |
|
|
|| ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
|
| 3462 |
|
|
|| ((device == "Mercury") || (device == "MERCURY") || (device == "mercury") || (device == "DALI") || (device == "dali"))
|
| 3463 |
|
|
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|
| 3464 |
|
|
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|
| 3465 |
|
|
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|
| 3466 |
|
|
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|
| 3467 |
|
|
|| ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix"))
|
| 3468 |
|
|
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|
| 3469 |
|
|
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|
| 3470 |
|
|
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|
| 3471 |
|
|
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
|
| 3472 |
|
|
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|
| 3473 |
|
|
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|
| 3474 |
|
|
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|
| 3475 |
|
|
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|
| 3476 |
|
|
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|
| 3477 |
|
|
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|
| 3478 |
|
|
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)"))
|
| 3479 |
|
|
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")))
|
| 3480 |
|
|
is_valid = 1;
|
| 3481 |
|
|
else
|
| 3482 |
|
|
is_valid = 0;
|
| 3483 |
|
|
|
| 3484 |
|
|
IS_VALID_FAMILY = is_valid;
|
| 3485 |
|
|
end
|
| 3486 |
|
|
endfunction // IS_VALID_FAMILY
|
| 3487 |
|
|
|
| 3488 |
|
|
|
| 3489 |
|
|
endmodule // ALTERA_DEVICE_FAMILIES
|
| 3490 |
|
|
|
| 3491 |
|
|
|
| 3492 |
|
|
// BEGINNING OF MODULE
|
| 3493 |
|
|
`timescale 1 ps / 1 ps
|
| 3494 |
|
|
|
| 3495 |
|
|
`define TRUE 1
|
| 3496 |
|
|
`define FALSE 0
|
| 3497 |
|
|
`define NULL 0
|
| 3498 |
|
|
`define EOF -1
|
| 3499 |
|
|
`define MAX_BUFFER_SZ 2048
|
| 3500 |
|
|
`define MAX_NAME_SZ 256
|
| 3501 |
|
|
`define MAX_WIDTH 256
|
| 3502 |
|
|
`define COLON ":"
|
| 3503 |
|
|
`define DOT "."
|
| 3504 |
|
|
`define NEWLINE "\n"
|
| 3505 |
|
|
`define CARRIAGE_RETURN 8'h0D
|
| 3506 |
|
|
`define SPACE " "
|
| 3507 |
|
|
`define TAB "\t"
|
| 3508 |
|
|
`define OPEN_BRACKET "["
|
| 3509 |
|
|
`define CLOSE_BRACKET "]"
|
| 3510 |
|
|
`define OFFSET 9
|
| 3511 |
|
|
`define H10 8'h10
|
| 3512 |
|
|
`define H10000 20'h10000
|
| 3513 |
|
|
`define AWORD 8
|
| 3514 |
|
|
`define MASK15 32'h000000FF
|
| 3515 |
|
|
`define EXT_STR "ver"
|
| 3516 |
|
|
`define PERCENT "%"
|
| 3517 |
|
|
`define MINUS "-"
|
| 3518 |
|
|
`define SEMICOLON ";"
|
| 3519 |
|
|
`define EQUAL "="
|
| 3520 |
|
|
|
| 3521 |
|
|
// MODULE DECLARATION
|
| 3522 |
|
|
module ALTERA_MF_MEMORY_INITIALIZATION;
|
| 3523 |
|
|
|
| 3524 |
|
|
/****************************************************************/
|
| 3525 |
|
|
/* convert uppercase character values to lowercase. */
|
| 3526 |
|
|
/****************************************************************/
|
| 3527 |
|
|
function [8:1] tolower;
|
| 3528 |
|
|
input [8:1] given_character;
|
| 3529 |
|
|
reg [8:1] conv_char;
|
| 3530 |
|
|
|
| 3531 |
|
|
begin
|
| 3532 |
|
|
if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
|
| 3533 |
|
|
begin
|
| 3534 |
|
|
conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
|
| 3535 |
|
|
tolower = conv_char;
|
| 3536 |
|
|
end
|
| 3537 |
|
|
else
|
| 3538 |
|
|
tolower = given_character;
|
| 3539 |
|
|
end
|
| 3540 |
|
|
endfunction
|
| 3541 |
|
|
|
| 3542 |
|
|
/****************************************************************/
|
| 3543 |
|
|
/* Read in Altera-mif format data to verilog format data. */
|
| 3544 |
|
|
/****************************************************************/
|
| 3545 |
|
|
task convert_mif2ver;
|
| 3546 |
|
|
input[`MAX_NAME_SZ*8 : 1] in_file;
|
| 3547 |
|
|
input width;
|
| 3548 |
|
|
output [`MAX_NAME_SZ*8 : 1] out_file;
|
| 3549 |
|
|
reg [`MAX_NAME_SZ*8 : 1] in_file;
|
| 3550 |
|
|
reg [`MAX_NAME_SZ*8 : 1] out_file;
|
| 3551 |
|
|
reg [`MAX_NAME_SZ*8 : 1] buffer;
|
| 3552 |
|
|
reg [`MAX_WIDTH : 0] memory_data1, memory_data2;
|
| 3553 |
|
|
reg [8 : 1] c;
|
| 3554 |
|
|
reg [3 : 0] hex, tmp_char;
|
| 3555 |
|
|
reg [24 : 1] address_radix, data_radix;
|
| 3556 |
|
|
reg get_width;
|
| 3557 |
|
|
reg get_depth;
|
| 3558 |
|
|
reg get_data_radix;
|
| 3559 |
|
|
reg get_address_radix;
|
| 3560 |
|
|
reg width_found;
|
| 3561 |
|
|
reg depth_found;
|
| 3562 |
|
|
reg data_radix_found;
|
| 3563 |
|
|
reg address_radix_found;
|
| 3564 |
|
|
reg get_address_data_pairs;
|
| 3565 |
|
|
reg get_address;
|
| 3566 |
|
|
reg get_data;
|
| 3567 |
|
|
reg display_address;
|
| 3568 |
|
|
reg invalid_address;
|
| 3569 |
|
|
reg get_start_address;
|
| 3570 |
|
|
reg get_end_address;
|
| 3571 |
|
|
reg done;
|
| 3572 |
|
|
reg error_status;
|
| 3573 |
|
|
reg first_rec;
|
| 3574 |
|
|
reg last_rec;
|
| 3575 |
|
|
|
| 3576 |
|
|
integer width;
|
| 3577 |
|
|
integer memory_width, memory_depth;
|
| 3578 |
|
|
integer value;
|
| 3579 |
|
|
integer ifp, ofp, r, r2;
|
| 3580 |
|
|
integer i, j, k, m, n;
|
| 3581 |
|
|
|
| 3582 |
|
|
integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ;
|
| 3583 |
|
|
integer start_address, end_address;
|
| 3584 |
|
|
integer line_no;
|
| 3585 |
|
|
integer character_count;
|
| 3586 |
|
|
integer comment_with_percent_found;
|
| 3587 |
|
|
integer comment_with_double_minus_found;
|
| 3588 |
|
|
|
| 3589 |
|
|
begin
|
| 3590 |
|
|
`ifdef NO_PLI
|
| 3591 |
|
|
`else
|
| 3592 |
|
|
`ifdef USE_RIF
|
| 3593 |
|
|
`else
|
| 3594 |
|
|
done = `FALSE;
|
| 3595 |
|
|
error_status = `FALSE;
|
| 3596 |
|
|
first_rec = `FALSE;
|
| 3597 |
|
|
last_rec = `FALSE;
|
| 3598 |
|
|
comment_with_percent_found = `FALSE;
|
| 3599 |
|
|
comment_with_double_minus_found = `FALSE;
|
| 3600 |
|
|
|
| 3601 |
|
|
off_addr= 0;
|
| 3602 |
|
|
nn= 0;
|
| 3603 |
|
|
address = 0;
|
| 3604 |
|
|
start_address = 0;
|
| 3605 |
|
|
end_address = 0;
|
| 3606 |
|
|
tt= 0;
|
| 3607 |
|
|
cc= 0;
|
| 3608 |
|
|
aah= 0;
|
| 3609 |
|
|
aal= 0;
|
| 3610 |
|
|
dd= 0;
|
| 3611 |
|
|
sum = 0;
|
| 3612 |
|
|
line_no = 1;
|
| 3613 |
|
|
c = 0;
|
| 3614 |
|
|
hex = 0;
|
| 3615 |
|
|
value = 0;
|
| 3616 |
|
|
buffer = "";
|
| 3617 |
|
|
character_count = 0;
|
| 3618 |
|
|
memory_width = 0;
|
| 3619 |
|
|
memory_depth = 0;
|
| 3620 |
|
|
memory_data1 = {(`MAX_WIDTH+1) {1'b0}};
|
| 3621 |
|
|
memory_data2 = {(`MAX_WIDTH+1) {1'b0}};
|
| 3622 |
|
|
address_radix = "hex";
|
| 3623 |
|
|
data_radix = "hex";
|
| 3624 |
|
|
get_width = `FALSE;
|
| 3625 |
|
|
get_depth = `FALSE;
|
| 3626 |
|
|
get_data_radix = `FALSE;
|
| 3627 |
|
|
get_address_radix = `FALSE;
|
| 3628 |
|
|
width_found = `FALSE;
|
| 3629 |
|
|
depth_found = `FALSE;
|
| 3630 |
|
|
data_radix_found = `FALSE;
|
| 3631 |
|
|
address_radix_found = `FALSE;
|
| 3632 |
|
|
get_address_data_pairs = `FALSE;
|
| 3633 |
|
|
display_address = `FALSE;
|
| 3634 |
|
|
invalid_address = `FALSE;
|
| 3635 |
|
|
get_start_address = `FALSE;
|
| 3636 |
|
|
get_end_address = `FALSE;
|
| 3637 |
|
|
|
| 3638 |
|
|
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
|
| 3639 |
|
|
out_file = in_file;
|
| 3640 |
|
|
else
|
| 3641 |
|
|
begin
|
| 3642 |
|
|
ifp = $fopen(in_file, "r");
|
| 3643 |
|
|
|
| 3644 |
|
|
if (ifp == `NULL)
|
| 3645 |
|
|
begin
|
| 3646 |
|
|
$display("ERROR: cannot read %0s.", in_file);
|
| 3647 |
|
|
done = `TRUE;
|
| 3648 |
|
|
end
|
| 3649 |
|
|
|
| 3650 |
|
|
out_file = in_file;
|
| 3651 |
|
|
|
| 3652 |
|
|
if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF"))
|
| 3653 |
|
|
out_file[3*8 : 1] = `EXT_STR;
|
| 3654 |
|
|
else
|
| 3655 |
|
|
begin
|
| 3656 |
|
|
$display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file);
|
| 3657 |
|
|
done = `TRUE;
|
| 3658 |
|
|
end
|
| 3659 |
|
|
|
| 3660 |
|
|
if (!done)
|
| 3661 |
|
|
begin
|
| 3662 |
|
|
ofp = $fopen(out_file, "w");
|
| 3663 |
|
|
|
| 3664 |
|
|
if (ofp == `NULL)
|
| 3665 |
|
|
begin
|
| 3666 |
|
|
$display("ERROR : cannot write %0s.", out_file);
|
| 3667 |
|
|
done = `TRUE;
|
| 3668 |
|
|
end
|
| 3669 |
|
|
end
|
| 3670 |
|
|
|
| 3671 |
|
|
while((!done) && (!error_status))
|
| 3672 |
|
|
begin : READER
|
| 3673 |
|
|
|
| 3674 |
|
|
r = $fgetc(ifp);
|
| 3675 |
|
|
|
| 3676 |
|
|
if (r == `EOF)
|
| 3677 |
|
|
begin
|
| 3678 |
|
|
// to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising
|
| 3679 |
|
|
if(!first_rec)
|
| 3680 |
|
|
begin
|
| 3681 |
|
|
error_status = `TRUE;
|
| 3682 |
|
|
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
|
| 3683 |
|
|
end
|
| 3684 |
|
|
else if (!get_address_data_pairs)
|
| 3685 |
|
|
begin
|
| 3686 |
|
|
error_status = `TRUE;
|
| 3687 |
|
|
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
|
| 3688 |
|
|
end
|
| 3689 |
|
|
else if(!last_rec)
|
| 3690 |
|
|
begin
|
| 3691 |
|
|
error_status = `TRUE;
|
| 3692 |
|
|
$display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no);
|
| 3693 |
|
|
end
|
| 3694 |
|
|
done = `TRUE;
|
| 3695 |
|
|
end
|
| 3696 |
|
|
else if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
|
| 3697 |
|
|
begin
|
| 3698 |
|
|
if ((buffer == "contentbegin") && (get_address_data_pairs == `FALSE))
|
| 3699 |
|
|
begin
|
| 3700 |
|
|
get_address_data_pairs = `TRUE;
|
| 3701 |
|
|
get_address = `TRUE;
|
| 3702 |
|
|
buffer = "";
|
| 3703 |
|
|
end
|
| 3704 |
|
|
else if (buffer == "content")
|
| 3705 |
|
|
begin
|
| 3706 |
|
|
// continue to next character
|
| 3707 |
|
|
end
|
| 3708 |
|
|
else
|
| 3709 |
|
|
if (buffer != "")
|
| 3710 |
|
|
begin
|
| 3711 |
|
|
// found invalid syntax in the particular line.
|
| 3712 |
|
|
error_status = `TRUE;
|
| 3713 |
|
|
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
|
| 3714 |
|
|
disable READER;
|
| 3715 |
|
|
end
|
| 3716 |
|
|
line_no = line_no +1;
|
| 3717 |
|
|
|
| 3718 |
|
|
end
|
| 3719 |
|
|
else if ((r == `SPACE) || (r == `TAB))
|
| 3720 |
|
|
begin
|
| 3721 |
|
|
// continue to next character;
|
| 3722 |
|
|
end
|
| 3723 |
|
|
else if (r == `PERCENT)
|
| 3724 |
|
|
begin
|
| 3725 |
|
|
// Ignore all the characters which which is part of comment.
|
| 3726 |
|
|
r = $fgetc(ifp);
|
| 3727 |
|
|
|
| 3728 |
|
|
while ((r != `PERCENT) && (r != `NEWLINE) && (r != `CARRIAGE_RETURN))
|
| 3729 |
|
|
begin
|
| 3730 |
|
|
r = $fgetc(ifp);
|
| 3731 |
|
|
end
|
| 3732 |
|
|
|
| 3733 |
|
|
if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
|
| 3734 |
|
|
begin
|
| 3735 |
|
|
line_no = line_no +1;
|
| 3736 |
|
|
|
| 3737 |
|
|
if ((buffer == "contentbegin") && (get_address_data_pairs == `FALSE))
|
| 3738 |
|
|
begin
|
| 3739 |
|
|
get_address_data_pairs = `TRUE;
|
| 3740 |
|
|
get_address = `TRUE;
|
| 3741 |
|
|
buffer = "";
|
| 3742 |
|
|
end
|
| 3743 |
|
|
end
|
| 3744 |
|
|
end
|
| 3745 |
|
|
else if (r == `MINUS)
|
| 3746 |
|
|
begin
|
| 3747 |
|
|
r = $fgetc(ifp);
|
| 3748 |
|
|
if (r == `MINUS)
|
| 3749 |
|
|
begin
|
| 3750 |
|
|
// Ignore all the characters which which is part of comment.
|
| 3751 |
|
|
r = $fgetc(ifp);
|
| 3752 |
|
|
|
| 3753 |
|
|
while ((r != `NEWLINE) && (r != `CARRIAGE_RETURN))
|
| 3754 |
|
|
begin
|
| 3755 |
|
|
r = $fgetc(ifp);
|
| 3756 |
|
|
|
| 3757 |
|
|
end
|
| 3758 |
|
|
|
| 3759 |
|
|
if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
|
| 3760 |
|
|
begin
|
| 3761 |
|
|
line_no = line_no +1;
|
| 3762 |
|
|
|
| 3763 |
|
|
if ((buffer == "contentbegin") && (get_address_data_pairs == `FALSE))
|
| 3764 |
|
|
begin
|
| 3765 |
|
|
get_address_data_pairs = `TRUE;
|
| 3766 |
|
|
get_address = `TRUE;
|
| 3767 |
|
|
buffer = "";
|
| 3768 |
|
|
end
|
| 3769 |
|
|
end
|
| 3770 |
|
|
end
|
| 3771 |
|
|
else
|
| 3772 |
|
|
begin
|
| 3773 |
|
|
error_status = `TRUE;
|
| 3774 |
|
|
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
|
| 3775 |
|
|
done = `TRUE;
|
| 3776 |
|
|
disable READER;
|
| 3777 |
|
|
end
|
| 3778 |
|
|
end
|
| 3779 |
|
|
else if (r == `EQUAL)
|
| 3780 |
|
|
begin
|
| 3781 |
|
|
if (buffer == "width")
|
| 3782 |
|
|
begin
|
| 3783 |
|
|
if (width_found == `FALSE)
|
| 3784 |
|
|
begin
|
| 3785 |
|
|
get_width = `TRUE;
|
| 3786 |
|
|
buffer = "";
|
| 3787 |
|
|
end
|
| 3788 |
|
|
else
|
| 3789 |
|
|
begin
|
| 3790 |
|
|
error_status = `TRUE;
|
| 3791 |
|
|
$display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no);
|
| 3792 |
|
|
end
|
| 3793 |
|
|
end
|
| 3794 |
|
|
else if (buffer == "depth")
|
| 3795 |
|
|
begin
|
| 3796 |
|
|
get_depth = `TRUE;
|
| 3797 |
|
|
buffer = "";
|
| 3798 |
|
|
end
|
| 3799 |
|
|
else if (buffer == "data_radix")
|
| 3800 |
|
|
begin
|
| 3801 |
|
|
get_data_radix = `TRUE;
|
| 3802 |
|
|
buffer = "";
|
| 3803 |
|
|
end
|
| 3804 |
|
|
else if (buffer == "address_radix")
|
| 3805 |
|
|
begin
|
| 3806 |
|
|
get_address_radix = `TRUE;
|
| 3807 |
|
|
buffer = "";
|
| 3808 |
|
|
end
|
| 3809 |
|
|
else
|
| 3810 |
|
|
begin
|
| 3811 |
|
|
error_status = `TRUE;
|
| 3812 |
|
|
$display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer);
|
| 3813 |
|
|
end
|
| 3814 |
|
|
end
|
| 3815 |
|
|
else if (r == `COLON)
|
| 3816 |
|
|
begin
|
| 3817 |
|
|
if (!get_address_data_pairs)
|
| 3818 |
|
|
begin
|
| 3819 |
|
|
error_status = `TRUE;
|
| 3820 |
|
|
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
|
| 3821 |
|
|
end
|
| 3822 |
|
|
else if (invalid_address == `TRUE)
|
| 3823 |
|
|
begin
|
| 3824 |
|
|
error_status = `TRUE;
|
| 3825 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 3826 |
|
|
end
|
| 3827 |
|
|
begin
|
| 3828 |
|
|
get_address = `FALSE;
|
| 3829 |
|
|
get_data = `TRUE;
|
| 3830 |
|
|
display_address = `TRUE;
|
| 3831 |
|
|
end
|
| 3832 |
|
|
end
|
| 3833 |
|
|
else if (r == `DOT)
|
| 3834 |
|
|
begin
|
| 3835 |
|
|
r = $fgetc(ifp);
|
| 3836 |
|
|
if (r == `DOT)
|
| 3837 |
|
|
begin
|
| 3838 |
|
|
if (get_start_address == `TRUE)
|
| 3839 |
|
|
begin
|
| 3840 |
|
|
start_address = address;
|
| 3841 |
|
|
address = 0;
|
| 3842 |
|
|
get_start_address = `FALSE;
|
| 3843 |
|
|
get_end_address = `TRUE;
|
| 3844 |
|
|
end
|
| 3845 |
|
|
else
|
| 3846 |
|
|
begin
|
| 3847 |
|
|
error_status = `TRUE;
|
| 3848 |
|
|
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
|
| 3849 |
|
|
done = `TRUE;
|
| 3850 |
|
|
disable READER;
|
| 3851 |
|
|
end
|
| 3852 |
|
|
end
|
| 3853 |
|
|
else
|
| 3854 |
|
|
begin
|
| 3855 |
|
|
error_status = `TRUE;
|
| 3856 |
|
|
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
|
| 3857 |
|
|
done = `TRUE;
|
| 3858 |
|
|
disable READER;
|
| 3859 |
|
|
end
|
| 3860 |
|
|
end
|
| 3861 |
|
|
else if (r == `OPEN_BRACKET)
|
| 3862 |
|
|
begin
|
| 3863 |
|
|
get_start_address = `TRUE;
|
| 3864 |
|
|
end
|
| 3865 |
|
|
else if (r == `CLOSE_BRACKET)
|
| 3866 |
|
|
begin
|
| 3867 |
|
|
if (get_end_address == `TRUE)
|
| 3868 |
|
|
begin
|
| 3869 |
|
|
end_address = address;
|
| 3870 |
|
|
address = 0;
|
| 3871 |
|
|
get_end_address = `FALSE;
|
| 3872 |
|
|
end
|
| 3873 |
|
|
else
|
| 3874 |
|
|
begin
|
| 3875 |
|
|
error_status = `TRUE;
|
| 3876 |
|
|
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
|
| 3877 |
|
|
done = `TRUE;
|
| 3878 |
|
|
disable READER;
|
| 3879 |
|
|
end
|
| 3880 |
|
|
end
|
| 3881 |
|
|
else if (r == `SEMICOLON)
|
| 3882 |
|
|
begin
|
| 3883 |
|
|
if (get_width == `TRUE)
|
| 3884 |
|
|
begin
|
| 3885 |
|
|
width_found = `TRUE;
|
| 3886 |
|
|
memory_width = value;
|
| 3887 |
|
|
value = 0;
|
| 3888 |
|
|
get_width = `FALSE;
|
| 3889 |
|
|
end
|
| 3890 |
|
|
else if (get_depth == `TRUE)
|
| 3891 |
|
|
begin
|
| 3892 |
|
|
depth_found = `TRUE;
|
| 3893 |
|
|
memory_depth = value;
|
| 3894 |
|
|
value = 0;
|
| 3895 |
|
|
get_depth = `FALSE;
|
| 3896 |
|
|
end
|
| 3897 |
|
|
else if (get_data_radix == `TRUE)
|
| 3898 |
|
|
begin
|
| 3899 |
|
|
data_radix_found = `TRUE;
|
| 3900 |
|
|
get_data_radix = `FALSE;
|
| 3901 |
|
|
|
| 3902 |
|
|
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
|
| 3903 |
|
|
(buffer == "hex"))
|
| 3904 |
|
|
begin
|
| 3905 |
|
|
data_radix = buffer[24 : 1];
|
| 3906 |
|
|
end
|
| 3907 |
|
|
else
|
| 3908 |
|
|
begin
|
| 3909 |
|
|
error_status = `TRUE;
|
| 3910 |
|
|
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer);
|
| 3911 |
|
|
end
|
| 3912 |
|
|
buffer = "";
|
| 3913 |
|
|
end
|
| 3914 |
|
|
else if (get_address_radix == `TRUE)
|
| 3915 |
|
|
begin
|
| 3916 |
|
|
address_radix_found = `TRUE;
|
| 3917 |
|
|
get_address_radix = `FALSE;
|
| 3918 |
|
|
|
| 3919 |
|
|
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
|
| 3920 |
|
|
(buffer == "hex"))
|
| 3921 |
|
|
begin
|
| 3922 |
|
|
address_radix = buffer[24 : 1];
|
| 3923 |
|
|
end
|
| 3924 |
|
|
else
|
| 3925 |
|
|
begin
|
| 3926 |
|
|
error_status = `TRUE;
|
| 3927 |
|
|
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer);
|
| 3928 |
|
|
end
|
| 3929 |
|
|
buffer = "";
|
| 3930 |
|
|
end
|
| 3931 |
|
|
else if (buffer == "end")
|
| 3932 |
|
|
begin
|
| 3933 |
|
|
if (get_address_data_pairs == `TRUE)
|
| 3934 |
|
|
begin
|
| 3935 |
|
|
last_rec = `TRUE;
|
| 3936 |
|
|
buffer = "";
|
| 3937 |
|
|
end
|
| 3938 |
|
|
else
|
| 3939 |
|
|
begin
|
| 3940 |
|
|
error_status = `TRUE;
|
| 3941 |
|
|
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
|
| 3942 |
|
|
end
|
| 3943 |
|
|
end
|
| 3944 |
|
|
else if (get_data == `TRUE)
|
| 3945 |
|
|
begin
|
| 3946 |
|
|
get_address = `TRUE;
|
| 3947 |
|
|
get_data = `FALSE;
|
| 3948 |
|
|
buffer = "";
|
| 3949 |
|
|
character_count = 0;
|
| 3950 |
|
|
|
| 3951 |
|
|
if (start_address != end_address)
|
| 3952 |
|
|
begin
|
| 3953 |
|
|
for (address = start_address; address <= end_address; address = address+1)
|
| 3954 |
|
|
begin
|
| 3955 |
|
|
$fdisplay(ofp,"@%0h", address);
|
| 3956 |
|
|
|
| 3957 |
|
|
for (i = memory_width -1; i >= 0; i = i-1 )
|
| 3958 |
|
|
begin
|
| 3959 |
|
|
hex[(i % 4)] = memory_data1[i];
|
| 3960 |
|
|
|
| 3961 |
|
|
if ((i % 4) == 0)
|
| 3962 |
|
|
begin
|
| 3963 |
|
|
$fwrite(ofp, "%0h", hex);
|
| 3964 |
|
|
hex = 0;
|
| 3965 |
|
|
end
|
| 3966 |
|
|
end
|
| 3967 |
|
|
|
| 3968 |
|
|
$fwrite(ofp, "\n");
|
| 3969 |
|
|
end
|
| 3970 |
|
|
start_address = 0;
|
| 3971 |
|
|
end_address = 0;
|
| 3972 |
|
|
address = 0;
|
| 3973 |
|
|
hex = 0;
|
| 3974 |
|
|
memory_data1 = {(`MAX_WIDTH+1) {1'b0}};
|
| 3975 |
|
|
end
|
| 3976 |
|
|
else
|
| 3977 |
|
|
begin
|
| 3978 |
|
|
if (display_address == `TRUE)
|
| 3979 |
|
|
begin
|
| 3980 |
|
|
$fdisplay(ofp,"@%0h", address);
|
| 3981 |
|
|
display_address = `FALSE;
|
| 3982 |
|
|
end
|
| 3983 |
|
|
|
| 3984 |
|
|
for (i = memory_width -1; i >= 0; i = i-1 )
|
| 3985 |
|
|
begin
|
| 3986 |
|
|
hex[(i % 4)] = memory_data1[i];
|
| 3987 |
|
|
|
| 3988 |
|
|
if ((i % 4) == 0)
|
| 3989 |
|
|
begin
|
| 3990 |
|
|
$fwrite(ofp, "%0h", hex);
|
| 3991 |
|
|
hex = 0;
|
| 3992 |
|
|
end
|
| 3993 |
|
|
end
|
| 3994 |
|
|
|
| 3995 |
|
|
$fwrite(ofp, "\n");
|
| 3996 |
|
|
address = 0;
|
| 3997 |
|
|
hex = 0;
|
| 3998 |
|
|
memory_data1 = {(`MAX_WIDTH+1) {1'b0}};
|
| 3999 |
|
|
end
|
| 4000 |
|
|
end
|
| 4001 |
|
|
else
|
| 4002 |
|
|
begin
|
| 4003 |
|
|
error_status = `TRUE;
|
| 4004 |
|
|
$display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no);
|
| 4005 |
|
|
end
|
| 4006 |
|
|
end
|
| 4007 |
|
|
else if ((get_width == `TRUE) || (get_depth == `TRUE))
|
| 4008 |
|
|
begin
|
| 4009 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4010 |
|
|
value = (value * 10) + (r - 'h30);
|
| 4011 |
|
|
else
|
| 4012 |
|
|
begin
|
| 4013 |
|
|
error_status = `TRUE;
|
| 4014 |
|
|
$display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no);
|
| 4015 |
|
|
end
|
| 4016 |
|
|
end
|
| 4017 |
|
|
else if (get_address == `TRUE)
|
| 4018 |
|
|
begin
|
| 4019 |
|
|
if (address_radix == "hex")
|
| 4020 |
|
|
begin
|
| 4021 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4022 |
|
|
value = (r - 'h30);
|
| 4023 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4024 |
|
|
value = 10 + (r - 'h41);
|
| 4025 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4026 |
|
|
value = 10 + (r - 'h61);
|
| 4027 |
|
|
else
|
| 4028 |
|
|
begin
|
| 4029 |
|
|
invalid_address = `TRUE;
|
| 4030 |
|
|
end
|
| 4031 |
|
|
|
| 4032 |
|
|
address = (address * 16) + value;
|
| 4033 |
|
|
end
|
| 4034 |
|
|
else if ((address_radix == "dec"))
|
| 4035 |
|
|
begin
|
| 4036 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4037 |
|
|
value = (r - 'h30);
|
| 4038 |
|
|
else
|
| 4039 |
|
|
begin
|
| 4040 |
|
|
invalid_address = `TRUE;
|
| 4041 |
|
|
end
|
| 4042 |
|
|
|
| 4043 |
|
|
address = (address * 10) + value;
|
| 4044 |
|
|
end
|
| 4045 |
|
|
else if (address_radix == "uns")
|
| 4046 |
|
|
begin
|
| 4047 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4048 |
|
|
value = (r - 'h30);
|
| 4049 |
|
|
else
|
| 4050 |
|
|
begin
|
| 4051 |
|
|
invalid_address = `TRUE;
|
| 4052 |
|
|
end
|
| 4053 |
|
|
|
| 4054 |
|
|
address = (address * 10) + value;
|
| 4055 |
|
|
end
|
| 4056 |
|
|
else if (address_radix == "bin")
|
| 4057 |
|
|
begin
|
| 4058 |
|
|
if ((r >= "0") && (r <= "1"))
|
| 4059 |
|
|
value = (r - 'h30);
|
| 4060 |
|
|
else
|
| 4061 |
|
|
begin
|
| 4062 |
|
|
invalid_address = `TRUE;
|
| 4063 |
|
|
end
|
| 4064 |
|
|
|
| 4065 |
|
|
address = (address * 2) + value;
|
| 4066 |
|
|
end
|
| 4067 |
|
|
else if (address_radix == "oct")
|
| 4068 |
|
|
begin
|
| 4069 |
|
|
if ((r >= "0") && (r <= "7"))
|
| 4070 |
|
|
value = (r - 'h30);
|
| 4071 |
|
|
else
|
| 4072 |
|
|
begin
|
| 4073 |
|
|
invalid_address = `TRUE;
|
| 4074 |
|
|
end
|
| 4075 |
|
|
|
| 4076 |
|
|
address = (address * 8) + value;
|
| 4077 |
|
|
end
|
| 4078 |
|
|
|
| 4079 |
|
|
if ((r >= 65) && (r <= 90))
|
| 4080 |
|
|
c = tolower(r);
|
| 4081 |
|
|
else
|
| 4082 |
|
|
c = r;
|
| 4083 |
|
|
|
| 4084 |
|
|
{tmp_char,buffer} = {buffer, c};
|
| 4085 |
|
|
end
|
| 4086 |
|
|
else if (get_data == `TRUE)
|
| 4087 |
|
|
begin
|
| 4088 |
|
|
character_count = character_count +1;
|
| 4089 |
|
|
|
| 4090 |
|
|
if (data_radix == "hex")
|
| 4091 |
|
|
begin
|
| 4092 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4093 |
|
|
value = (r - 'h30);
|
| 4094 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4095 |
|
|
value = 10 + (r - 'h41);
|
| 4096 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4097 |
|
|
value = 10 + (r - 'h61);
|
| 4098 |
|
|
else
|
| 4099 |
|
|
begin
|
| 4100 |
|
|
error_status = `TRUE;
|
| 4101 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 4102 |
|
|
done = `TRUE;
|
| 4103 |
|
|
disable READER;
|
| 4104 |
|
|
end
|
| 4105 |
|
|
|
| 4106 |
|
|
memory_data1 = (memory_data1 * 16) + value;
|
| 4107 |
|
|
end
|
| 4108 |
|
|
else if ((data_radix == "dec"))
|
| 4109 |
|
|
begin
|
| 4110 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4111 |
|
|
value = (r - 'h30);
|
| 4112 |
|
|
else
|
| 4113 |
|
|
begin
|
| 4114 |
|
|
error_status = `TRUE;
|
| 4115 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 4116 |
|
|
done = `TRUE;
|
| 4117 |
|
|
disable READER;
|
| 4118 |
|
|
end
|
| 4119 |
|
|
|
| 4120 |
|
|
memory_data1 = (memory_data1 * 10) + value;
|
| 4121 |
|
|
end
|
| 4122 |
|
|
else if (data_radix == "uns")
|
| 4123 |
|
|
begin
|
| 4124 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4125 |
|
|
value = (r - 'h30);
|
| 4126 |
|
|
else
|
| 4127 |
|
|
begin
|
| 4128 |
|
|
error_status = `TRUE;
|
| 4129 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 4130 |
|
|
done = `TRUE;
|
| 4131 |
|
|
disable READER;
|
| 4132 |
|
|
end
|
| 4133 |
|
|
|
| 4134 |
|
|
memory_data1 = (memory_data1 * 10) + value;
|
| 4135 |
|
|
end
|
| 4136 |
|
|
else if (data_radix == "bin")
|
| 4137 |
|
|
begin
|
| 4138 |
|
|
if ((r >= "0") && (r <= "1"))
|
| 4139 |
|
|
value = (r - 'h30);
|
| 4140 |
|
|
else
|
| 4141 |
|
|
begin
|
| 4142 |
|
|
error_status = `TRUE;
|
| 4143 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 4144 |
|
|
done = `TRUE;
|
| 4145 |
|
|
disable READER;
|
| 4146 |
|
|
end
|
| 4147 |
|
|
|
| 4148 |
|
|
memory_data1 = (memory_data1 * 2) + value;
|
| 4149 |
|
|
end
|
| 4150 |
|
|
else if (data_radix == "oct")
|
| 4151 |
|
|
begin
|
| 4152 |
|
|
if ((r >= "0") && (r <= "7"))
|
| 4153 |
|
|
value = (r - 'h30);
|
| 4154 |
|
|
else
|
| 4155 |
|
|
begin
|
| 4156 |
|
|
error_status = `TRUE;
|
| 4157 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 4158 |
|
|
done = `TRUE;
|
| 4159 |
|
|
disable READER;
|
| 4160 |
|
|
end
|
| 4161 |
|
|
|
| 4162 |
|
|
memory_data1 = (memory_data1 * 8) + value;
|
| 4163 |
|
|
end
|
| 4164 |
|
|
end
|
| 4165 |
|
|
else
|
| 4166 |
|
|
begin
|
| 4167 |
|
|
first_rec = `TRUE;
|
| 4168 |
|
|
|
| 4169 |
|
|
if ((r >= 65) && (r <= 90))
|
| 4170 |
|
|
c = tolower(r);
|
| 4171 |
|
|
else
|
| 4172 |
|
|
c = r;
|
| 4173 |
|
|
|
| 4174 |
|
|
{tmp_char,buffer} = {buffer, c};
|
| 4175 |
|
|
end
|
| 4176 |
|
|
end
|
| 4177 |
|
|
$fclose(ifp);
|
| 4178 |
|
|
$fclose(ofp);
|
| 4179 |
|
|
end
|
| 4180 |
|
|
`endif
|
| 4181 |
|
|
`endif
|
| 4182 |
|
|
end
|
| 4183 |
|
|
endtask // convert_mif2ver
|
| 4184 |
|
|
|
| 4185 |
|
|
/****************************************************************/
|
| 4186 |
|
|
/* Read in Intel-hex format data to verilog format data. */
|
| 4187 |
|
|
/* Intel-hex format :nnaaaaattddddcc */
|
| 4188 |
|
|
/****************************************************************/
|
| 4189 |
|
|
task convert_hex2ver;
|
| 4190 |
|
|
input[`MAX_NAME_SZ*8 : 1] in_file;
|
| 4191 |
|
|
input width;
|
| 4192 |
|
|
output [`MAX_NAME_SZ*8 : 1] out_file;
|
| 4193 |
|
|
reg [`MAX_NAME_SZ*8 : 1] in_file;
|
| 4194 |
|
|
reg [`MAX_NAME_SZ*8 : 1] out_file;
|
| 4195 |
|
|
reg [8:1] c;
|
| 4196 |
|
|
reg [3:0] hex, tmp_char;
|
| 4197 |
|
|
reg done;
|
| 4198 |
|
|
reg error_status;
|
| 4199 |
|
|
reg first_rec;
|
| 4200 |
|
|
reg last_rec;
|
| 4201 |
|
|
reg first_normal_record;
|
| 4202 |
|
|
reg is_word_address_format;
|
| 4203 |
|
|
|
| 4204 |
|
|
integer width;
|
| 4205 |
|
|
integer ifp, ofp, r, r2;
|
| 4206 |
|
|
integer i, j, k, m, n;
|
| 4207 |
|
|
|
| 4208 |
|
|
integer off_addr, nn, aaaa, aaaa_pre, tt, cc, aah, aal, dd, sum ;
|
| 4209 |
|
|
integer line_no;
|
| 4210 |
|
|
integer divide_factor;
|
| 4211 |
|
|
|
| 4212 |
|
|
begin
|
| 4213 |
|
|
`ifdef NO_PLI
|
| 4214 |
|
|
`else
|
| 4215 |
|
|
`ifdef USE_RIF
|
| 4216 |
|
|
`else
|
| 4217 |
|
|
done = `FALSE;
|
| 4218 |
|
|
error_status = `FALSE;
|
| 4219 |
|
|
first_rec = `FALSE;
|
| 4220 |
|
|
last_rec = `FALSE;
|
| 4221 |
|
|
first_normal_record = `TRUE;
|
| 4222 |
|
|
is_word_address_format = `FALSE;
|
| 4223 |
|
|
off_addr= 0;
|
| 4224 |
|
|
nn= 0;
|
| 4225 |
|
|
aaaa= 0;
|
| 4226 |
|
|
aaaa_pre = 0;
|
| 4227 |
|
|
tt= 0;
|
| 4228 |
|
|
cc= 0;
|
| 4229 |
|
|
aah= 0;
|
| 4230 |
|
|
aal= 0;
|
| 4231 |
|
|
dd= 0;
|
| 4232 |
|
|
sum = 0;
|
| 4233 |
|
|
line_no = 1;
|
| 4234 |
|
|
c = 0;
|
| 4235 |
|
|
hex = 0;
|
| 4236 |
|
|
divide_factor = 1;
|
| 4237 |
|
|
|
| 4238 |
|
|
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
|
| 4239 |
|
|
out_file = in_file;
|
| 4240 |
|
|
else
|
| 4241 |
|
|
begin
|
| 4242 |
|
|
ifp = $fopen(in_file, "r");
|
| 4243 |
|
|
if (ifp == `NULL)
|
| 4244 |
|
|
begin
|
| 4245 |
|
|
$display("ERROR: cannot read %0s.", in_file);
|
| 4246 |
|
|
done = `TRUE;
|
| 4247 |
|
|
end
|
| 4248 |
|
|
|
| 4249 |
|
|
out_file = in_file;
|
| 4250 |
|
|
|
| 4251 |
|
|
if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX"))
|
| 4252 |
|
|
out_file[3*8 : 1] = `EXT_STR;
|
| 4253 |
|
|
else
|
| 4254 |
|
|
begin
|
| 4255 |
|
|
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file);
|
| 4256 |
|
|
done = `TRUE;
|
| 4257 |
|
|
end
|
| 4258 |
|
|
|
| 4259 |
|
|
if (!done)
|
| 4260 |
|
|
begin
|
| 4261 |
|
|
ofp = $fopen(out_file, "w");
|
| 4262 |
|
|
if (ofp == `NULL)
|
| 4263 |
|
|
begin
|
| 4264 |
|
|
$display("ERROR : cannot write %0s.", out_file);
|
| 4265 |
|
|
done = `TRUE;
|
| 4266 |
|
|
end
|
| 4267 |
|
|
end
|
| 4268 |
|
|
|
| 4269 |
|
|
while((!done) && (!error_status))
|
| 4270 |
|
|
begin : READER
|
| 4271 |
|
|
|
| 4272 |
|
|
r = $fgetc(ifp);
|
| 4273 |
|
|
|
| 4274 |
|
|
if (r == `EOF)
|
| 4275 |
|
|
begin
|
| 4276 |
|
|
if(!first_rec)
|
| 4277 |
|
|
begin
|
| 4278 |
|
|
error_status = `TRUE;
|
| 4279 |
|
|
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
|
| 4280 |
|
|
end
|
| 4281 |
|
|
else if(!last_rec)
|
| 4282 |
|
|
begin
|
| 4283 |
|
|
error_status = `TRUE;
|
| 4284 |
|
|
$display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no);
|
| 4285 |
|
|
end
|
| 4286 |
|
|
end
|
| 4287 |
|
|
else if (r == `COLON)
|
| 4288 |
|
|
begin
|
| 4289 |
|
|
first_rec = `TRUE;
|
| 4290 |
|
|
nn= 0;
|
| 4291 |
|
|
aaaa_pre = aaaa;
|
| 4292 |
|
|
aaaa= 0;
|
| 4293 |
|
|
tt= 0;
|
| 4294 |
|
|
cc= 0;
|
| 4295 |
|
|
aah= 0;
|
| 4296 |
|
|
aal= 0;
|
| 4297 |
|
|
dd= 0;
|
| 4298 |
|
|
sum = 0;
|
| 4299 |
|
|
|
| 4300 |
|
|
// get record length bytes
|
| 4301 |
|
|
for (i = 0; i < 2; i = i+1)
|
| 4302 |
|
|
begin
|
| 4303 |
|
|
r = $fgetc(ifp);
|
| 4304 |
|
|
|
| 4305 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4306 |
|
|
nn = (nn * 16) + (r - 'h30);
|
| 4307 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4308 |
|
|
nn = (nn * 16) + 10 + (r - 'h41);
|
| 4309 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4310 |
|
|
nn = (nn * 16) + 10 + (r - 'h61);
|
| 4311 |
|
|
else
|
| 4312 |
|
|
begin
|
| 4313 |
|
|
error_status = `TRUE;
|
| 4314 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4315 |
|
|
done = `TRUE;
|
| 4316 |
|
|
disable READER;
|
| 4317 |
|
|
end
|
| 4318 |
|
|
end
|
| 4319 |
|
|
|
| 4320 |
|
|
// get address bytes
|
| 4321 |
|
|
for (i = 0; i < 4; i = i+1)
|
| 4322 |
|
|
begin
|
| 4323 |
|
|
r = $fgetc(ifp);
|
| 4324 |
|
|
|
| 4325 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4326 |
|
|
hex = (r - 'h30);
|
| 4327 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4328 |
|
|
hex = 10 + (r - 'h41);
|
| 4329 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4330 |
|
|
hex = 10 + (r - 'h61);
|
| 4331 |
|
|
else
|
| 4332 |
|
|
begin
|
| 4333 |
|
|
error_status = `TRUE;
|
| 4334 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4335 |
|
|
done = `TRUE;
|
| 4336 |
|
|
disable READER;
|
| 4337 |
|
|
end
|
| 4338 |
|
|
|
| 4339 |
|
|
aaaa = (aaaa * 16) + hex;
|
| 4340 |
|
|
|
| 4341 |
|
|
if (i < 2)
|
| 4342 |
|
|
aal = (aal * 16) + hex;
|
| 4343 |
|
|
else
|
| 4344 |
|
|
aah = (aah * 16) + hex;
|
| 4345 |
|
|
end
|
| 4346 |
|
|
|
| 4347 |
|
|
// get record type bytes
|
| 4348 |
|
|
for (i = 0; i < 2; i = i+1)
|
| 4349 |
|
|
begin
|
| 4350 |
|
|
r = $fgetc(ifp);
|
| 4351 |
|
|
|
| 4352 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4353 |
|
|
tt = (tt * 16) + (r - 'h30);
|
| 4354 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4355 |
|
|
tt = (tt * 16) + 10 + (r - 'h41);
|
| 4356 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4357 |
|
|
tt = (tt * 16) + 10 + (r - 'h61);
|
| 4358 |
|
|
else
|
| 4359 |
|
|
begin
|
| 4360 |
|
|
error_status = `TRUE;
|
| 4361 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4362 |
|
|
done = `TRUE;
|
| 4363 |
|
|
disable READER;
|
| 4364 |
|
|
end
|
| 4365 |
|
|
end
|
| 4366 |
|
|
|
| 4367 |
|
|
if((tt == 2) && (nn != 2) )
|
| 4368 |
|
|
begin
|
| 4369 |
|
|
error_status = `TRUE;
|
| 4370 |
|
|
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
|
| 4371 |
|
|
end
|
| 4372 |
|
|
else
|
| 4373 |
|
|
begin
|
| 4374 |
|
|
|
| 4375 |
|
|
// get the sum of all the bytes for record length, address and record types
|
| 4376 |
|
|
sum = nn + aah + aal + tt ;
|
| 4377 |
|
|
|
| 4378 |
|
|
// check the record type
|
| 4379 |
|
|
case(tt)
|
| 4380 |
|
|
// normal_record
|
| 4381 |
|
|
8'h00 :
|
| 4382 |
|
|
begin
|
| 4383 |
|
|
first_rec = `TRUE;
|
| 4384 |
|
|
i = 0;
|
| 4385 |
|
|
k = width / `AWORD;
|
| 4386 |
|
|
if ((width % `AWORD) != 0)
|
| 4387 |
|
|
k = k + 1;
|
| 4388 |
|
|
|
| 4389 |
|
|
if ((first_normal_record == `FALSE) &&(aaaa != k))
|
| 4390 |
|
|
is_word_address_format = `TRUE;
|
| 4391 |
|
|
|
| 4392 |
|
|
first_normal_record = `FALSE;
|
| 4393 |
|
|
|
| 4394 |
|
|
if ((aaaa == k) && (is_word_address_format == `FALSE))
|
| 4395 |
|
|
divide_factor = k;
|
| 4396 |
|
|
|
| 4397 |
|
|
// k = no. of bytes per entry.
|
| 4398 |
|
|
while (i < nn)
|
| 4399 |
|
|
begin
|
| 4400 |
|
|
$fdisplay(ofp,"@%0h", (aaaa + off_addr)/divide_factor);
|
| 4401 |
|
|
|
| 4402 |
|
|
for (j = 1; j <= k; j = j +1)
|
| 4403 |
|
|
begin
|
| 4404 |
|
|
if ((k - j +1) > nn)
|
| 4405 |
|
|
begin
|
| 4406 |
|
|
for(m = 1; m <= 2; m= m+1)
|
| 4407 |
|
|
begin
|
| 4408 |
|
|
if((((k-j)*8) + ((3-m)*4) - width) < 4)
|
| 4409 |
|
|
$fwrite(ofp, "0");
|
| 4410 |
|
|
end
|
| 4411 |
|
|
end
|
| 4412 |
|
|
else
|
| 4413 |
|
|
begin
|
| 4414 |
|
|
// get the data bytes
|
| 4415 |
|
|
for(m = 1; m <= 2; m= m+1)
|
| 4416 |
|
|
begin
|
| 4417 |
|
|
r = $fgetc(ifp);
|
| 4418 |
|
|
|
| 4419 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4420 |
|
|
hex = (r - 'h30);
|
| 4421 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4422 |
|
|
hex = 10 + (r - 'h41);
|
| 4423 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4424 |
|
|
hex = 10 + (r - 'h61);
|
| 4425 |
|
|
else
|
| 4426 |
|
|
begin
|
| 4427 |
|
|
error_status = `TRUE;
|
| 4428 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4429 |
|
|
done = `TRUE;
|
| 4430 |
|
|
disable READER;
|
| 4431 |
|
|
end
|
| 4432 |
|
|
|
| 4433 |
|
|
if((((k-j)*8) + ((3-m)*4) - width) < 4)
|
| 4434 |
|
|
$fwrite(ofp, "%h", hex);
|
| 4435 |
|
|
dd = (dd * 16) + hex;
|
| 4436 |
|
|
|
| 4437 |
|
|
if(m % 2 == 0)
|
| 4438 |
|
|
begin
|
| 4439 |
|
|
sum = sum + dd;
|
| 4440 |
|
|
dd = 0;
|
| 4441 |
|
|
end
|
| 4442 |
|
|
end
|
| 4443 |
|
|
end
|
| 4444 |
|
|
end
|
| 4445 |
|
|
$fwrite(ofp, "\n");
|
| 4446 |
|
|
|
| 4447 |
|
|
i = i + k;
|
| 4448 |
|
|
aaaa = aaaa + 1;
|
| 4449 |
|
|
end // end of while (i < nn)
|
| 4450 |
|
|
end
|
| 4451 |
|
|
// last record
|
| 4452 |
|
|
8'h01:
|
| 4453 |
|
|
begin
|
| 4454 |
|
|
last_rec = `TRUE;
|
| 4455 |
|
|
done = `TRUE;
|
| 4456 |
|
|
end
|
| 4457 |
|
|
// address base record
|
| 4458 |
|
|
8'h02:
|
| 4459 |
|
|
begin
|
| 4460 |
|
|
off_addr= 0;
|
| 4461 |
|
|
|
| 4462 |
|
|
// get the extended segment address record
|
| 4463 |
|
|
for(i = 1; i <= (nn*2); i= i+1)
|
| 4464 |
|
|
begin
|
| 4465 |
|
|
r = $fgetc(ifp);
|
| 4466 |
|
|
|
| 4467 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4468 |
|
|
hex = (r - 'h30);
|
| 4469 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4470 |
|
|
hex = 10 + (r - 'h41);
|
| 4471 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4472 |
|
|
hex = 10 + (r - 'h61);
|
| 4473 |
|
|
else
|
| 4474 |
|
|
begin
|
| 4475 |
|
|
error_status = `TRUE;
|
| 4476 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4477 |
|
|
done = `TRUE;
|
| 4478 |
|
|
disable READER;
|
| 4479 |
|
|
end
|
| 4480 |
|
|
|
| 4481 |
|
|
off_addr = (off_addr * `H10) + hex;
|
| 4482 |
|
|
dd = (dd * 16) + hex;
|
| 4483 |
|
|
|
| 4484 |
|
|
if(i % 2 == 0)
|
| 4485 |
|
|
begin
|
| 4486 |
|
|
sum = sum + dd;
|
| 4487 |
|
|
dd = 0;
|
| 4488 |
|
|
end
|
| 4489 |
|
|
end
|
| 4490 |
|
|
|
| 4491 |
|
|
off_addr = off_addr * `H10;
|
| 4492 |
|
|
end
|
| 4493 |
|
|
// address base record
|
| 4494 |
|
|
8'h03:
|
| 4495 |
|
|
// get the start segment address record
|
| 4496 |
|
|
for(i = 1; i <= (nn*2); i= i+1)
|
| 4497 |
|
|
begin
|
| 4498 |
|
|
r = $fgetc(ifp);
|
| 4499 |
|
|
|
| 4500 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4501 |
|
|
hex = (r - 'h30);
|
| 4502 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4503 |
|
|
hex = 10 + (r - 'h41);
|
| 4504 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4505 |
|
|
hex = 10 + (r - 'h61);
|
| 4506 |
|
|
else
|
| 4507 |
|
|
begin
|
| 4508 |
|
|
error_status = `TRUE;
|
| 4509 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4510 |
|
|
done = `TRUE;
|
| 4511 |
|
|
disable READER;
|
| 4512 |
|
|
end
|
| 4513 |
|
|
dd = (dd * 16) + hex;
|
| 4514 |
|
|
|
| 4515 |
|
|
if(i % 2 == 0)
|
| 4516 |
|
|
begin
|
| 4517 |
|
|
sum = sum + dd;
|
| 4518 |
|
|
dd = 0;
|
| 4519 |
|
|
end
|
| 4520 |
|
|
end
|
| 4521 |
|
|
// address base record
|
| 4522 |
|
|
8'h04:
|
| 4523 |
|
|
begin
|
| 4524 |
|
|
off_addr= 0;
|
| 4525 |
|
|
|
| 4526 |
|
|
// get the extended linear address record
|
| 4527 |
|
|
for(i = 1; i <= (nn*2); i= i+1)
|
| 4528 |
|
|
begin
|
| 4529 |
|
|
r = $fgetc(ifp);
|
| 4530 |
|
|
|
| 4531 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4532 |
|
|
hex = (r - 'h30);
|
| 4533 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4534 |
|
|
hex = 10 + (r - 'h41);
|
| 4535 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4536 |
|
|
hex = 10 + (r - 'h61);
|
| 4537 |
|
|
else
|
| 4538 |
|
|
begin
|
| 4539 |
|
|
error_status = `TRUE;
|
| 4540 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4541 |
|
|
done = `TRUE;
|
| 4542 |
|
|
disable READER;
|
| 4543 |
|
|
end
|
| 4544 |
|
|
|
| 4545 |
|
|
off_addr = (off_addr * `H10) + hex;
|
| 4546 |
|
|
dd = (dd * 16) + hex;
|
| 4547 |
|
|
|
| 4548 |
|
|
if(i % 2 == 0)
|
| 4549 |
|
|
begin
|
| 4550 |
|
|
sum = sum + dd;
|
| 4551 |
|
|
dd = 0;
|
| 4552 |
|
|
end
|
| 4553 |
|
|
end
|
| 4554 |
|
|
|
| 4555 |
|
|
off_addr = off_addr * `H10000;
|
| 4556 |
|
|
end
|
| 4557 |
|
|
// address base record
|
| 4558 |
|
|
8'h05:
|
| 4559 |
|
|
// get the start linear address record
|
| 4560 |
|
|
for(i = 1; i <= (nn*2); i= i+1)
|
| 4561 |
|
|
begin
|
| 4562 |
|
|
r = $fgetc(ifp);
|
| 4563 |
|
|
|
| 4564 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4565 |
|
|
hex = (r - 'h30);
|
| 4566 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4567 |
|
|
hex = 10 + (r - 'h41);
|
| 4568 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4569 |
|
|
hex = 10 + (r - 'h61);
|
| 4570 |
|
|
else
|
| 4571 |
|
|
begin
|
| 4572 |
|
|
error_status = `TRUE;
|
| 4573 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4574 |
|
|
done = `TRUE;
|
| 4575 |
|
|
disable READER;
|
| 4576 |
|
|
end
|
| 4577 |
|
|
dd = (dd * 16) + hex;
|
| 4578 |
|
|
|
| 4579 |
|
|
if(i % 2 == 0)
|
| 4580 |
|
|
begin
|
| 4581 |
|
|
sum = sum + dd;
|
| 4582 |
|
|
dd = 0;
|
| 4583 |
|
|
end
|
| 4584 |
|
|
end
|
| 4585 |
|
|
default:
|
| 4586 |
|
|
begin
|
| 4587 |
|
|
error_status = `TRUE;
|
| 4588 |
|
|
$display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no);
|
| 4589 |
|
|
end
|
| 4590 |
|
|
endcase
|
| 4591 |
|
|
|
| 4592 |
|
|
// get the checksum bytes
|
| 4593 |
|
|
for (i = 0; i < 2; i = i+1)
|
| 4594 |
|
|
begin
|
| 4595 |
|
|
r = $fgetc(ifp);
|
| 4596 |
|
|
|
| 4597 |
|
|
if ((r >= "0") && (r <= "9"))
|
| 4598 |
|
|
cc = (cc * 16) + (r - 'h30);
|
| 4599 |
|
|
else if ((r >= "A") && (r <= "F"))
|
| 4600 |
|
|
cc = 10 + (cc * 16) + (r - 'h41);
|
| 4601 |
|
|
else if ((r >= "a") && (r <= "f"))
|
| 4602 |
|
|
cc = 10 + (cc * 16) + (r - 'h61);
|
| 4603 |
|
|
else
|
| 4604 |
|
|
begin
|
| 4605 |
|
|
error_status = `TRUE;
|
| 4606 |
|
|
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4607 |
|
|
done = `TRUE;
|
| 4608 |
|
|
disable READER;
|
| 4609 |
|
|
end
|
| 4610 |
|
|
end
|
| 4611 |
|
|
|
| 4612 |
|
|
// Perform check sum.
|
| 4613 |
|
|
if(((~sum+1)& `MASK15) != cc)
|
| 4614 |
|
|
begin
|
| 4615 |
|
|
error_status = `TRUE;
|
| 4616 |
|
|
$display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no);
|
| 4617 |
|
|
end
|
| 4618 |
|
|
end
|
| 4619 |
|
|
end
|
| 4620 |
|
|
else if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
|
| 4621 |
|
|
begin
|
| 4622 |
|
|
line_no = line_no +1;
|
| 4623 |
|
|
end
|
| 4624 |
|
|
else if (r == `SPACE)
|
| 4625 |
|
|
begin
|
| 4626 |
|
|
// continue to next character;
|
| 4627 |
|
|
end
|
| 4628 |
|
|
else
|
| 4629 |
|
|
begin
|
| 4630 |
|
|
error_status = `TRUE;
|
| 4631 |
|
|
$display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
|
| 4632 |
|
|
done = `TRUE;
|
| 4633 |
|
|
end
|
| 4634 |
|
|
end
|
| 4635 |
|
|
$fclose(ifp);
|
| 4636 |
|
|
$fclose(ofp);
|
| 4637 |
|
|
end
|
| 4638 |
|
|
`endif
|
| 4639 |
|
|
`endif
|
| 4640 |
|
|
end
|
| 4641 |
|
|
endtask // convert_hex2ver
|
| 4642 |
|
|
|
| 4643 |
|
|
task convert_to_ver_file;
|
| 4644 |
|
|
input[`MAX_NAME_SZ*8 : 1] in_file;
|
| 4645 |
|
|
input width;
|
| 4646 |
|
|
output [`MAX_NAME_SZ*8 : 1] out_file;
|
| 4647 |
|
|
reg [`MAX_NAME_SZ*8 : 1] in_file;
|
| 4648 |
|
|
reg [`MAX_NAME_SZ*8 : 1] out_file;
|
| 4649 |
|
|
integer width;
|
| 4650 |
|
|
begin
|
| 4651 |
|
|
|
| 4652 |
|
|
if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") ||
|
| 4653 |
|
|
(in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
|
| 4654 |
|
|
convert_hex2ver(in_file, width, out_file);
|
| 4655 |
|
|
else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF"))
|
| 4656 |
|
|
convert_mif2ver(in_file, width, out_file);
|
| 4657 |
|
|
else
|
| 4658 |
|
|
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file);
|
| 4659 |
|
|
end
|
| 4660 |
|
|
endtask // convert_to_ver_file
|
| 4661 |
|
|
|
| 4662 |
|
|
endmodule // ALTERA_MF_MEMORY_INITIALIZATION
|
