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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 221

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430_fpga.v
//
// *Module Description:
//                      openMSP430 FPGA testbench
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module  tb_openMSP430_fpga;
 
//
// Wire & Register definition
//------------------------------
 
// User Clocks
reg               FPGA_CLK1_50;
reg               FPGA_CLK2_50;
reg               FPGA_CLK3_50;
 
// User Interface (FPGA)
reg         [1:0] KEY;
reg         [3:0] SW;
wire        [7:0] LED;
 
// GPIO
wire       [35:0] GPIO_0;
wire       [35:0] GPIO_1;
 
// Arduino Digital Interface
wire       [15:0] ARDUINO_IO;
wire              ARDUINO_RESET_N;
 
// ADC
wire              ADC_CONVST;
wire              ADC_SCK;
wire              ADC_SDI;
reg               ADC_SDO;
 
// Core debug signals
wire   [8*32-1:0] omsp_i_state;
wire   [8*32-1:0] omsp_e_state;
wire       [31:0] omsp_inst_cycle;
wire   [8*32-1:0] omsp_inst_full;
wire       [31:0] omsp_inst_number;
wire       [15:0] omsp_inst_pc;
wire   [8*32-1:0] omsp_inst_short;
 
// LT24 data bus
reg               lt24_data_drive_en;
reg        [15:0] lt24_data_reg;
wire       [15:0] lt24_data = lt24_data_drive_en ? lt24_data_reg : 16'hzzzz;
 
// Testbench variables
integer           i;
integer           error;
reg               stimulus_done;
 
 
//
// Include files
//------------------------------
 
// CPU & Memory registers
`include "registers_omsp.v"
 
// Verilog stimulus
`include "stimulus.v"
 
//
// Initialize Program Memory
//------------------------------
 
initial
  begin
     // Read memory file
     #10 $readmemh("./pmem.mem", pmem);
  end
 
//
// Generate Clock & Reset
//------------------------------
initial
  begin
     FPGA_CLK1_50 = 1'b0;
     forever #10.0 FPGA_CLK1_50 <= ~FPGA_CLK1_50; // 50 MHz
  end
 
initial
  begin
     FPGA_CLK2_50 = 1'b0;
     forever #10.0 FPGA_CLK2_50 <= ~FPGA_CLK2_50; // 50 MHz
  end
 
initial
  begin
     FPGA_CLK3_50 = 1'b0;
     forever #10.0 FPGA_CLK3_50 <= ~FPGA_CLK3_50; // 50 MHz
  end
 
initial
  begin
     KEY[0]      = 1'b1;
     #100 KEY[0] = 1'b0;
     #600 KEY[0] = 1'b1;
  end
 
//
// Global initialization
//------------------------------
initial
  begin
     error              = 0;        // Testbench
     stimulus_done      = 1;
 
     KEY[1]             = 1'b1;     // Keys/Buttons
 
     SW[0]              = 1'b0;     // Switches
     SW[1]              = 1'b0;
     SW[2]              = 1'b0;
     SW[3]              = 1'b0;
 
     ADC_SDO            = 1'b1;     // ADC
 
     lt24_data_drive_en = 1'b0;     // LT24 Data bus
     lt24_data_reg      = 16'h0000;
  end
 
//
// openMSP430 FPGA Instance
//----------------------------------
 
openMSP430_fpga dut (
 
     // USER CLOCKS
     .FPGA_CLK1_50    ( FPGA_CLK1_50    ),
     .FPGA_CLK2_50    ( FPGA_CLK2_50    ),
     .FPGA_CLK3_50    ( FPGA_CLK3_50    ),
 
     // USER INTERFACE (FPGA)
     .KEY             ( KEY             ),
     .LED             ( LED             ),
     .SW              ( SW              ),
 
     // GPIO
     .GPIO_0          ( GPIO_0          ),
     .GPIO_1          ( GPIO_1          ),
 
     // ARDUINO DIGITAL INTERFACE
     .ARDUINO_IO      ( ARDUINO_IO      ),
     .ARDUINO_RESET_N ( ARDUINO_RESET_N ),
 
     // ADC
     .ADC_CONVST      ( ADC_CONVST      ),
     .ADC_SCK         ( ADC_SCK         ),
     .ADC_SDI         ( ADC_SDI         ),
     .ADC_SDO         ( ADC_SDO         )
);
 
// Pull-ups for the I2C debug interface
pullup dbg_scl_inst (ARDUINO_IO[15]);
pullup dbg_sda_inst (ARDUINO_IO[14]);
 
// Assign LT24 data bus
assign GPIO_0[8]  = lt24_data[0] ;
assign GPIO_0[7]  = lt24_data[1] ;
assign GPIO_0[6]  = lt24_data[2] ;
assign GPIO_0[5]  = lt24_data[3] ;
assign GPIO_0[13] = lt24_data[4] ;
assign GPIO_0[14] = lt24_data[5] ;
assign GPIO_0[15] = lt24_data[6] ;
assign GPIO_0[16] = lt24_data[7] ;
assign GPIO_0[17] = lt24_data[8] ;
assign GPIO_0[18] = lt24_data[9] ;
assign GPIO_0[19] = lt24_data[10];
assign GPIO_0[20] = lt24_data[11];
assign GPIO_0[21] = lt24_data[12];
assign GPIO_0[22] = lt24_data[13];
assign GPIO_0[23] = lt24_data[14];
assign GPIO_0[24] = lt24_data[15];
 
 
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_omsp (
 
// OUTPUTs
    .e_state      (omsp_e_state),       // Execution state
    .i_state      (omsp_i_state),       // Instruction fetch state
    .inst_cycle   (omsp_inst_cycle),    // Cycle number within current instruction
    .inst_full    (omsp_inst_full),     // Currently executed instruction (full version)
    .inst_number  (omsp_inst_number),   // Instruction number since last system reset
    .inst_pc      (omsp_inst_pc),       // Instruction Program counter
    .inst_short   (omsp_inst_short)     // Currently executed instruction (short version)
);
 
//
// Generate Waveform
//----------------------------------------
initial
  begin
   `ifdef VPD_FILE
     $vcdplusfile("tb_openMSP430_fpga.vpd");
     $vcdpluson();
   `else
     `ifdef TRN_FILE
        $recordfile ("tb_openMSP430_fpga.trn");
        $recordvars;
     `else
        $dumpfile("tb_openMSP430_fpga.vcd");
        $dumpvars(0, tb_openMSP430_fpga);
     `endif
   `endif
  end
 
//
// End of simulation
//----------------------------------------
 
initial // Timeout
  begin
   `ifdef NO_TIMEOUT
   `else
     `ifdef VERY_LONG_TIMEOUT
       #500000000;
     `else
     `ifdef LONG_TIMEOUT
       #5000000;
     `else
       #500000;
     `endif
     `endif
       $display(" ===============================================");
       $display("|               SIMULATION FAILED               |");
       $display("|              (simulation Timeout)             |");
       $display(" ===============================================");
       $finish;
   `endif
  end
 
initial // Normal end of test
  begin
     @(omsp_inst_pc===16'hffff)
     $display(" ===============================================");
     if (error!=0)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (the verilog stimulus didn't complete)    |");
       end
     else
       begin
          $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end
 
 
//
// Tasks Definition
//------------------------------
 
   task tb_error;
      input [65*8:0] error_string;
      begin
         $display("ERROR: %s %t", error_string, $time);
         error = error+1;
      end
   endtask
 
 
endmodule

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 221

Line No.	Rev	Author	Line
1	221	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: tb_openMSP430_fpga.v`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 FPGA testbench`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev: 111 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $`
37			`//----------------------------------------------------------------------------`
38			`include "timescale.v"
39			`ifdef OMSP_NO_INCLUDE
40			`else
41			`include "openMSP430_defines.v"
42			`endif
43
44			`module tb_openMSP430_fpga;`
45
46			`//`
47			`// Wire & Register definition`
48			`//------------------------------`
49
50			`// User Clocks`
51			`reg FPGA_CLK1_50;`
52			`reg FPGA_CLK2_50;`
53			`reg FPGA_CLK3_50;`
54
55			`// User Interface (FPGA)`
56			`reg [1:0] KEY;`
57			`reg [3:0] SW;`
58			`wire [7:0] LED;`
59
60			`// GPIO`
61			`wire [35:0] GPIO_0;`
62			`wire [35:0] GPIO_1;`
63
64			`// Arduino Digital Interface`
65			`wire [15:0] ARDUINO_IO;`
66			`wire ARDUINO_RESET_N;`
67
68			`// ADC`
69			`wire ADC_CONVST;`
70			`wire ADC_SCK;`
71			`wire ADC_SDI;`
72			`reg ADC_SDO;`
73
74			`// Core debug signals`
75			`wire [8*32-1:0] omsp_i_state;`
76			`wire [8*32-1:0] omsp_e_state;`
77			`wire [31:0] omsp_inst_cycle;`
78			`wire [8*32-1:0] omsp_inst_full;`
79			`wire [31:0] omsp_inst_number;`
80			`wire [15:0] omsp_inst_pc;`
81			`wire [8*32-1:0] omsp_inst_short;`
82
83			`// LT24 data bus`
84			`reg lt24_data_drive_en;`
85			`reg [15:0] lt24_data_reg;`
86			`wire [15:0] lt24_data = lt24_data_drive_en ? lt24_data_reg : 16'hzzzz;`
87
88			`// Testbench variables`
89			`integer i;`
90			`integer error;`
91			`reg stimulus_done;`
92
93
94			`//`
95			`// Include files`
96			`//------------------------------`
97
98			`// CPU & Memory registers`
99			`include "registers_omsp.v"
100
101			`// Verilog stimulus`
102			`include "stimulus.v"
103
104			`//`
105			`// Initialize Program Memory`
106			`//------------------------------`
107
108			`initial`
109			`begin`
110			`// Read memory file`
111			`#10 $readmemh("./pmem.mem", pmem);`
112			`end`
113
114			`//`
115			`// Generate Clock & Reset`
116			`//------------------------------`
117			`initial`
118			`begin`
119			`FPGA_CLK1_50 = 1'b0;`
120			`forever #10.0 FPGA_CLK1_50 <= ~FPGA_CLK1_50; // 50 MHz`
121			`end`
122
123			`initial`
124			`begin`
125			`FPGA_CLK2_50 = 1'b0;`
126			`forever #10.0 FPGA_CLK2_50 <= ~FPGA_CLK2_50; // 50 MHz`
127			`end`
128
129			`initial`
130			`begin`
131			`FPGA_CLK3_50 = 1'b0;`
132			`forever #10.0 FPGA_CLK3_50 <= ~FPGA_CLK3_50; // 50 MHz`
133			`end`
134
135			`initial`
136			`begin`
137			`KEY[0] = 1'b1;`
138			`#100 KEY[0] = 1'b0;`
139			`#600 KEY[0] = 1'b1;`
140			`end`
141
142			`//`
143			`// Global initialization`
144			`//------------------------------`
145			`initial`
146			`begin`
147			`error = 0; // Testbench`
148			`stimulus_done = 1;`
149
150			`KEY[1] = 1'b1; // Keys/Buttons`
151
152			`SW[0] = 1'b0; // Switches`
153			`SW[1] = 1'b0;`
154			`SW[2] = 1'b0;`
155			`SW[3] = 1'b0;`
156
157			`ADC_SDO = 1'b1; // ADC`
158
159			`lt24_data_drive_en = 1'b0; // LT24 Data bus`
160			`lt24_data_reg = 16'h0000;`
161			`end`
162
163			`//`
164			`// openMSP430 FPGA Instance`
165			`//----------------------------------`
166
167			`openMSP430_fpga dut (`
168
169			`// USER CLOCKS`
170			`.FPGA_CLK1_50 ( FPGA_CLK1_50 ),`
171			`.FPGA_CLK2_50 ( FPGA_CLK2_50 ),`
172			`.FPGA_CLK3_50 ( FPGA_CLK3_50 ),`
173
174			`// USER INTERFACE (FPGA)`
175			`.KEY ( KEY ),`
176			`.LED ( LED ),`
177			`.SW ( SW ),`
178
179			`// GPIO`
180			`.GPIO_0 ( GPIO_0 ),`
181			`.GPIO_1 ( GPIO_1 ),`
182
183			`// ARDUINO DIGITAL INTERFACE`
184			`.ARDUINO_IO ( ARDUINO_IO ),`
185			`.ARDUINO_RESET_N ( ARDUINO_RESET_N ),`
186
187			`// ADC`
188			`.ADC_CONVST ( ADC_CONVST ),`
189			`.ADC_SCK ( ADC_SCK ),`
190			`.ADC_SDI ( ADC_SDI ),`
191			`.ADC_SDO ( ADC_SDO )`
192			`);`
193
194			`// Pull-ups for the I2C debug interface`
195			`pullup dbg_scl_inst (ARDUINO_IO[15]);`
196			`pullup dbg_sda_inst (ARDUINO_IO[14]);`
197
198			`// Assign LT24 data bus`
199			`assign GPIO_0[8] = lt24_data[0] ;`
200			`assign GPIO_0[7] = lt24_data[1] ;`
201			`assign GPIO_0[6] = lt24_data[2] ;`
202			`assign GPIO_0[5] = lt24_data[3] ;`
203			`assign GPIO_0[13] = lt24_data[4] ;`
204			`assign GPIO_0[14] = lt24_data[5] ;`
205			`assign GPIO_0[15] = lt24_data[6] ;`
206			`assign GPIO_0[16] = lt24_data[7] ;`
207			`assign GPIO_0[17] = lt24_data[8] ;`
208			`assign GPIO_0[18] = lt24_data[9] ;`
209			`assign GPIO_0[19] = lt24_data[10];`
210			`assign GPIO_0[20] = lt24_data[11];`
211			`assign GPIO_0[21] = lt24_data[12];`
212			`assign GPIO_0[22] = lt24_data[13];`
213			`assign GPIO_0[23] = lt24_data[14];`
214			`assign GPIO_0[24] = lt24_data[15];`
215
216
217			`// Debug utility signals`
218			`//----------------------------------------`
219			`msp_debug msp_debug_omsp (`
220
221			`// OUTPUTs`
222			`.e_state (omsp_e_state), // Execution state`
223			`.i_state (omsp_i_state), // Instruction fetch state`
224			`.inst_cycle (omsp_inst_cycle), // Cycle number within current instruction`
225			`.inst_full (omsp_inst_full), // Currently executed instruction (full version)`
226			`.inst_number (omsp_inst_number), // Instruction number since last system reset`
227			`.inst_pc (omsp_inst_pc), // Instruction Program counter`
228			`.inst_short (omsp_inst_short) // Currently executed instruction (short version)`
229			`);`
230
231			`//`
232			`// Generate Waveform`
233			`//----------------------------------------`
234			`initial`
235			`begin`
236			`ifdef VPD_FILE
237			`$vcdplusfile("tb_openMSP430_fpga.vpd");`
238			`$vcdpluson();`
239			`else
240			`ifdef TRN_FILE
241			`$recordfile ("tb_openMSP430_fpga.trn");`
242			`$recordvars;`
243			`else
244			`$dumpfile("tb_openMSP430_fpga.vcd");`
245			`$dumpvars(0, tb_openMSP430_fpga);`
246			`endif
247			`endif
248			`end`
249
250			`//`
251			`// End of simulation`
252			`//----------------------------------------`
253
254			`initial // Timeout`
255			`begin`
256			`ifdef NO_TIMEOUT
257			`else
258			`ifdef VERY_LONG_TIMEOUT
259			`#500000000;`
260			`else
261			`ifdef LONG_TIMEOUT
262			`#5000000;`
263			`else
264			`#500000;`
265			`endif
266			`endif
267			`$display(" ===============================================");`
268			`$display("\| SIMULATION FAILED \|");`
269			`$display("\| (simulation Timeout) \|");`
270			`$display(" ===============================================");`
271			`$finish;`
272			`endif
273			`end`
274
275			`initial // Normal end of test`
276			`begin`
277			`@(omsp_inst_pc===16'hffff)`
278			`$display(" ===============================================");`
279			`if (error!=0)`
280			`begin`
281			`$display("\| SIMULATION FAILED \|");`
282			`$display("\| (some verilog stimulus checks failed) \|");`
283			`end`
284			`else if (~stimulus_done)`
285			`begin`
286			`$display("\| SIMULATION FAILED \|");`
287			`$display("\| (the verilog stimulus didn't complete) \|");`
288			`end`
289			`else`
290			`begin`
291			`$display("\| SIMULATION PASSED \|");`
292			`end`
293			`$display(" ===============================================");`
294			`$finish;`
295			`end`
296
297
298			`//`
299			`// Tasks Definition`
300			`//------------------------------`
301
302			`task tb_error;`
303			`input [65*8:0] error_string;`
304			`begin`
305			`$display("ERROR: %s %t", error_string, $time);`
306			`error = error+1;`
307			`end`
308			`endtask`
309
310
311			`endmodule`