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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_ADC.map.smsg] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
2
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
3
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
4
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
5
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
6
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
7
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
8
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
9
Warning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(2120): conditional expression evaluates to a constant
10
Warning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(2122): conditional expression evaluates to a constant
11
Warning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(2278): conditional expression evaluates to a constant
12
Warning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(3102): conditional expression evaluates to a constant

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