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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_ADC.map.summary] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi 
Analysis & Synthesis Status : Successful - Thu Dec 18 15:55:31 2014
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Quartus II 64-Bit Version : 14.0.2 Build 209 09/17/2014 SJ Full Version
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Revision Name : DE0_NANO_SOC_ADC
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Top-level Entity Name : DE0_NANO_SOC_ADC
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Family : Cyclone V
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Logic utilization (in ALMs) : N/A
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Total registers : 2263
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Total pins : 93
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Total virtual pins : 0
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Total block memory bits : 1,368,512
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Total DSP Blocks : 2
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Total HSSI RX PCSs : 0
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Total HSSI PMA RX Deserializers : 0
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Total HSSI TX PCSs : 0
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Total HSSI PMA TX Serializers : 0
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Total PLLs : 1
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Total DLLs : 0

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