Subversion Repositories openmsp430

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# This .sdc file is created by Terasic Tool.

# Users are recommended to modify this file to match users logic.

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# Create Clock

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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]

create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]

create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]

# for enhancing USB BlasterII to be reliable, 25MHz

create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]

set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]

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# Create Generated Clock

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derive_pll_clocks

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# Set Clock Latency

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# Set Clock Uncertainty

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derive_clock_uncertainty

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# Set Input Delay

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# Set Output Delay

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# Set Clock Groups

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# Set False Path

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# Set Multicycle Path

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# Set Maximum Delay

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# Set Minimum Delay

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# Set Input Transition

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# Set Load

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