OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_ADC.v] - Blame information for rev 221

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 221 olivier.gi
 
2
//=======================================================
3
//  This code is generated by Terasic System Builder
4
//=======================================================
5
 
6
//`define ENABLE_HPS
7
module DE0_NANO_SOC_ADC(
8
 
9
        //////////// ADC //////////
10
        output                                  ADC_CONVST,
11
        output                                  ADC_SCK,
12
        output                                  ADC_SDI,
13
        input                                   ADC_SDO,
14
 
15
        //////////// CLOCK //////////
16
        input                                   FPGA_CLK1_50,
17
        input                                   FPGA_CLK2_50,
18
        input                                   FPGA_CLK3_50,
19
 
20
`ifdef ENABLE_HPS
21
        //////////// HPS //////////
22
        inout                                   HPS_CONV_USB_N,
23
        output              [14:0]               HPS_DDR3_ADDR,
24
        output               [2:0]               HPS_DDR3_BA,
25
        output                                  HPS_DDR3_CAS_N,
26
        output                                  HPS_DDR3_CK_N,
27
        output                                  HPS_DDR3_CK_P,
28
        output                                  HPS_DDR3_CKE,
29
        output                                  HPS_DDR3_CS_N,
30
        output               [3:0]               HPS_DDR3_DM,
31
        inout               [31:0]               HPS_DDR3_DQ,
32
        inout                [3:0]               HPS_DDR3_DQS_N,
33
        inout                [3:0]               HPS_DDR3_DQS_P,
34
        output                                  HPS_DDR3_ODT,
35
        output                                  HPS_DDR3_RAS_N,
36
        output                                  HPS_DDR3_RESET_N,
37
        input                                   HPS_DDR3_RZQ,
38
        output                                  HPS_DDR3_WE_N,
39
        output                                  HPS_ENET_GTX_CLK,
40
        inout                                   HPS_ENET_INT_N,
41
        output                                  HPS_ENET_MDC,
42
        inout                                   HPS_ENET_MDIO,
43
        input                                   HPS_ENET_RX_CLK,
44
        input                [3:0]               HPS_ENET_RX_DATA,
45
        input                                   HPS_ENET_RX_DV,
46
        output               [3:0]               HPS_ENET_TX_DATA,
47
        output                                  HPS_ENET_TX_EN,
48
        inout                                   HPS_GSENSOR_INT,
49
        inout                                   HPS_I2C0_SCLK,
50
        inout                                   HPS_I2C0_SDAT,
51
        inout                                   HPS_I2C1_SCLK,
52
        inout                                   HPS_I2C1_SDAT,
53
        inout                                   HPS_KEY,
54
        inout                                   HPS_LED,
55
        inout                                   HPS_LTC_GPIO,
56
        output                                  HPS_SD_CLK,
57
        inout                                   HPS_SD_CMD,
58
        inout                [3:0]               HPS_SD_DATA,
59
        output                                  HPS_SPIM_CLK,
60
        input                                   HPS_SPIM_MISO,
61
        output                                  HPS_SPIM_MOSI,
62
        inout                                   HPS_SPIM_SS,
63
        input                                   HPS_UART_RX,
64
        output                                  HPS_UART_TX,
65
        input                                   HPS_USB_CLKOUT,
66
        inout                [7:0]               HPS_USB_DATA,
67
        input                                   HPS_USB_DIR,
68
        input                                   HPS_USB_NXT,
69
        output                                  HPS_USB_STP,
70
`endif /*ENABLE_HPS*/
71
 
72
        //////////// KEY //////////
73
        input                [1:0]               KEY,
74
 
75
        //////////// LED //////////
76
        output               [7:0]               LED,
77
 
78
        //////////// SW //////////
79
        input                [3:0]               SW,
80
 
81
        //////////// GPIO_0, GPIO connect to GPIO Default //////////
82
        inout               [35:0]               GPIO_0,
83
 
84
        //////////// GPIO_1, GPIO connect to GPIO Default //////////
85
        inout               [35:0]               GPIO_1
86
);
87
 
88
//=======================================================
89
//  REG/WIRE declarations
90
//=======================================================
91
 
92
//=======================================================
93
//  Structural coding
94
//=======================================================
95
 
96
DE0_NANO_SOC_QSYS u0 (
97
        .clk_clk                        (FPGA_CLK1_50),     // clk.clk
98
        .reset_reset_n                  (KEY[0]),           // reset.reset_n
99
        .sw_external_connection_export  (SW),               // sw_external_connection.export
100
        .adc_ltc2308_conduit_end_CONVST (ADC_CONVST),       // adc_ltc2308_conduit_end.CONVST
101
        .adc_ltc2308_conduit_end_SCK    (ADC_SCK),          //.SCK
102
        .adc_ltc2308_conduit_end_SDI    (ADC_SDI),          //.SDI
103
        .adc_ltc2308_conduit_end_SDO    (ADC_SDO)           //.SDO
104
    );
105
 
106
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.