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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_ADC.v] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi 
 
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//=======================================================
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//  This code is generated by Terasic System Builder
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//=======================================================
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//`define ENABLE_HPS
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module DE0_NANO_SOC_ADC(
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        //////////// ADC //////////
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        output                                  ADC_CONVST,
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        output                                  ADC_SCK,
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        output                                  ADC_SDI,
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        input                                   ADC_SDO,
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        //////////// CLOCK //////////
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        input                                   FPGA_CLK1_50,
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        input                                   FPGA_CLK2_50,
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        input                                   FPGA_CLK3_50,
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`ifdef ENABLE_HPS
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        //////////// HPS //////////
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        inout                                   HPS_CONV_USB_N,
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        output              [14:0]               HPS_DDR3_ADDR,
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        output               [2:0]               HPS_DDR3_BA,
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        output                                  HPS_DDR3_CAS_N,
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        output                                  HPS_DDR3_CK_N,
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        output                                  HPS_DDR3_CK_P,
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        output                                  HPS_DDR3_CKE,
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        output                                  HPS_DDR3_CS_N,
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        output               [3:0]               HPS_DDR3_DM,
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        inout               [31:0]               HPS_DDR3_DQ,
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        inout                [3:0]               HPS_DDR3_DQS_N,
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        inout                [3:0]               HPS_DDR3_DQS_P,
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        output                                  HPS_DDR3_ODT,
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        output                                  HPS_DDR3_RAS_N,
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        output                                  HPS_DDR3_RESET_N,
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        input                                   HPS_DDR3_RZQ,
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        output                                  HPS_DDR3_WE_N,
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        output                                  HPS_ENET_GTX_CLK,
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        inout                                   HPS_ENET_INT_N,
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        output                                  HPS_ENET_MDC,
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        inout                                   HPS_ENET_MDIO,
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        input                                   HPS_ENET_RX_CLK,
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        input                [3:0]               HPS_ENET_RX_DATA,
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        input                                   HPS_ENET_RX_DV,
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        output               [3:0]               HPS_ENET_TX_DATA,
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        output                                  HPS_ENET_TX_EN,
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        inout                                   HPS_GSENSOR_INT,
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        inout                                   HPS_I2C0_SCLK,
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        inout                                   HPS_I2C0_SDAT,
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        inout                                   HPS_I2C1_SCLK,
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        inout                                   HPS_I2C1_SDAT,
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        inout                                   HPS_KEY,
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        inout                                   HPS_LED,
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        inout                                   HPS_LTC_GPIO,
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        output                                  HPS_SD_CLK,
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        inout                                   HPS_SD_CMD,
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        inout                [3:0]               HPS_SD_DATA,
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        output                                  HPS_SPIM_CLK,
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        input                                   HPS_SPIM_MISO,
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        output                                  HPS_SPIM_MOSI,
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        inout                                   HPS_SPIM_SS,
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        input                                   HPS_UART_RX,
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        output                                  HPS_UART_TX,
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        input                                   HPS_USB_CLKOUT,
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        inout                [7:0]               HPS_USB_DATA,
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        input                                   HPS_USB_DIR,
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        input                                   HPS_USB_NXT,
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        output                                  HPS_USB_STP,
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`endif /*ENABLE_HPS*/
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        //////////// KEY //////////
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        input                [1:0]               KEY,
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        //////////// LED //////////
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        output               [7:0]               LED,
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        //////////// SW //////////
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        input                [3:0]               SW,
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        //////////// GPIO_0, GPIO connect to GPIO Default //////////
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        inout               [35:0]               GPIO_0,
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        //////////// GPIO_1, GPIO connect to GPIO Default //////////
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        inout               [35:0]               GPIO_1
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);
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//=======================================================
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//  REG/WIRE declarations
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//=======================================================
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//=======================================================
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//  Structural coding
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//=======================================================
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DE0_NANO_SOC_QSYS u0 (
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        .clk_clk                        (FPGA_CLK1_50),     // clk.clk
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        .reset_reset_n                  (KEY[0]),           // reset.reset_n
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        .sw_external_connection_export  (SW),               // sw_external_connection.export
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        .adc_ltc2308_conduit_end_CONVST (ADC_CONVST),       // adc_ltc2308_conduit_end.CONVST
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        .adc_ltc2308_conduit_end_SCK    (ADC_SCK),          //.SCK
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        .adc_ltc2308_conduit_end_SDI    (ADC_SDI),          //.SDI
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        .adc_ltc2308_conduit_end_SDO    (ADC_SDO)           //.SDO
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    );
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endmodule

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