Subversion Repositories openmsp430

 date="2014.12.18.15:53:19"

 outputDirectory="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/">

     name="AUTO_GENERATION_ID"

     type="Integer"

     defaultValue="0"

     onHdl="0"

     affectsHdl="1" />

     name="AUTO_UNIQUE_ID"

     type="String"

     defaultValue=""

     onHdl="0"

     affectsHdl="1" />

     name="AUTO_DEVICE_FAMILY"

     type="String"

     defaultValue="Cyclone V"

     onHdl="0"

     affectsHdl="1" />

     name="AUTO_DEVICE"

     type="String"

     defaultValue="5CSEMA6F31C6"

     onHdl="0"

     affectsHdl="1" />

     name="AUTO_CLK_CLOCK_RATE"

     type="Long"

     defaultValue="-1"

     onHdl="0"

     affectsHdl="1" />

     name="AUTO_CLK_CLOCK_DOMAIN"

     type="Integer"

     defaultValue="-1"

     onHdl="0"

     affectsHdl="1" />

     name="AUTO_CLK_RESET_DOMAIN"

     type="Integer"

     defaultValue="-1"

     onHdl="0"

     affectsHdl="1" />

       name="adc_ltc2308_conduit_end_CONVST"

       direction="output"

       role="CONVST"

       width="1" />

       name="adc_ltc2308_conduit_end_SCK"

       direction="output"

       role="SCK"

       width="1" />

       name="adc_ltc2308_conduit_end_SDI"

       direction="output"

       role="SDI"

       width="1" />

       name="adc_ltc2308_conduit_end_SDO"

       direction="input"

       role="SDO"

       width="1" />

       name="sw_external_connection_export"

       direction="input"

       role="export"

       width="10" />

       name="pll_sys_locked_export"

       direction="output"

       role="export"

       width="1" />

   path=""

   parameterizationKey="DE0_NANO_SOC_QSYS:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=5CSEMA4U23C6,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_GENERATION_ID=1418889131,AUTO_UNIQUE_ID=(clock_source:14.0:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_nios2_qsys:14.0:bht_ramBlockType=Automatic,breakAbsoluteAddr=526368,breakOffset=32,breakSlave=nios2_qsys.jtag_debug_module,clockFrequency=100000000,cpuID=0,cpuID_stored=0,cpuReset=false,customInstSlavesSystemInfo=<info/>,dataAddrWidth=20,dataSlaveMapParam=<address-map><slave name='sw.s1' start='0x0' end='0x10' /><slave name='onchip_memory2.s1' start='0x40000' end='0x67100' /><slave name='nios2_qsys.jtag_debug_module' start='0x80800' end='0x81000' /><slave name='jtag_uart.avalon_jtag_slave' start='0x81000' end='0x81008' /><slave name='sysid_qsys.control_slave' start='0x81008' end='0x81010' /><slave name='adc_ltc2308.slave' start='0x81010' end='0x81018' /></address-map>,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize=32,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_omitDataMaster=false,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_debugReqSignals=false,debug_embeddedPLL=true,debug_jtagInstanceID=0,debug_level=Level1,debug_triggerArming=true,deviceFamilyName=Cyclone V,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,exceptionAbsoluteAddr=262176,exceptionOffset=32,exceptionSlave=onchip_memory2.s1,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=4096,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=20,instSlaveMapParam=<address-map><slave name='onchip_memory2.s1' start='0x40000' end='0x67100' /><slave name='nios2_qsys.jtag_debug_module' start='0x80800' end='0x81000' /></address-map>,internalIrqMaskSystemInfo=3,manuallyAssignCpuID=true,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=None,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,muldiv_divider=false,muldiv_multiplierType=EmbeddedMulFast,ocimem_ramBlockType=Automatic,regfile_ramBlockType=Automatic,resetAbsoluteAddr=262144,resetOffset=0,resetSlave=onchip_memory2.s1,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateModelChecker=false,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_activateTrace_user=false,setting_allowFullAddressRange=false,setting_alwaysEncrypt=true,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_avalonDebugPortPresent=false,setting_bhtIndexPcOnly=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Automatic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_debugSimGen=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportvectors=false,setting_extraExceptionInfo=false,setting_fullWaveformSignals=false,setting_ic_ecc_present=true,setting_illegalInstructionsTrap=false,setting_illegalMemAccessDetection=false,setting_interruptControllerType=Internal,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_perfCounterWidth=32,setting_performanceCounter=false,setting_preciseDivisionErrorException=false,setting_preciseIllegalMemAccessException=false,setting_preciseSlaveAccessErrorException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,translate_off= "synthesis translate_off" ,translate_on= "synthesis translate_on"  ,userDefinedSettings=)(altera_avalon_onchip_memory2:14.0:allowInSystemMemoryContentEditor=false,autoInitializationFileName=DE0_NANO_SOC_QSYS_onchip_memory2,blockType=AUTO,dataWidth=32,derived_gui_ram_block_type=Automatic,derived_init_file_name=DE0_NANO_SOC_QSYS_onchip_memory2.hex,derived_is_hardcopy=false,derived_set_addr_width=16,derived_set_data_width=32,deviceFamily=Cyclone V,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=false,ecc_enabled=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=160000,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(altera_avalon_sysid_qsys:14.0:AUTO_CLK_CLOCK_RATE=100000000,AUTO_DEVICE_FAMILY=Cyclone V,id=0,timestamp=1418889131)(altera_avalon_jtag_uart:14.0:allowMultipleConnections=false,avalonSpec=2.0,enableInteractiveInput=false,enableInteractiveOutput=false,hubInstanceID=0,legacySignalAllow=false,readBufferDepth=64,readIRQThreshold=8,simInputCharacterStream=,simInteractiveOptions=NO_INTERACTIVE_WINDOWS,useRegistersForReadBuffer=false,useRegistersForWriteBuffer=false,useRelativePathForSimFile=false,writeBufferDepth=64,writeIRQThreshold=8)(altera_pll:14.0:AUTO_REFCLK_CLOCK_RATE=50000000,c_cnt_bypass_en0=false,c_cnt_bypass_en1=false,c_cnt_bypass_en10=true,c_cnt_bypass_en11=true,c_cnt_bypass_en12=true,c_cnt_bypass_en13=true,c_cnt_bypass_en14=true,c_cnt_bypass_en15=true,c_cnt_bypass_en16=true,c_cnt_bypass_en17=true,c_cnt_bypass_en2=false,c_cnt_bypass_en3=true,c_cnt_bypass_en4=true,c_cnt_bypass_en5=true,c_cnt_bypass_en6=true,c_cnt_bypass_en7=true,c_cnt_bypass_en8=true,c_cnt_bypass_en9=true,c_cnt_hi_div0=2,c_cnt_hi_div1=5,c_cnt_hi_div10=1,c_cnt_hi_div11=1,c_cnt_hi_div12=1,c_cnt_hi_div13=1,c_cnt_hi_div14=1,c_cnt_hi_div15=1,c_cnt_hi_div16=1,c_cnt_hi_div17=1,c_cnt_hi_div2=1,c_cnt_hi_div3=1,c_cnt_hi_div4=1,c_cnt_hi_div5=1,c_cnt_hi_div6=1,c_cnt_hi_div7=1,c_cnt_hi_div8=1,c_cnt_hi_div9=1,c_cnt_in_src0=ph_mux_clk,c_cnt_in_src1=ph_mux_clk,c_cnt_in_src10=ph_mux_clk,c_cnt_in_src11=ph_mux_clk,c_cnt_in_src12=ph_mux_clk,c_cnt_in_src13=ph_mux_clk,c_cnt_in_src14=ph_mux_clk,c_cnt_in_src15=ph_mux_clk,c_cnt_in_src16=ph_mux_clk,c_cnt_in_src17=ph_mux_clk,c_cnt_in_src2=ph_mux_clk,c_cnt_in_src3=ph_mux_clk,c_cnt_in_src4=ph_mux_clk,c_cnt_in_src5=ph_mux_clk,c_cnt_in_src6=ph_mux_clk,c_cnt_in_src7=ph_mux_clk,c_cnt_in_src8=ph_mux_clk,c_cnt_in_src9=ph_mux_clk,c_cnt_lo_div0=2,c_cnt_lo_div1=5,c_cnt_lo_div10=1,c_cnt_lo_div11=1,c_cnt_lo_div12=1,c_cnt_lo_div13=1,c_cnt_lo_div14=1,c_cnt_lo_div15=1,c_cnt_lo_div16=1,c_cnt_lo_div17=1,c_cnt_lo_div2=1,c_cnt_lo_div3=1,c_cnt_lo_div4=1,c_cnt_lo_div5=1,c_cnt_lo_div6=1,c_cnt_lo_div7=1,c_cnt_lo_div8=1,c_cnt_lo_div9=1,c_cnt_odd_div_duty_en0=false,c_cnt_odd_div_duty_en1=false,c_cnt_odd_div_duty_en10=false,c_cnt_odd_div_duty_en11=false,c_cnt_odd_div_duty_en12=false,c_cnt_odd_div_duty_en13=false,c_cnt_odd_div_duty_en14=false,c_cnt_odd_div_duty_en15=false,c_cnt_odd_div_duty_en16=false,c_cnt_odd_div_duty_en17=false,c_cnt_odd_div_duty_en2=false,c_cnt_odd_div_duty_en3=false,c_cnt_odd_div_duty_en4=false,c_cnt_odd_div_duty_en5=false,c_cnt_odd_div_duty_en6=false,c_cnt_odd_div_duty_en7=false,c_cnt_odd_div_duty_en8=false,c_cnt_odd_div_duty_en9=false,c_cnt_ph_mux_prst0=0,c_cnt_ph_mux_prst1=0,c_cnt_ph_mux_prst10=0,c_cnt_ph_mux_prst11=0,c_cnt_ph_mux_prst12=0,c_cnt_ph_mux_prst13=0,c_cnt_ph_mux_prst14=0,c_cnt_ph_mux_prst15=0,c_cnt_ph_mux_prst16=0,c_cnt_ph_mux_prst17=0,c_cnt_ph_mux_prst2=0,c_cnt_ph_mux_prst3=0,c_cnt_ph_mux_prst4=0,c_cnt_ph_mux_prst5=0,c_cnt_ph_mux_prst6=0,c_cnt_ph_mux_prst7=0,c_cnt_ph_mux_prst8=0,c_cnt_ph_mux_prst9=0,c_cnt_prst0=1,c_cnt_prst1=1,c_cnt_prst10=1,c_cnt_prst11=1,c_cnt_prst12=1,c_cnt_prst13=1,c_cnt_prst14=1,c_cnt_prst15=1,c_cnt_prst16=1,c_cnt_prst17=1,c_cnt_prst2=1,c_cnt_prst3=1,c_cnt_prst4=1,c_cnt_prst5=1,c_cnt_prst6=1,c_cnt_prst7=1,c_cnt_prst8=1,c_cnt_prst9=1,debug_print_output=false,debug_use_rbc_taf_method=false,device=5CSEMA4U23C6,device_family=Cyclone V,duty_cycle0=50,duty_cycle1=50,duty_cycle10=50,duty_cycle11=50,duty_cycle12=50,duty_cycle13=50,duty_cycle14=50,duty_cycle15=50,duty_cycle16=50,duty_cycle17=50,duty_cycle2=50,duty_cycle3=50,duty_cycle4=50,duty_cycle5=50,duty_cycle6=50,duty_cycle7=50,duty_cycle8=50,duty_cycle9=50,fractional_vco_multiplier=false,gui_active_clk=false,gui_actual_divide_factor0=4,gui_actual_divide_factor1=10,gui_actual_divide_factor10=1,gui_actual_divide_factor11=1,gui_actual_divide_factor12=1,gui_actual_divide_factor13=1,gui_actual_divide_factor14=1,gui_actual_divide_factor15=1,gui_actual_divide_factor16=1,gui_actual_divide_factor17=1,gui_actual_divide_factor2=2,gui_actual_divide_factor3=1,gui_actual_divide_factor4=1,gui_actual_divide_factor5=1,gui_actual_divide_factor6=1,gui_actual_divide_factor7=1,gui_actual_divide_factor8=1,gui_actual_divide_factor9=1,gui_actual_frac_multiply_factor0=1,gui_actual_frac_multiply_factor1=1,gui_actual_frac_multiply_factor10=1,gui_actual_frac_multiply_factor11=1,gui_actual_frac_multiply_factor12=1,gui_actual_frac_multiply_factor13=1,gui_actual_frac_multiply_factor14=1,gui_actual_frac_multiply_factor15=1,gui_actual_frac_multiply_factor16=1,gui_actual_frac_multiply_factor17=1,gui_actual_frac_multiply_factor2=1,gui_actual_frac_multiply_factor3=1,gui_actual_frac_multiply_factor4=1,gui_actual_frac_multiply_factor5=1,gui_actual_frac_multiply_factor6=1,gui_actual_frac_multiply_factor7=1,gui_actual_frac_multiply_factor8=1,gui_actual_frac_multiply_factor9=1,gui_actual_multiply_factor0=8,gui_actual_multiply_factor1=8,gui_actual_multiply_factor10=1,gui_actual_multiply_factor11=1,gui_actual_multiply_factor12=1,gui_actual_multiply_factor13=1,gui_actual_multiply_factor14=1,gui_actual_multiply_factor15=1,gui_actual_multiply_factor16=1,gui_actual_multiply_factor17=1,gui_actual_multiply_factor2=8,gui_actual_multiply_factor3=1,gui_actual_multiply_factor4=1,gui_actual_multiply_factor5=1,gui_actual_multiply_factor6=1,gui_actual_multiply_factor7=1,gui_actual_multiply_factor8=1,gui_actual_multiply_factor9=1,gui_actual_output_clock_frequency0=0 MHz,gui_actual_output_clock_frequency1=0 MHz,gui_actual_output_clock_frequency10=0 MHz,gui_actual_output_clock_frequency11=0 MHz,gui_actual_output_clock_frequency12=0 MHz,gui_actual_output_clock_frequency13=0 MHz,gui_actual_output_clock_frequency14=0 MHz,gui_actual_output_clock_frequency15=0 MHz,gui_actual_output_clock_frequency16=0 MHz,gui_actual_output_clock_frequency17=0 MHz,gui_actual_output_clock_frequency2=0 MHz,gui_actual_output_clock_frequency3=0 MHz,gui_actual_output_clock_frequency4=0 MHz,gui_actual_output_clock_frequency5=0 MHz,gui_actual_output_clock_frequency6=0 MHz,gui_actual_output_clock_frequency7=0 MHz,gui_actual_output_clock_frequency8=0 MHz,gui_actual_output_clock_frequency9=0 MHz,gui_actual_phase_shift0=0,gui_actual_phase_shift1=0,gui_actual_phase_shift10=0,gui_actual_phase_shift11=0,gui_actual_phase_shift12=0,gui_actual_phase_shift13=0,gui_actual_phase_shift14=0,gui_actual_phase_shift15=0,gui_actual_phase_shift16=0,gui_actual_phase_shift17=0,gui_actual_phase_shift2=0,gui_actual_phase_shift3=0,gui_actual_phase_shift4=0,gui_actual_phase_shift5=0,gui_actual_phase_shift6=0,gui_actual_phase_shift7=0,gui_actual_phase_shift8=0,gui_actual_phase_shift9=0,gui_cascade_counter0=false,gui_cascade_counter1=false,gui_cascade_counter10=false,gui_cascade_counter11=false,gui_cascade_counter12=false,gui_cascade_counter13=false,gui_cascade_counter14=false,gui_cascade_counter15=false,gui_cascade_counter16=false,gui_cascade_counter17=false,gui_cascade_counter2=false,gui_cascade_counter3=false,gui_cascade_counter4=false,gui_cascade_counter5=false,gui_cascade_counter6=false,gui_cascade_counter7=false,gui_cascade_counter8=false,gui_cascade_counter9=false,gui_cascade_outclk_index=0,gui_channel_spacing=0.0,gui_clk_bad=false,gui_device_speed_grade=2,gui_divide_factor_c0=1,gui_divide_factor_c1=1,gui_divide_factor_c10=1,gui_divide_factor_c11=1,gui_divide_factor_c12=1,gui_divide_factor_c13=1,gui_divide_factor_c14=1,gui_divide_factor_c15=1,gui_divide_factor_c16=1,gui_divide_factor_c17=1,gui_divide_factor_c2=1,gui_divide_factor_c3=1,gui_divide_factor_c4=1,gui_divide_factor_c5=1,gui_divide_factor_c6=1,gui_divide_factor_c7=1,gui_divide_factor_c8=1,gui_divide_factor_c9=1,gui_divide_factor_n=1,gui_dps_cntr=C0,gui_dps_dir=Positive,gui_dps_num=1,gui_dsm_out_sel=1st_order,gui_duty_cycle0=50,gui_duty_cycle1=50,gui_duty_cycle10=50,gui_duty_cycle11=50,gui_duty_cycle12=50,gui_duty_cycle13=50,gui_duty_cycle14=50,gui_duty_cycle15=50,gui_duty_cycle16=50,gui_duty_cycle17=50,gui_duty_cycle2=50,gui_duty_cycle3=50,gui_duty_cycle4=50,gui_duty_cycle5=50,gui_duty_cycle6=50,gui_duty_cycle7=50,gui_duty_cycle8=50,gui_duty_cycle9=50,gui_en_adv_params=false,gui_en_dps_ports=false,gui_en_lvds_ports=false,gui_en_phout_ports=false,gui_en_reconf=false,gui_enable_cascade_in=false,gui_enable_cascade_out=false,gui_enable_mif_dps=false,gui_feedback_clock=Global Clock,gui_frac_multiply_factor=1,gui_fractional_cout=32,gui_mif_generate=false,gui_multiply_factor=1,gui_number_of_clocks=3,gui_operation_mode=normal,gui_output_clock_frequency0=100.0,gui_output_clock_frequency1=40.0,gui_output_clock_frequency10=100.0,gui_output_clock_frequency11=100.0,gui_output_clock_frequency12=100.0,gui_output_clock_frequency13=100.0,gui_output_clock_frequency14=100.0,gui_output_clock_frequency15=100.0,gui_output_clock_frequency16=100.0,gui_output_clock_frequency17=100.0,gui_output_clock_frequency2=200.0,gui_output_clock_frequency3=120.0,gui_output_clock_frequency4=100.0,gui_output_clock_frequency5=100.0,gui_output_clock_frequency6=100.0,gui_output_clock_frequency7=100.0,gui_output_clock_frequency8=100.0,gui_output_clock_frequency9=100.0,gui_parameter_list=M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset,gui_parameter_values=4,4,256,256,false,true,false,false,2,2,1,0,ph_mux_clk,false,false,5,5,1,0,ph_mux_clk,false,false,1,1,1,0,ph_mux_clk,false,false,2,20,4000,400.0 MHz,1,gclk,glb,fb_1,ph_mux_clk,false,gui_phase_shift0=0,gui_phase_shift1=0,gui_phase_shift10=0,gui_phase_shift11=0,gui_phase_shift12=0,gui_phase_shift13=0,gui_phase_shift14=0,gui_phase_shift15=0,gui_phase_shift16=0,gui_phase_shift17=0,gui_phase_shift2=0,gui_phase_shift3=0,gui_phase_shift4=0,gui_phase_shift5=0,gui_phase_shift6=0,gui_phase_shift7=0,gui_phase_shift8=0,gui_phase_shift9=0,gui_phase_shift_deg0=0.0,gui_phase_shift_deg1=0.0,gui_phase_shift_deg10=0.0,gui_phase_shift_deg11=0.0,gui_phase_shift_deg12=0.0,gui_phase_shift_deg13=0.0,gui_phase_shift_deg14=0.0,gui_phase_shift_deg15=0.0,gui_phase_shift_deg16=0.0,gui_phase_shift_deg17=0.0,gui_phase_shift_deg2=0.0,gui_phase_shift_deg3=0.0,gui_phase_shift_deg4=0.0,gui_phase_shift_deg5=0.0,gui_phase_shift_deg6=0.0,gui_phase_shift_deg7=0.0,gui_phase_shift_deg8=0.0,gui_phase_shift_deg9=0.0,gui_phout_division=1,gui_pll_auto_reset=Off,gui_pll_bandwidth_preset=Auto,gui_pll_cascading_mode=Create an adjpllin signal to connect with an upstream PLL,gui_pll_mode=Integer-N PLL,gui_ps_units0=ps,gui_ps_units1=ps,gui_ps_units10=ps,gui_ps_units11=ps,gui_ps_units12=ps,gui_ps_units13=ps,gui_ps_units14=ps,gui_ps_units15=ps,gui_ps_units16=ps,gui_ps_units17=ps,gui_ps_units2=ps,gui_ps_units3=ps,gui_ps_units4=ps,gui_ps_units5=ps,gui_ps_units6=ps,gui_ps_units7=ps,gui_ps_units8=ps,gui_ps_units9=ps,gui_refclk1_frequency=100.0,gui_refclk_switch=false,gui_reference_clock_frequency=50.0,gui_switchover_delay=0,gui_switchover_mode=Automatic Switchover,gui_use_locked=true,m_cnt_bypass_en=false,m_cnt_hi_div=4,m_cnt_lo_div=4,m_cnt_odd_div_duty_en=false,mimic_fbclk_type=gclk,n_cnt_bypass_en=true,n_cnt_hi_div=256,n_cnt_lo_div=256,n_cnt_odd_div_duty_en=false,number_of_cascade_counters=0,number_of_clocks=3,operation_mode=normal,output_clock_frequency0=100.000000 MHz,output_clock_frequency1=40.000000 MHz,output_clock_frequency10=0 MHz,output_clock_frequency11=0 MHz,output_clock_frequency12=0 MHz,output_clock_frequency13=0 MHz,output_clock_frequency14=0 MHz,output_clock_frequency15=0 MHz,output_clock_frequency16=0 MHz,output_clock_frequency17=0 MHz,output_clock_frequency2=200.000000 MHz,output_clock_frequency3=0 MHz,output_clock_frequency4=0 MHz,output_clock_frequency5=0 MHz,output_clock_frequency6=0 MHz,output_clock_frequency7=0 MHz,output_clock_frequency8=0 MHz,output_clock_frequency9=0 MHz,phase_shift0=0 ps,phase_shift1=0 ps,phase_shift10=0 ps,phase_shift11=0 ps,phase_shift12=0 ps,phase_shift13=0 ps,phase_shift14=0 ps,phase_shift15=0 ps,phase_shift16=0 ps,phase_shift17=0 ps,phase_shift2=0 ps,phase_shift3=0 ps,phase_shift4=0 ps,phase_shift5=0 ps,phase_shift6=0 ps,phase_shift7=0 ps,phase_shift8=0 ps,phase_shift9=0 ps,pll_auto_clk_sw_en=false,pll_bwctrl=4000,pll_clk_loss_sw_en=false,pll_clk_sw_dly=0,pll_clkin_0_src=clk_0,pll_clkin_1_src=clk_0,pll_cp_current=20,pll_dsm_out_sel=1st_order,pll_fbclk_mux_1=glb,pll_fbclk_mux_2=fb_1,pll_fractional_cout=32,pll_fractional_division=1,pll_m_cnt_in_src=ph_mux_clk,pll_manu_clk_sw_en=false,pll_output_clk_frequency=400.0 MHz,pll_slf_rst=false,pll_subtype=General,pll_type=General,pll_vco_div=2,pll_vcoph_div=1,refclk1_frequency=100.0 MHz,reference_clock_frequency=50.0 MHz)(adc_ltc2308:1.1:AUTO_CLOCK_SINK_ADC_CLOCK_RATE=40000000,AUTO_CLOCK_SINK_CLOCK_RATE=100000000)(altera_avalon_pio:14.0:bitClearingEdgeCapReg=false,bitModifyingOutReg=false,captureEdge=true,clockRate=100000000,derived_capture=true,derived_do_test_bench_wiring=false,derived_edge_type=ANY,derived_has_in=true,derived_has_irq=true,derived_has_out=false,derived_has_tri=false,derived_irq_type=EDGE,direction=Input,edgeType=ANY,generateIRQ=true,irqType=EDGE,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=10)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00080800,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00080800,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00040000,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00081008,defaultConnection=false)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00081000,defaultConnection=false)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(clock:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00040000,defaultConnection=false)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(reset:14.0:)(interrupt:14.0:irqNumber=0)(clock:14.0:)(clock:14.0:)(reset:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x00081010,defaultConnection=false)(clock:14.0:)(reset:14.0:)(avalon:14.0:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(interrupt:14.0:irqNumber=1)(reset:14.0:)"

   instancePathKey="DE0_NANO_SOC_QSYS"

   kind="DE0_NANO_SOC_QSYS"

   version="1.0"

   name="DE0_NANO_SOC_QSYS">

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/DE0_NANO_SOC_QSYS.v"

       type="VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys.ocp"

       type="OTHER"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys.sdc"

       type="SDC"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys.v"

       type="VERILOG_ENCRYPT"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_bht_ram.mif"

       type="MIF"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_dc_tag_ram.mif"

       type="MIF"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_ic_tag_ram.mif"

       type="MIF"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_wrapper.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_mult_cell.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_ociram_default_contents.mif"

       type="MIF"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_oci_test_bench.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_rf_ram_a.mif"

       type="MIF"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_rf_ram_b.mif"

       type="MIF"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_nios2_qsys_test_bench.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_onchip_memory2.hex"

       type="HEX"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_onchip_memory2.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_sysid_qsys.v"

       type="VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_jtag_uart.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_pll_sys.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_pll_sys.qip"

       type="OTHER"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/adc_ltc2308_fifo.v"

       type="VERILOG"

       attributes="TOP_LEVEL_FILE" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/adc_ltc2308.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/adc_data_fifo.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_sw.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0.v"

       type="VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_master_translator.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_master_agent.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v"

       type="VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_router.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_reorder_memory.sv"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v"

       type="SYSTEM_VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux_001.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux_001.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/DE0_NANO_SOC_QSYS_irq_mapper.sv"

       type="SYSTEM_VERILOG" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_reset_controller.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_reset_synchronizer.v"

       type="VERILOG"

       attributes="" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/DE0_NANO_SOC_QSYS/synthesis/submodules/altera_reset_controller.sdc"

       type="SDC"

       attributes="" />

       path="C:/altera/14.0/ip/altera/nios2_ip/altera_nios2/altera_nios2_qsys_hw.tcl" />

       path="C:/altera/14.0/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />

       path="C:/altera/14.0/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />

       path="C:/altera/14.0/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.version.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />

       path="C:/altera/14.0/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />

       path="D:/SVN/DE0_Nano_soc/DE0_NANO_SOC_ADC/ip/ADC_LTC2308_FIFO/adc_ltc2308_hw.tcl" />

       path="C:/altera/14.0/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />

       path="C:/altera/14.0/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />

       path="C:/altera/14.0/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_arbitrator.sv" />

       path="C:/altera/14.0/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />

       path="C:/altera/14.0/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />

   queue size: 0 starting:DE0_NANO_SOC_QSYS "DE0_NANO_SOC_QSYS"

   Transform: CustomInstructionTransform

   No custom instruction connections, skipping transform 

   8 modules, 26 connections]]>

   Transform: MMTransform

   Transform: InitialInterconnectTransform

   8 modules, 21 connections]]>

   Transform: TerminalIdAssignmentUpdateTransform

   Transform: DefaultSlaveTransform

   Transform: TranslatorTransform

   16 modules, 48 connections]]>

   Transform: IDPadTransform

   Transform: DomainTransform

   Transform merlin_domain_transform not run on matched interfaces nios2_qsys.instruction_master and nios2_qsys_instruction_master_translator.avalon_anti_master_0

   Transform merlin_domain_transform not run on matched interfaces nios2_qsys.data_master and nios2_qsys_data_master_translator.avalon_anti_master_0

   Transform merlin_domain_transform not run on matched interfaces nios2_qsys_jtag_debug_module_translator.avalon_anti_slave_0 and nios2_qsys.jtag_debug_module

   Transform merlin_domain_transform not run on matched interfaces onchip_memory2_s1_translator.avalon_anti_slave_0 and onchip_memory2.s1

   Transform merlin_domain_transform not run on matched interfaces sysid_qsys_control_slave_translator.avalon_anti_slave_0 and sysid_qsys.control_slave

   Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave

   Transform merlin_domain_transform not run on matched interfaces adc_ltc2308_slave_translator.avalon_anti_slave_0 and adc_ltc2308.slave

   Transform merlin_domain_transform not run on matched interfaces sw_s1_translator.avalon_anti_slave_0 and sw.s1

   31 modules, 133 connections]]>

   Transform: RouterTransform

   39 modules, 160 connections]]>

   Transform: TrafficLimiterTransform

   41 modules, 170 connections]]>

   Transform: BurstTransform

   Transform: TreeTransform

   Transform: NetworkToSwitchTransform

   56 modules, 205 connections]]>

   Transform: WidthTransform

   Transform: RouterTableTransform

   Transform: ThreadIDMappingTableTransform

   Transform: ClockCrossingTransform

   Transform: PipelineTransform

   Transform: SpotPipelineTransform

   Transform: PerformanceMonitorTransform

   Transform: TrafficLimiterUpdateTransform

   56 modules, 207 connections]]>

   Transform: InsertClockAndResetBridgesTransform

   59 modules, 264 connections]]>

   Transform: InterconnectConnectionsTagger

   Transform: HierarchyTransform

   9 modules, 30 connections]]>

   9 modules, 30 connections]]>

   Transform: InterruptMapperTransform

   10 modules, 34 connections]]>

   Transform: InterruptSyncTransform

   Transform: InterruptFanoutTransform

   Transform: AvalonStreamingTransform

   Transform: ResetAdaptation

   15 modules, 47 connections]]>

   DE0_NANO_SOC_QSYS" reuses altera_nios2_qsys "submodules/DE0_NANO_SOC_QSYS_nios2_qsys"]]>

   DE0_NANO_SOC_QSYS" reuses altera_avalon_onchip_memory2 "submodules/DE0_NANO_SOC_QSYS_onchip_memory2"]]>

   DE0_NANO_SOC_QSYS" reuses altera_avalon_sysid_qsys "submodules/DE0_NANO_SOC_QSYS_sysid_qsys"]]>

   DE0_NANO_SOC_QSYS" reuses altera_avalon_jtag_uart "submodules/DE0_NANO_SOC_QSYS_jtag_uart"]]>

   DE0_NANO_SOC_QSYS" reuses altera_pll "submodules/DE0_NANO_SOC_QSYS_pll_sys"]]>

   DE0_NANO_SOC_QSYS" reuses adc_ltc2308 "submodules/adc_ltc2308_fifo"]]>

   DE0_NANO_SOC_QSYS" reuses altera_avalon_pio "submodules/DE0_NANO_SOC_QSYS_sw"]]>

   DE0_NANO_SOC_QSYS" reuses altera_mm_interconnect "submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0"]]>

   DE0_NANO_SOC_QSYS" reuses altera_irq_mapper "submodules/DE0_NANO_SOC_QSYS_irq_mapper"]]>

   DE0_NANO_SOC_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller"]]>

   DE0_NANO_SOC_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller"]]>

   DE0_NANO_SOC_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller"]]>

   queue size: 11 starting:altera_nios2_qsys "submodules/DE0_NANO_SOC_QSYS_nios2_qsys"

   Starting RTL generation for module 'DE0_NANO_SOC_QSYS_nios2_qsys'

     Generation command is [exec C:/altera/14.0/quartus/bin64/eperlcmd.exe -I C:/altera/14.0/quartus/bin64/perl/lib -I C:/altera/14.0/quartus/sopc_builder/bin/europa -I C:/altera/14.0/quartus/sopc_builder/bin/perl_lib -I C:/altera/14.0/quartus/sopc_builder/bin -I C:/altera/14.0/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/14.0/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/14.0/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/14.0/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/14.0/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=DE0_NANO_SOC_QSYS_nios2_qsys --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0001_nios2_qsys_gen/ --quartus_bindir=C:/altera/14.0/quartus/bin64 --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0001_nios2_qsys_gen//DE0_NANO_SOC_QSYS_nios2_qsys_processor_configuration.pl  --do_build_sim=0  ]

   # 2014.12.18 15:52:25 (*) Starting Nios II generation

   # 2014.12.18 15:52:25 (*)   Checking for plaintext license.

   # 2014.12.18 15:52:37 (*)   Plaintext license not found.

   # 2014.12.18 15:52:37 (*)   Checking for encrypted license (non-evaluation).

   # 2014.12.18 15:52:57 (*)   Encrypted license found.  SOF will not be time-limited.

   # 2014.12.18 15:52:57 (*)   Elaborating CPU configuration settings

   # 2014.12.18 15:52:57 (*)   Creating all objects for CPU

   # 2014.12.18 15:52:57 (*)     Testbench

   # 2014.12.18 15:52:58 (*)     Instruction decoding

   # 2014.12.18 15:52:58 (*)       Instruction fields

   # 2014.12.18 15:52:58 (*)       Instruction decodes

   # 2014.12.18 15:52:59 (*)       Signals for RTL simulation waveforms

   # 2014.12.18 15:52:59 (*)       Instruction controls

   # 2014.12.18 15:52:59 (*)     Pipeline frontend

   # 2014.12.18 15:52:59 (*)     Pipeline backend

   # 2014.12.18 15:53:03 (*)   Generating RTL from CPU objects

   # 2014.12.18 15:53:07 (*)   Creating encrypted RTL

   # 2014.12.18 15:53:09 (*) Done Nios II generation

   Done RTL generation for module 'DE0_NANO_SOC_QSYS_nios2_qsys'

   DE0_NANO_SOC_QSYS" instantiated altera_nios2_qsys "nios2_qsys"]]>

   queue size: 10 starting:altera_avalon_onchip_memory2 "submodules/DE0_NANO_SOC_QSYS_onchip_memory2"

   Starting RTL generation for module 'DE0_NANO_SOC_QSYS_onchip_memory2'

     Generation command is [exec C:/altera/14.0/quartus/bin64/perl/bin/perl.exe -I C:/altera/14.0/quartus/bin64/perl/lib -I C:/altera/14.0/quartus/sopc_builder/bin/europa -I C:/altera/14.0/quartus/sopc_builder/bin/perl_lib -I C:/altera/14.0/quartus/sopc_builder/bin -I C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=DE0_NANO_SOC_QSYS_onchip_memory2 --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0002_onchip_memory2_gen/ --quartus_dir=C:/altera/14.0/quartus --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0002_onchip_memory2_gen//DE0_NANO_SOC_QSYS_onchip_memory2_component_configuration.pl  --do_build_sim=0  ]

   Done RTL generation for module 'DE0_NANO_SOC_QSYS_onchip_memory2'

   DE0_NANO_SOC_QSYS" instantiated altera_avalon_onchip_memory2 "onchip_memory2"]]>

   queue size: 9 starting:altera_avalon_sysid_qsys "submodules/DE0_NANO_SOC_QSYS_sysid_qsys"

   DE0_NANO_SOC_QSYS" instantiated altera_avalon_sysid_qsys "sysid_qsys"]]>

   queue size: 8 starting:altera_avalon_jtag_uart "submodules/DE0_NANO_SOC_QSYS_jtag_uart"

   Starting RTL generation for module 'DE0_NANO_SOC_QSYS_jtag_uart'

     Generation command is [exec C:/altera/14.0/quartus/bin64/perl/bin/perl.exe -I C:/altera/14.0/quartus/bin64/perl/lib -I C:/altera/14.0/quartus/sopc_builder/bin/europa -I C:/altera/14.0/quartus/sopc_builder/bin/perl_lib -I C:/altera/14.0/quartus/sopc_builder/bin -I C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=DE0_NANO_SOC_QSYS_jtag_uart --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0004_jtag_uart_gen/ --quartus_dir=C:/altera/14.0/quartus --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0004_jtag_uart_gen//DE0_NANO_SOC_QSYS_jtag_uart_component_configuration.pl  --do_build_sim=0  ]

   Done RTL generation for module 'DE0_NANO_SOC_QSYS_jtag_uart'

   DE0_NANO_SOC_QSYS" instantiated altera_avalon_jtag_uart "jtag_uart"]]>

   queue size: 7 starting:altera_pll "submodules/DE0_NANO_SOC_QSYS_pll_sys"

   DE0_NANO_SOC_QSYS" instantiated altera_pll "pll_sys"]]>

   queue size: 6 starting:adc_ltc2308 "submodules/adc_ltc2308_fifo"

   DE0_NANO_SOC_QSYS" instantiated adc_ltc2308 "adc_ltc2308"]]>

   queue size: 5 starting:altera_avalon_pio "submodules/DE0_NANO_SOC_QSYS_sw"

   Starting RTL generation for module 'DE0_NANO_SOC_QSYS_sw'

     Generation command is [exec C:/altera/14.0/quartus/bin64/perl/bin/perl.exe -I C:/altera/14.0/quartus/bin64/perl/lib -I C:/altera/14.0/quartus/sopc_builder/bin/europa -I C:/altera/14.0/quartus/sopc_builder/bin/perl_lib -I C:/altera/14.0/quartus/sopc_builder/bin -I C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/14.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=DE0_NANO_SOC_QSYS_sw --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0007_sw_gen/ --quartus_dir=C:/altera/14.0/quartus --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt6422_7349580087849942241.dir/0007_sw_gen//DE0_NANO_SOC_QSYS_sw_component_configuration.pl  --do_build_sim=0  ]

   Done RTL generation for module 'DE0_NANO_SOC_QSYS_sw'

   DE0_NANO_SOC_QSYS" instantiated altera_avalon_pio "sw"]]>

   queue size: 4 starting:altera_mm_interconnect "submodules/DE0_NANO_SOC_QSYS_mm_interconnect_0"

   Transform: CustomInstructionTransform

   No custom instruction connections, skipping transform 

   51 modules, 170 connections]]>

   Transform: MMTransform

   Transform: InitialInterconnectTransform

   0 modules, 0 connections]]>

   Transform: TerminalIdAssignmentUpdateTransform

   Transform: DefaultSlaveTransform

   Transform: TranslatorTransform

   No Avalon connections, skipping transform 

   Transform: IDPadTransform

   Transform: DomainTransform

   Transform: RouterTransform

   Transform: TrafficLimiterTransform

   Transform: BurstTransform

   Transform: TreeTransform

   Transform: NetworkToSwitchTransform

   Transform: WidthTransform

   Transform: RouterTableTransform

   Transform: ThreadIDMappingTableTransform

   Transform: ClockCrossingTransform

   Transform: PipelineTransform

   Transform: SpotPipelineTransform

   Transform: PerformanceMonitorTransform

   Transform: TrafficLimiterUpdateTransform

   Transform: InsertClockAndResetBridgesTransform

   Transform: InterconnectConnectionsTagger

   Transform: HierarchyTransform

   51 modules, 170 connections]]>

   Transform: InitialInterconnectTransform

   0 modules, 0 connections]]>

   Transform: TerminalIdAssignmentUpdateTransform

   Transform: DefaultSlaveTransform

   Transform: TranslatorTransform

   No Avalon connections, skipping transform 

   Transform: IDPadTransform

   Transform: DomainTransform

   Transform: RouterTransform

   Transform: TrafficLimiterTransform

   Transform: BurstTransform

   Transform: TreeTransform

   Transform: NetworkToSwitchTransform

   Transform: WidthTransform

   Transform: RouterTableTransform

   Transform: ThreadIDMappingTableTransform

   Transform: ClockCrossingTransform

   Transform: PipelineTransform

   Transform: SpotPipelineTransform

   Transform: PerformanceMonitorTransform

   Transform: TrafficLimiterUpdateTransform

   Transform: InsertClockAndResetBridgesTransform

   Transform: InterconnectConnectionsTagger

   Transform: HierarchyTransform

   51 modules, 170 connections]]>

   Transform: InitialInterconnectTransform

   0 modules, 0 connections]]>

   Transform: TerminalIdAssignmentUpdateTransform

   Transform: DefaultSlaveTransform

   Transform: TranslatorTransform

   No Avalon connections, skipping transform 

   Transform: IDPadTransform

   Transform: DomainTransform

   Transform: RouterTransform

   Transform: TrafficLimiterTransform

   Transform: BurstTransform

   Transform: TreeTransform

   Transform: NetworkToSwitchTransform

   Transform: WidthTransform

   Transform: RouterTableTransform

   Transform: ThreadIDMappingTableTransform

   Transform: ClockCrossingTransform

   Transform: PipelineTransform

   Transform: SpotPipelineTransform