OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [synthesis/] [DE0_NANO_SOC_QSYS.regmap] - Blame information for rev 221

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 221 olivier.gi
2
3
DE0_NANO_SOC_QSYS
4
5
6
      DE0_NANO_SOC_QSYS_sw_s1_altera_avalon_pio0x00000000
7
      
8
        0x0
9
        32
10
        registers
11
      
12
      
13
        
14
         DATA
15
         Data
16
         Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).
17
         0x0
18
         32
19
         read-write
20
         0x0
21
         0xffffffff
22
         
23
           data
24
           Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.
25
            0x0
26
            32
27
            read-write
28
        
29
       
30
     
31
        
32
         DIRECTION
33
         Direction
34
         The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.
35
         0x4
36
         32
37
         read-write
38
         0x0
39
         0xffffffff
40
         
41
           direction
42
            Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.
43
            0x0
44
            32
45
            read-write
46
        
47
       
48
     
49
        
50
         IRQ_MASK
51
         Interrupt mask
52
         Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.
53
         0x8
54
         32
55
         read-write
56
         0x0
57
         0xffffffff
58
         
59
           interruptmask
60
            IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.
61
            0x0
62
            32
63
            read-write
64
        
65
       
66
     
67
        
68
         EDGE_CAP
69
         Edge capture
70
         Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.
71
         0xc
72
         32
73
         read-write
74
         0x0
75
         0xffffffff
76
         
77
           edgecapture
78
            Edge detection for each input port.
79
            0x0
80
            32
81
            read-write
82
        
83
       
84
     
85
        
86
         SET_BIT
87
         Outset
88
         You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.
89
         0x10
90
         32
91
         write-only
92
         0x0
93
         0xffffffff
94
         
95
           outset
96
            Specifies which bit of the output port to set.
97
            0x0
98
            32
99
            write-only
100
        
101
       
102
     
103
        
104
         CLEAR_BITS
105
         Outclear
106
         You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.
107
         0x14
108
         32
109
         write-only
110
         0x0
111
         0xffffffff
112
         
113
           outclear
114
            Specifies which output bit to clear.
115
            0x0
116
            32
117
            write-only
118
        
119
       
120
     
121
    
122
   
123
  
124
      DE0_NANO_SOC_QSYS_jtag_uart_avalon_jtag_slave_altera_avalon_jtag_uart0x00000000
125
      
126
        0x0
127
        8
128
        registers
129
      
130
      
131
        
132
         DATA
133
         Data
134
         Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.
135
         0x0
136
         32
137
         read-write
138
         0x0
139
         0xffffffff
140
         
141
           data
142
           The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.
143
            0x0
144
            8
145
            read-write
146
        
147
           rvalid
148
           Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.
149
            0xf
150
            1
151
            read-only
152
        
153
           ravail
154
           The number of characters remaining in the read FIFO (after the current read).
155
            0x10
156
            16
157
            read-only
158
        
159
       
160
     
161
        
162
         CONTROL
163
         Control
164
         Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.
165
         0x4
166
         32
167
         read-write
168
         0x0
169
         0xffffffff
170
         
171
           re
172
            Interrupt-enable bit for read interrupts.
173
            0x0
174
            1
175
            read-write
176
        
177
           we
178
            Interrupt-enable bit for write interrupts
179
            0x1
180
            1
181
            read-write
182
        
183
           ri
184
            Indicates that the read interrupt is pending.
185
            0x8
186
            1
187
            read-only
188
        
189
           wi
190
            Indicates that the write interrupt is pending.
191
            0x9
192
            1
193
            read-only
194
        
195
           ac
196
            Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.
197
            0xa
198
            1
199
            read-write
200
        
201
           wspace
202
            The number of spaces available in the write FIFO
203
            0x10
204
            16
205
            read-only
206
        
207
       
208
     
209
    
210
   
211
  
212
      DE0_NANO_SOC_QSYS_sysid_qsys_control_slave_altera_avalon_sysid0x00000000
213
      
214
        0x0
215
        8
216
        registers
217
      
218
      
219
        
220
         ID
221
         System ID
222
            A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.
223
         0x0
224
         32
225
         read-only
226
         ${sysid_id_value}
227
         0xffffffff
228
         
229
           id
230
            0x0
231
            32
232
            read-only
233
        
234
       
235
     
236
        
237
         TIMESTAMP
238
         Time stamp
239
         A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.
240
         0x4
241
         32
242
         read-only
243
         ${sysid_timestamp_value}
244
         0xffffffff
245
         
246
           timestamp
247
            0x0
248
            32
249
            read-only
250
        
251
       
252
     
253
    
254
   
255
  
256

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.