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olivier.gi |
// DE0_NANO_SOC_QSYS.v
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// Generated using ACDS version 14.0 209 at 2014.12.18.15:52:20
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`timescale 1 ps / 1 ps
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module DE0_NANO_SOC_QSYS (
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input wire clk_clk, // clk.clk
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input wire reset_reset_n, // reset.reset_n
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output wire adc_ltc2308_conduit_end_CONVST, // adc_ltc2308_conduit_end.CONVST
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output wire adc_ltc2308_conduit_end_SCK, // .SCK
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output wire adc_ltc2308_conduit_end_SDI, // .SDI
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input wire adc_ltc2308_conduit_end_SDO, // .SDO
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input wire [9:0] sw_external_connection_export, // sw_external_connection.export
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output wire pll_sys_locked_export, // pll_sys_locked.export
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output wire pll_sys_outclk2_clk // pll_sys_outclk2.clk
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);
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wire pll_sys_outclk0_clk; // pll_sys:outclk_0 -> [adc_ltc2308:slave_clk, irq_mapper:clk, jtag_uart:clk, mm_interconnect_0:pll_sys_outclk0_clk, nios2_qsys:clk, onchip_memory2:clk, rst_controller:clk, rst_controller_001:clk, sw:clk, sysid_qsys:clock]
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wire pll_sys_outclk1_clk; // pll_sys:outclk_1 -> adc_ltc2308:adc_clk
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wire nios2_qsys_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_instruction_master_waitrequest -> nios2_qsys:i_waitrequest
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wire [19:0] nios2_qsys_instruction_master_address; // nios2_qsys:i_address -> mm_interconnect_0:nios2_qsys_instruction_master_address
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wire nios2_qsys_instruction_master_read; // nios2_qsys:i_read -> mm_interconnect_0:nios2_qsys_instruction_master_read
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wire [31:0] nios2_qsys_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_instruction_master_readdata -> nios2_qsys:i_readdata
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wire nios2_qsys_instruction_master_readdatavalid; // mm_interconnect_0:nios2_qsys_instruction_master_readdatavalid -> nios2_qsys:i_readdatavalid
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wire nios2_qsys_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_data_master_waitrequest -> nios2_qsys:d_waitrequest
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wire [31:0] nios2_qsys_data_master_writedata; // nios2_qsys:d_writedata -> mm_interconnect_0:nios2_qsys_data_master_writedata
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wire [19:0] nios2_qsys_data_master_address; // nios2_qsys:d_address -> mm_interconnect_0:nios2_qsys_data_master_address
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wire nios2_qsys_data_master_write; // nios2_qsys:d_write -> mm_interconnect_0:nios2_qsys_data_master_write
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wire nios2_qsys_data_master_read; // nios2_qsys:d_read -> mm_interconnect_0:nios2_qsys_data_master_read
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wire [31:0] nios2_qsys_data_master_readdata; // mm_interconnect_0:nios2_qsys_data_master_readdata -> nios2_qsys:d_readdata
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wire nios2_qsys_data_master_debugaccess; // nios2_qsys:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_data_master_debugaccess
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wire nios2_qsys_data_master_readdatavalid; // mm_interconnect_0:nios2_qsys_data_master_readdatavalid -> nios2_qsys:d_readdatavalid
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wire [3:0] nios2_qsys_data_master_byteenable; // nios2_qsys:d_byteenable -> mm_interconnect_0:nios2_qsys_data_master_byteenable
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wire mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest; // nios2_qsys:jtag_debug_module_waitrequest -> mm_interconnect_0:nios2_qsys_jtag_debug_module_waitrequest
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wire [31:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata; // mm_interconnect_0:nios2_qsys_jtag_debug_module_writedata -> nios2_qsys:jtag_debug_module_writedata
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wire [8:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_address; // mm_interconnect_0:nios2_qsys_jtag_debug_module_address -> nios2_qsys:jtag_debug_module_address
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wire mm_interconnect_0_nios2_qsys_jtag_debug_module_write; // mm_interconnect_0:nios2_qsys_jtag_debug_module_write -> nios2_qsys:jtag_debug_module_write
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wire mm_interconnect_0_nios2_qsys_jtag_debug_module_read; // mm_interconnect_0:nios2_qsys_jtag_debug_module_read -> nios2_qsys:jtag_debug_module_read
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wire [31:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata; // nios2_qsys:jtag_debug_module_readdata -> mm_interconnect_0:nios2_qsys_jtag_debug_module_readdata
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wire mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess; // mm_interconnect_0:nios2_qsys_jtag_debug_module_debugaccess -> nios2_qsys:jtag_debug_module_debugaccess
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wire [3:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable; // mm_interconnect_0:nios2_qsys_jtag_debug_module_byteenable -> nios2_qsys:jtag_debug_module_byteenable
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wire [31:0] mm_interconnect_0_onchip_memory2_s1_writedata; // mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata
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wire [15:0] mm_interconnect_0_onchip_memory2_s1_address; // mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address
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wire mm_interconnect_0_onchip_memory2_s1_chipselect; // mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect
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wire mm_interconnect_0_onchip_memory2_s1_clken; // mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken
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wire mm_interconnect_0_onchip_memory2_s1_write; // mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write
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wire [31:0] mm_interconnect_0_onchip_memory2_s1_readdata; // onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata
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wire [3:0] mm_interconnect_0_onchip_memory2_s1_byteenable; // mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable
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wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
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wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
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wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
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wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
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wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
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wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
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wire [15:0] mm_interconnect_0_adc_ltc2308_slave_writedata; // mm_interconnect_0:adc_ltc2308_slave_writedata -> adc_ltc2308:slave_wriredata
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wire [0:0] mm_interconnect_0_adc_ltc2308_slave_address; // mm_interconnect_0:adc_ltc2308_slave_address -> adc_ltc2308:slave_addr
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wire mm_interconnect_0_adc_ltc2308_slave_chipselect; // mm_interconnect_0:adc_ltc2308_slave_chipselect -> adc_ltc2308:slave_chipselect_n
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wire mm_interconnect_0_adc_ltc2308_slave_write; // mm_interconnect_0:adc_ltc2308_slave_write -> adc_ltc2308:slave_wrtie_n
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wire mm_interconnect_0_adc_ltc2308_slave_read; // mm_interconnect_0:adc_ltc2308_slave_read -> adc_ltc2308:slave_read_n
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wire [15:0] mm_interconnect_0_adc_ltc2308_slave_readdata; // adc_ltc2308:slave_readdata -> mm_interconnect_0:adc_ltc2308_slave_readdata
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wire [31:0] mm_interconnect_0_sw_s1_writedata; // mm_interconnect_0:sw_s1_writedata -> sw:writedata
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wire [1:0] mm_interconnect_0_sw_s1_address; // mm_interconnect_0:sw_s1_address -> sw:address
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wire mm_interconnect_0_sw_s1_chipselect; // mm_interconnect_0:sw_s1_chipselect -> sw:chipselect
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wire mm_interconnect_0_sw_s1_write; // mm_interconnect_0:sw_s1_write -> sw:write_n
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wire [31:0] mm_interconnect_0_sw_s1_readdata; // sw:readdata -> mm_interconnect_0:sw_s1_readdata
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wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq
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wire irq_mapper_receiver1_irq; // sw:irq -> irq_mapper:receiver1_irq
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wire [31:0] nios2_qsys_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys:d_irq
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_qsys_reset_n_reset_bridge_in_reset_reset, nios2_qsys:reset_n]
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wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys:reset_req, rst_translator:reset_req_in]
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wire nios2_qsys_jtag_debug_module_reset_reset; // nios2_qsys:jtag_debug_module_resetrequest -> rst_controller:reset_in1
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wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [adc_ltc2308:slave_reset_n, jtag_uart:rst_n, mm_interconnect_0:onchip_memory2_reset1_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_translator_001:in_reset, sw:reset_n, sysid_qsys:reset_n]
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wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [onchip_memory2:reset_req, rst_translator_001:reset_req_in]
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wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> pll_sys:rst
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DE0_NANO_SOC_QSYS_nios2_qsys nios2_qsys (
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.clk (pll_sys_outclk0_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
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.reset_req (rst_controller_reset_out_reset_req), // .reset_req
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.d_address (nios2_qsys_data_master_address), // data_master.address
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.d_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
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.d_read (nios2_qsys_data_master_read), // .read
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.d_readdata (nios2_qsys_data_master_readdata), // .readdata
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.d_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
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.d_write (nios2_qsys_data_master_write), // .write
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.d_writedata (nios2_qsys_data_master_writedata), // .writedata
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.d_readdatavalid (nios2_qsys_data_master_readdatavalid), // .readdatavalid
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.jtag_debug_module_debugaccess_to_roms (nios2_qsys_data_master_debugaccess), // .debugaccess
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.i_address (nios2_qsys_instruction_master_address), // instruction_master.address
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.i_read (nios2_qsys_instruction_master_read), // .read
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.i_readdata (nios2_qsys_instruction_master_readdata), // .readdata
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.i_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
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.i_readdatavalid (nios2_qsys_instruction_master_readdatavalid), // .readdatavalid
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.d_irq (nios2_qsys_d_irq_irq), // d_irq.irq
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.jtag_debug_module_resetrequest (nios2_qsys_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
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.jtag_debug_module_address (mm_interconnect_0_nios2_qsys_jtag_debug_module_address), // jtag_debug_module.address
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.jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable), // .byteenable
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.jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
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.jtag_debug_module_read (mm_interconnect_0_nios2_qsys_jtag_debug_module_read), // .read
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.jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata), // .readdata
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.jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
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.jtag_debug_module_write (mm_interconnect_0_nios2_qsys_jtag_debug_module_write), // .write
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.jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata), // .writedata
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.no_ci_readra () // custom_instruction_master.readra
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);
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DE0_NANO_SOC_QSYS_onchip_memory2 onchip_memory2 (
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.clk (pll_sys_outclk0_clk), // clk1.clk
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.address (mm_interconnect_0_onchip_memory2_s1_address), // s1.address
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.clken (mm_interconnect_0_onchip_memory2_s1_clken), // .clken
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.chipselect (mm_interconnect_0_onchip_memory2_s1_chipselect), // .chipselect
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.write (mm_interconnect_0_onchip_memory2_s1_write), // .write
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.readdata (mm_interconnect_0_onchip_memory2_s1_readdata), // .readdata
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.writedata (mm_interconnect_0_onchip_memory2_s1_writedata), // .writedata
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.byteenable (mm_interconnect_0_onchip_memory2_s1_byteenable), // .byteenable
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.reset (rst_controller_001_reset_out_reset), // reset1.reset
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.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
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);
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DE0_NANO_SOC_QSYS_sysid_qsys sysid_qsys (
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.clock (pll_sys_outclk0_clk), // clk.clk
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.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
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.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
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.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
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);
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DE0_NANO_SOC_QSYS_jtag_uart jtag_uart (
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.clk (pll_sys_outclk0_clk), // clk.clk
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.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
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.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
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.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
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.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
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.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
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.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
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.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
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.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
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.av_irq (irq_mapper_receiver0_irq) // irq.irq
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);
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DE0_NANO_SOC_QSYS_pll_sys pll_sys (
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.refclk (clk_clk), // refclk.clk
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.rst (rst_controller_002_reset_out_reset), // reset.reset
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.outclk_0 (pll_sys_outclk0_clk), // outclk0.clk
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.outclk_1 (pll_sys_outclk1_clk), // outclk1.clk
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.outclk_2 (pll_sys_outclk2_clk), // outclk2.clk
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.locked (pll_sys_locked_export) // locked.export
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);
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adc_ltc2308_fifo adc_ltc2308 (
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.slave_chipselect_n (~mm_interconnect_0_adc_ltc2308_slave_chipselect), // slave.chipselect_n
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.slave_read_n (~mm_interconnect_0_adc_ltc2308_slave_read), // .read_n
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.slave_readdata (mm_interconnect_0_adc_ltc2308_slave_readdata), // .readdata
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.slave_addr (mm_interconnect_0_adc_ltc2308_slave_address), // .address
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.slave_wrtie_n (~mm_interconnect_0_adc_ltc2308_slave_write), // .write_n
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.slave_wriredata (mm_interconnect_0_adc_ltc2308_slave_writedata), // .writedata
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.ADC_CONVST (adc_ltc2308_conduit_end_CONVST), // conduit_end.export
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.ADC_SCK (adc_ltc2308_conduit_end_SCK), // .export
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.ADC_SDI (adc_ltc2308_conduit_end_SDI), // .export
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.ADC_SDO (adc_ltc2308_conduit_end_SDO), // .export
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.slave_reset_n (~rst_controller_001_reset_out_reset), // reset_sink.reset_n
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.slave_clk (pll_sys_outclk0_clk), // clock_sink.clk
|
| 165 |
|
|
.adc_clk (pll_sys_outclk1_clk) // clock_sink_adc.clk
|
| 166 |
|
|
);
|
| 167 |
|
|
|
| 168 |
|
|
DE0_NANO_SOC_QSYS_sw sw (
|
| 169 |
|
|
.clk (pll_sys_outclk0_clk), // clk.clk
|
| 170 |
|
|
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
|
| 171 |
|
|
.address (mm_interconnect_0_sw_s1_address), // s1.address
|
| 172 |
|
|
.write_n (~mm_interconnect_0_sw_s1_write), // .write_n
|
| 173 |
|
|
.writedata (mm_interconnect_0_sw_s1_writedata), // .writedata
|
| 174 |
|
|
.chipselect (mm_interconnect_0_sw_s1_chipselect), // .chipselect
|
| 175 |
|
|
.readdata (mm_interconnect_0_sw_s1_readdata), // .readdata
|
| 176 |
|
|
.in_port (sw_external_connection_export), // external_connection.export
|
| 177 |
|
|
.irq (irq_mapper_receiver1_irq) // irq.irq
|
| 178 |
|
|
);
|
| 179 |
|
|
|
| 180 |
|
|
DE0_NANO_SOC_QSYS_mm_interconnect_0 mm_interconnect_0 (
|
| 181 |
|
|
.pll_sys_outclk0_clk (pll_sys_outclk0_clk), // pll_sys_outclk0.clk
|
| 182 |
|
|
.nios2_qsys_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_reset_n_reset_bridge_in_reset.reset
|
| 183 |
|
|
.onchip_memory2_reset1_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // onchip_memory2_reset1_reset_bridge_in_reset.reset
|
| 184 |
|
|
.nios2_qsys_data_master_address (nios2_qsys_data_master_address), // nios2_qsys_data_master.address
|
| 185 |
|
|
.nios2_qsys_data_master_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
|
| 186 |
|
|
.nios2_qsys_data_master_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
|
| 187 |
|
|
.nios2_qsys_data_master_read (nios2_qsys_data_master_read), // .read
|
| 188 |
|
|
.nios2_qsys_data_master_readdata (nios2_qsys_data_master_readdata), // .readdata
|
| 189 |
|
|
.nios2_qsys_data_master_readdatavalid (nios2_qsys_data_master_readdatavalid), // .readdatavalid
|
| 190 |
|
|
.nios2_qsys_data_master_write (nios2_qsys_data_master_write), // .write
|
| 191 |
|
|
.nios2_qsys_data_master_writedata (nios2_qsys_data_master_writedata), // .writedata
|
| 192 |
|
|
.nios2_qsys_data_master_debugaccess (nios2_qsys_data_master_debugaccess), // .debugaccess
|
| 193 |
|
|
.nios2_qsys_instruction_master_address (nios2_qsys_instruction_master_address), // nios2_qsys_instruction_master.address
|
| 194 |
|
|
.nios2_qsys_instruction_master_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
|
| 195 |
|
|
.nios2_qsys_instruction_master_read (nios2_qsys_instruction_master_read), // .read
|
| 196 |
|
|
.nios2_qsys_instruction_master_readdata (nios2_qsys_instruction_master_readdata), // .readdata
|
| 197 |
|
|
.nios2_qsys_instruction_master_readdatavalid (nios2_qsys_instruction_master_readdatavalid), // .readdatavalid
|
| 198 |
|
|
.adc_ltc2308_slave_address (mm_interconnect_0_adc_ltc2308_slave_address), // adc_ltc2308_slave.address
|
| 199 |
|
|
.adc_ltc2308_slave_write (mm_interconnect_0_adc_ltc2308_slave_write), // .write
|
| 200 |
|
|
.adc_ltc2308_slave_read (mm_interconnect_0_adc_ltc2308_slave_read), // .read
|
| 201 |
|
|
.adc_ltc2308_slave_readdata (mm_interconnect_0_adc_ltc2308_slave_readdata), // .readdata
|
| 202 |
|
|
.adc_ltc2308_slave_writedata (mm_interconnect_0_adc_ltc2308_slave_writedata), // .writedata
|
| 203 |
|
|
.adc_ltc2308_slave_chipselect (mm_interconnect_0_adc_ltc2308_slave_chipselect), // .chipselect
|
| 204 |
|
|
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
|
| 205 |
|
|
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
|
| 206 |
|
|
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
|
| 207 |
|
|
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
|
| 208 |
|
|
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
|
| 209 |
|
|
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
|
| 210 |
|
|
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
|
| 211 |
|
|
.nios2_qsys_jtag_debug_module_address (mm_interconnect_0_nios2_qsys_jtag_debug_module_address), // nios2_qsys_jtag_debug_module.address
|
| 212 |
|
|
.nios2_qsys_jtag_debug_module_write (mm_interconnect_0_nios2_qsys_jtag_debug_module_write), // .write
|
| 213 |
|
|
.nios2_qsys_jtag_debug_module_read (mm_interconnect_0_nios2_qsys_jtag_debug_module_read), // .read
|
| 214 |
|
|
.nios2_qsys_jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata), // .readdata
|
| 215 |
|
|
.nios2_qsys_jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata), // .writedata
|
| 216 |
|
|
.nios2_qsys_jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable), // .byteenable
|
| 217 |
|
|
.nios2_qsys_jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
|
| 218 |
|
|
.nios2_qsys_jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
|
| 219 |
|
|
.onchip_memory2_s1_address (mm_interconnect_0_onchip_memory2_s1_address), // onchip_memory2_s1.address
|
| 220 |
|
|
.onchip_memory2_s1_write (mm_interconnect_0_onchip_memory2_s1_write), // .write
|
| 221 |
|
|
.onchip_memory2_s1_readdata (mm_interconnect_0_onchip_memory2_s1_readdata), // .readdata
|
| 222 |
|
|
.onchip_memory2_s1_writedata (mm_interconnect_0_onchip_memory2_s1_writedata), // .writedata
|
| 223 |
|
|
.onchip_memory2_s1_byteenable (mm_interconnect_0_onchip_memory2_s1_byteenable), // .byteenable
|
| 224 |
|
|
.onchip_memory2_s1_chipselect (mm_interconnect_0_onchip_memory2_s1_chipselect), // .chipselect
|
| 225 |
|
|
.onchip_memory2_s1_clken (mm_interconnect_0_onchip_memory2_s1_clken), // .clken
|
| 226 |
|
|
.sw_s1_address (mm_interconnect_0_sw_s1_address), // sw_s1.address
|
| 227 |
|
|
.sw_s1_write (mm_interconnect_0_sw_s1_write), // .write
|
| 228 |
|
|
.sw_s1_readdata (mm_interconnect_0_sw_s1_readdata), // .readdata
|
| 229 |
|
|
.sw_s1_writedata (mm_interconnect_0_sw_s1_writedata), // .writedata
|
| 230 |
|
|
.sw_s1_chipselect (mm_interconnect_0_sw_s1_chipselect), // .chipselect
|
| 231 |
|
|
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
|
| 232 |
|
|
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
|
| 233 |
|
|
);
|
| 234 |
|
|
|
| 235 |
|
|
DE0_NANO_SOC_QSYS_irq_mapper irq_mapper (
|
| 236 |
|
|
.clk (pll_sys_outclk0_clk), // clk.clk
|
| 237 |
|
|
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
| 238 |
|
|
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
|
| 239 |
|
|
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
|
| 240 |
|
|
.sender_irq (nios2_qsys_d_irq_irq) // sender.irq
|
| 241 |
|
|
);
|
| 242 |
|
|
|
| 243 |
|
|
altera_reset_controller #(
|
| 244 |
|
|
.NUM_RESET_INPUTS (2),
|
| 245 |
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
| 246 |
|
|
.SYNC_DEPTH (2),
|
| 247 |
|
|
.RESET_REQUEST_PRESENT (1),
|
| 248 |
|
|
.RESET_REQ_WAIT_TIME (1),
|
| 249 |
|
|
.MIN_RST_ASSERTION_TIME (3),
|
| 250 |
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
| 251 |
|
|
.USE_RESET_REQUEST_IN0 (0),
|
| 252 |
|
|
.USE_RESET_REQUEST_IN1 (0),
|
| 253 |
|
|
.USE_RESET_REQUEST_IN2 (0),
|
| 254 |
|
|
.USE_RESET_REQUEST_IN3 (0),
|
| 255 |
|
|
.USE_RESET_REQUEST_IN4 (0),
|
| 256 |
|
|
.USE_RESET_REQUEST_IN5 (0),
|
| 257 |
|
|
.USE_RESET_REQUEST_IN6 (0),
|
| 258 |
|
|
.USE_RESET_REQUEST_IN7 (0),
|
| 259 |
|
|
.USE_RESET_REQUEST_IN8 (0),
|
| 260 |
|
|
.USE_RESET_REQUEST_IN9 (0),
|
| 261 |
|
|
.USE_RESET_REQUEST_IN10 (0),
|
| 262 |
|
|
.USE_RESET_REQUEST_IN11 (0),
|
| 263 |
|
|
.USE_RESET_REQUEST_IN12 (0),
|
| 264 |
|
|
.USE_RESET_REQUEST_IN13 (0),
|
| 265 |
|
|
.USE_RESET_REQUEST_IN14 (0),
|
| 266 |
|
|
.USE_RESET_REQUEST_IN15 (0),
|
| 267 |
|
|
.ADAPT_RESET_REQUEST (0)
|
| 268 |
|
|
) rst_controller (
|
| 269 |
|
|
.reset_in0 (~reset_reset_n), // reset_in0.reset
|
| 270 |
|
|
.reset_in1 (nios2_qsys_jtag_debug_module_reset_reset), // reset_in1.reset
|
| 271 |
|
|
.clk (pll_sys_outclk0_clk), // clk.clk
|
| 272 |
|
|
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
| 273 |
|
|
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
|
| 274 |
|
|
.reset_req_in0 (1'b0), // (terminated)
|
| 275 |
|
|
.reset_req_in1 (1'b0), // (terminated)
|
| 276 |
|
|
.reset_in2 (1'b0), // (terminated)
|
| 277 |
|
|
.reset_req_in2 (1'b0), // (terminated)
|
| 278 |
|
|
.reset_in3 (1'b0), // (terminated)
|
| 279 |
|
|
.reset_req_in3 (1'b0), // (terminated)
|
| 280 |
|
|
.reset_in4 (1'b0), // (terminated)
|
| 281 |
|
|
.reset_req_in4 (1'b0), // (terminated)
|
| 282 |
|
|
.reset_in5 (1'b0), // (terminated)
|
| 283 |
|
|
.reset_req_in5 (1'b0), // (terminated)
|
| 284 |
|
|
.reset_in6 (1'b0), // (terminated)
|
| 285 |
|
|
.reset_req_in6 (1'b0), // (terminated)
|
| 286 |
|
|
.reset_in7 (1'b0), // (terminated)
|
| 287 |
|
|
.reset_req_in7 (1'b0), // (terminated)
|
| 288 |
|
|
.reset_in8 (1'b0), // (terminated)
|
| 289 |
|
|
.reset_req_in8 (1'b0), // (terminated)
|
| 290 |
|
|
.reset_in9 (1'b0), // (terminated)
|
| 291 |
|
|
.reset_req_in9 (1'b0), // (terminated)
|
| 292 |
|
|
.reset_in10 (1'b0), // (terminated)
|
| 293 |
|
|
.reset_req_in10 (1'b0), // (terminated)
|
| 294 |
|
|
.reset_in11 (1'b0), // (terminated)
|
| 295 |
|
|
.reset_req_in11 (1'b0), // (terminated)
|
| 296 |
|
|
.reset_in12 (1'b0), // (terminated)
|
| 297 |
|
|
.reset_req_in12 (1'b0), // (terminated)
|
| 298 |
|
|
.reset_in13 (1'b0), // (terminated)
|
| 299 |
|
|
.reset_req_in13 (1'b0), // (terminated)
|
| 300 |
|
|
.reset_in14 (1'b0), // (terminated)
|
| 301 |
|
|
.reset_req_in14 (1'b0), // (terminated)
|
| 302 |
|
|
.reset_in15 (1'b0), // (terminated)
|
| 303 |
|
|
.reset_req_in15 (1'b0) // (terminated)
|
| 304 |
|
|
);
|
| 305 |
|
|
|
| 306 |
|
|
altera_reset_controller #(
|
| 307 |
|
|
.NUM_RESET_INPUTS (1),
|
| 308 |
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
| 309 |
|
|
.SYNC_DEPTH (2),
|
| 310 |
|
|
.RESET_REQUEST_PRESENT (1),
|
| 311 |
|
|
.RESET_REQ_WAIT_TIME (1),
|
| 312 |
|
|
.MIN_RST_ASSERTION_TIME (3),
|
| 313 |
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
| 314 |
|
|
.USE_RESET_REQUEST_IN0 (0),
|
| 315 |
|
|
.USE_RESET_REQUEST_IN1 (0),
|
| 316 |
|
|
.USE_RESET_REQUEST_IN2 (0),
|
| 317 |
|
|
.USE_RESET_REQUEST_IN3 (0),
|
| 318 |
|
|
.USE_RESET_REQUEST_IN4 (0),
|
| 319 |
|
|
.USE_RESET_REQUEST_IN5 (0),
|
| 320 |
|
|
.USE_RESET_REQUEST_IN6 (0),
|
| 321 |
|
|
.USE_RESET_REQUEST_IN7 (0),
|
| 322 |
|
|
.USE_RESET_REQUEST_IN8 (0),
|
| 323 |
|
|
.USE_RESET_REQUEST_IN9 (0),
|
| 324 |
|
|
.USE_RESET_REQUEST_IN10 (0),
|
| 325 |
|
|
.USE_RESET_REQUEST_IN11 (0),
|
| 326 |
|
|
.USE_RESET_REQUEST_IN12 (0),
|
| 327 |
|
|
.USE_RESET_REQUEST_IN13 (0),
|
| 328 |
|
|
.USE_RESET_REQUEST_IN14 (0),
|
| 329 |
|
|
.USE_RESET_REQUEST_IN15 (0),
|
| 330 |
|
|
.ADAPT_RESET_REQUEST (0)
|
| 331 |
|
|
) rst_controller_001 (
|
| 332 |
|
|
.reset_in0 (~reset_reset_n), // reset_in0.reset
|
| 333 |
|
|
.clk (pll_sys_outclk0_clk), // clk.clk
|
| 334 |
|
|
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
|
| 335 |
|
|
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
|
| 336 |
|
|
.reset_req_in0 (1'b0), // (terminated)
|
| 337 |
|
|
.reset_in1 (1'b0), // (terminated)
|
| 338 |
|
|
.reset_req_in1 (1'b0), // (terminated)
|
| 339 |
|
|
.reset_in2 (1'b0), // (terminated)
|
| 340 |
|
|
.reset_req_in2 (1'b0), // (terminated)
|
| 341 |
|
|
.reset_in3 (1'b0), // (terminated)
|
| 342 |
|
|
.reset_req_in3 (1'b0), // (terminated)
|
| 343 |
|
|
.reset_in4 (1'b0), // (terminated)
|
| 344 |
|
|
.reset_req_in4 (1'b0), // (terminated)
|
| 345 |
|
|
.reset_in5 (1'b0), // (terminated)
|
| 346 |
|
|
.reset_req_in5 (1'b0), // (terminated)
|
| 347 |
|
|
.reset_in6 (1'b0), // (terminated)
|
| 348 |
|
|
.reset_req_in6 (1'b0), // (terminated)
|
| 349 |
|
|
.reset_in7 (1'b0), // (terminated)
|
| 350 |
|
|
.reset_req_in7 (1'b0), // (terminated)
|
| 351 |
|
|
.reset_in8 (1'b0), // (terminated)
|
| 352 |
|
|
.reset_req_in8 (1'b0), // (terminated)
|
| 353 |
|
|
.reset_in9 (1'b0), // (terminated)
|
| 354 |
|
|
.reset_req_in9 (1'b0), // (terminated)
|
| 355 |
|
|
.reset_in10 (1'b0), // (terminated)
|
| 356 |
|
|
.reset_req_in10 (1'b0), // (terminated)
|
| 357 |
|
|
.reset_in11 (1'b0), // (terminated)
|
| 358 |
|
|
.reset_req_in11 (1'b0), // (terminated)
|
| 359 |
|
|
.reset_in12 (1'b0), // (terminated)
|
| 360 |
|
|
.reset_req_in12 (1'b0), // (terminated)
|
| 361 |
|
|
.reset_in13 (1'b0), // (terminated)
|
| 362 |
|
|
.reset_req_in13 (1'b0), // (terminated)
|
| 363 |
|
|
.reset_in14 (1'b0), // (terminated)
|
| 364 |
|
|
.reset_req_in14 (1'b0), // (terminated)
|
| 365 |
|
|
.reset_in15 (1'b0), // (terminated)
|
| 366 |
|
|
.reset_req_in15 (1'b0) // (terminated)
|
| 367 |
|
|
);
|
| 368 |
|
|
|
| 369 |
|
|
altera_reset_controller #(
|
| 370 |
|
|
.NUM_RESET_INPUTS (1),
|
| 371 |
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
| 372 |
|
|
.SYNC_DEPTH (2),
|
| 373 |
|
|
.RESET_REQUEST_PRESENT (0),
|
| 374 |
|
|
.RESET_REQ_WAIT_TIME (1),
|
| 375 |
|
|
.MIN_RST_ASSERTION_TIME (3),
|
| 376 |
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
| 377 |
|
|
.USE_RESET_REQUEST_IN0 (0),
|
| 378 |
|
|
.USE_RESET_REQUEST_IN1 (0),
|
| 379 |
|
|
.USE_RESET_REQUEST_IN2 (0),
|
| 380 |
|
|
.USE_RESET_REQUEST_IN3 (0),
|
| 381 |
|
|
.USE_RESET_REQUEST_IN4 (0),
|
| 382 |
|
|
.USE_RESET_REQUEST_IN5 (0),
|
| 383 |
|
|
.USE_RESET_REQUEST_IN6 (0),
|
| 384 |
|
|
.USE_RESET_REQUEST_IN7 (0),
|
| 385 |
|
|
.USE_RESET_REQUEST_IN8 (0),
|
| 386 |
|
|
.USE_RESET_REQUEST_IN9 (0),
|
| 387 |
|
|
.USE_RESET_REQUEST_IN10 (0),
|
| 388 |
|
|
.USE_RESET_REQUEST_IN11 (0),
|
| 389 |
|
|
.USE_RESET_REQUEST_IN12 (0),
|
| 390 |
|
|
.USE_RESET_REQUEST_IN13 (0),
|
| 391 |
|
|
.USE_RESET_REQUEST_IN14 (0),
|
| 392 |
|
|
.USE_RESET_REQUEST_IN15 (0),
|
| 393 |
|
|
.ADAPT_RESET_REQUEST (0)
|
| 394 |
|
|
) rst_controller_002 (
|
| 395 |
|
|
.reset_in0 (~reset_reset_n), // reset_in0.reset
|
| 396 |
|
|
.clk (clk_clk), // clk.clk
|
| 397 |
|
|
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
|
| 398 |
|
|
.reset_req (), // (terminated)
|
| 399 |
|
|
.reset_req_in0 (1'b0), // (terminated)
|
| 400 |
|
|
.reset_in1 (1'b0), // (terminated)
|
| 401 |
|
|
.reset_req_in1 (1'b0), // (terminated)
|
| 402 |
|
|
.reset_in2 (1'b0), // (terminated)
|
| 403 |
|
|
.reset_req_in2 (1'b0), // (terminated)
|
| 404 |
|
|
.reset_in3 (1'b0), // (terminated)
|
| 405 |
|
|
.reset_req_in3 (1'b0), // (terminated)
|
| 406 |
|
|
.reset_in4 (1'b0), // (terminated)
|
| 407 |
|
|
.reset_req_in4 (1'b0), // (terminated)
|
| 408 |
|
|
.reset_in5 (1'b0), // (terminated)
|
| 409 |
|
|
.reset_req_in5 (1'b0), // (terminated)
|
| 410 |
|
|
.reset_in6 (1'b0), // (terminated)
|
| 411 |
|
|
.reset_req_in6 (1'b0), // (terminated)
|
| 412 |
|
|
.reset_in7 (1'b0), // (terminated)
|
| 413 |
|
|
.reset_req_in7 (1'b0), // (terminated)
|
| 414 |
|
|
.reset_in8 (1'b0), // (terminated)
|
| 415 |
|
|
.reset_req_in8 (1'b0), // (terminated)
|
| 416 |
|
|
.reset_in9 (1'b0), // (terminated)
|
| 417 |
|
|
.reset_req_in9 (1'b0), // (terminated)
|
| 418 |
|
|
.reset_in10 (1'b0), // (terminated)
|
| 419 |
|
|
.reset_req_in10 (1'b0), // (terminated)
|
| 420 |
|
|
.reset_in11 (1'b0), // (terminated)
|
| 421 |
|
|
.reset_req_in11 (1'b0), // (terminated)
|
| 422 |
|
|
.reset_in12 (1'b0), // (terminated)
|
| 423 |
|
|
.reset_req_in12 (1'b0), // (terminated)
|
| 424 |
|
|
.reset_in13 (1'b0), // (terminated)
|
| 425 |
|
|
.reset_req_in13 (1'b0), // (terminated)
|
| 426 |
|
|
.reset_in14 (1'b0), // (terminated)
|
| 427 |
|
|
.reset_req_in14 (1'b0), // (terminated)
|
| 428 |
|
|
.reset_in15 (1'b0), // (terminated)
|
| 429 |
|
|
.reset_req_in15 (1'b0) // (terminated)
|
| 430 |
|
|
);
|
| 431 |
|
|
|
| 432 |
|
|
endmodule
|
