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1 221 olivier.gi
// (C) 2001-2014 Altera Corporation. All rights reserved.
2
// Your use of Altera Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors.  Please refer to the applicable
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// agreement for further details.
12
 
13
 
14
// $Id: //acds/rel/14.0/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
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// $Revision: #1 $
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// $Date: 2014/02/16 $
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// $Author: swbranch $
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19
// --------------------------------------
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// Merlin Master Agent
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//
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// Converts Avalon-MM transactions into
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// Merlin network packets.
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// --------------------------------------
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26
`timescale 1 ns / 1 ns
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28
module altera_merlin_master_agent
29
#(
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    // -------------------
31
    // Packet Format Parameters
32
    // -------------------
33
    parameter PKT_QOS_H            = 109,
34
              PKT_QOS_L            = 106,
35
              PKT_DATA_SIDEBAND_H  = 105,
36
              PKT_DATA_SIDEBAND_L  = 98,
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              PKT_ADDR_SIDEBAND_H  = 97,
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              PKT_ADDR_SIDEBAND_L  = 93,
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              PKT_CACHE_H          = 92,
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              PKT_CACHE_L          = 89,
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              PKT_THREAD_ID_H      = 88,
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              PKT_THREAD_ID_L      = 87,
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              PKT_BEGIN_BURST      = 81,
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              PKT_PROTECTION_H     = 80,
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              PKT_PROTECTION_L     = 80,
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              PKT_BURSTWRAP_H      = 79,
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              PKT_BURSTWRAP_L      = 77,
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              PKT_BYTE_CNT_H       = 76,
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              PKT_BYTE_CNT_L       = 74,
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              PKT_ADDR_H           = 73,
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              PKT_ADDR_L           = 42,
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              PKT_BURST_SIZE_H     = 86,
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              PKT_BURST_SIZE_L     = 84,
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              PKT_BURST_TYPE_H     = 94,
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              PKT_BURST_TYPE_L     = 93,
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              PKT_TRANS_EXCLUSIVE  = 83,
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              PKT_TRANS_LOCK       = 82,
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              PKT_TRANS_COMPRESSED_READ = 41,
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              PKT_TRANS_POSTED     = 40,
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              PKT_TRANS_WRITE      = 39,
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              PKT_TRANS_READ       = 38,
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              PKT_DATA_H           = 37,
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              PKT_DATA_L           = 6,
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              PKT_BYTEEN_H         = 5,
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              PKT_BYTEEN_L         = 2,
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              PKT_SRC_ID_H         = 1,
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              PKT_SRC_ID_L         = 1,
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              PKT_DEST_ID_H        = 0,
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              PKT_DEST_ID_L        = 0,
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              PKT_RESPONSE_STATUS_L = 110,
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              PKT_RESPONSE_STATUS_H = 111,
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                          PKT_ORI_BURST_SIZE_L  = 112,
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                          PKT_ORI_BURST_SIZE_H  = 114,
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              ST_DATA_W             = 115,
75
              ST_CHANNEL_W          = 1,
76
 
77
    // -------------------
78
    // Agent Parameters
79
    // -------------------
80
              AV_BURSTCOUNT_W       = 3,
81
              ID                    = 1,
82
              SUPPRESS_0_BYTEEN_RSP = 1,
83
              BURSTWRAP_VALUE       = 4,
84
              CACHE_VALUE           = 0,
85
              SECURE_ACCESS_BIT     = 1,
86
              USE_READRESPONSE      = 0,
87
              USE_WRITERESPONSE     = 0,
88
 
89
    // -------------------
90
    // Derived Parameters
91
    // -------------------
92
              PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
93
              PKT_BYTE_CNT_W  = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
94
              PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
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              PKT_ADDR_W      = PKT_ADDR_H - PKT_ADDR_L + 1,
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              PKT_DATA_W      = PKT_DATA_H - PKT_DATA_L + 1,
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              PKT_BYTEEN_W    = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
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              PKT_SRC_ID_W    = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
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              PKT_DEST_ID_W   = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
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              PKT_BURST_SIZE_W= PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
101
)
102
(
103
    // -------------------
104
    // Clock & Reset
105
    // -------------------
106
    input                         clk,
107
    input                         reset,
108
 
109
    // -------------------
110
    // Avalon-MM Anti-Master
111
    // -------------------
112
    input [PKT_ADDR_W-1 : 0]      av_address,
113
    input                         av_write,
114
    input                         av_read,
115
    input [PKT_DATA_W-1 : 0]      av_writedata,
116
    output reg [PKT_DATA_W-1 : 0] av_readdata,
117
    output reg                    av_waitrequest,
118
    output reg                    av_readdatavalid,
119
    input [PKT_BYTEEN_W-1 : 0]    av_byteenable,
120
    input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
121
    input                         av_debugaccess,
122
    input                         av_lock,
123
    output reg [1:0]              av_response,
124
    input                         av_writeresponserequest,
125
    output reg                    av_writeresponsevalid,
126
 
127
    // -------------------
128
    // Command Source
129
    // -------------------
130
    output reg                    cp_valid,
131
    output reg [ST_DATA_W-1 : 0]  cp_data,
132
    output wire                   cp_startofpacket,
133
    output wire                   cp_endofpacket,
134
    input                         cp_ready,
135
 
136
    // -------------------
137
    // Response Sink
138
    // -------------------
139
    input                         rp_valid,
140
    input [ST_DATA_W-1 : 0]       rp_data,
141
    input [ST_CHANNEL_W-1 : 0]    rp_channel,
142
    input                         rp_startofpacket,
143
    input                         rp_endofpacket,
144
    output reg                    rp_ready
145
);
146
    // ------------------------------------------------------------
147
    // Utility Functions
148
    // ------------------------------------------------------------
149
    function integer clogb2;
150
        input [31:0] value;
151
        begin
152
            for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
153
                value = value >> 1;
154
            clogb2 = clogb2 - 1;
155
        end
156
    endfunction // clogb2
157
 
158
    localparam MAX_BURST    = 1 << (AV_BURSTCOUNT_W - 1);
159
    localparam NUMSYMBOLS   = PKT_BYTEEN_W;
160
    localparam BURSTING     = (MAX_BURST > NUMSYMBOLS);
161
    localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
162
    localparam BURST_SIZE   = clogb2(NUMSYMBOLS);
163
 
164
    typedef enum bit  [1:0]
165
    {
166
        FIXED       = 2'b00,
167
        INCR        = 2'b01,
168
        WRAP        = 2'b10,
169
        OTHER_WRAP  = 2'b11
170
    } MerlinBurstType;
171
 
172
    // --------------------------------------
173
    // Potential optimization: compare in words to save bits?
174
    // --------------------------------------
175
    wire is_burst;
176
    assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
177
 
178
    wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE;
179
    wire [31:0] id_int              = ID;
180
    wire [PKT_BURST_SIZE_W-1:0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1:0];
181
    wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
182
 
183
    // --------------------------------------
184
    // Address alignment
185
    //
186
    // The packet format requires that addresses be aligned to
187
    // the transaction size.
188
    // --------------------------------------
189
    wire [PKT_ADDR_W-1 : 0] av_address_aligned;
190
    generate
191
        if (NUMSYMBOLS > 1) begin
192
            assign av_address_aligned =
193
                {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
194
        end
195
        else begin
196
            assign av_address_aligned = av_address;
197
        end
198
    endgenerate
199
 
200
    // --------------------------------------
201
    // Command & Response Construction
202
    // --------------------------------------
203
    always @* begin
204
        cp_data                                            = '0; // default assignment; override below as needed.
205
 
206
        cp_data[PKT_PROTECTION_L]                          = av_debugaccess;
207
        cp_data[PKT_PROTECTION_L+1]                        = SECURE_ACCESS_BIT[0];    // Default Non-secured (AXI)
208
        cp_data[PKT_PROTECTION_L+2]                        = 1'b0;                  // Default Data access (AXI)
209
        cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L  ]         = burstwrap_value_int[PKT_BURSTWRAP_W-1:0];
210
        cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L   ]         = av_burstcount;
211
        cp_data[PKT_ADDR_H     :PKT_ADDR_L       ]         = av_address_aligned;
212
        cp_data[PKT_TRANS_EXCLUSIVE              ]         = 1'b0;
213
        cp_data[PKT_TRANS_LOCK                   ]         = av_lock;
214
        cp_data[PKT_TRANS_COMPRESSED_READ        ]         = av_read & is_burst;
215
        cp_data[PKT_TRANS_READ                   ]         = av_read;
216
        cp_data[PKT_TRANS_WRITE                  ]         = av_write;
217
        // posted and non-posted write avaiable now
218
        cp_data[PKT_TRANS_POSTED                 ]         = av_write & !av_writeresponserequest;
219
        cp_data[PKT_DATA_H     :PKT_DATA_L       ]         = av_writedata;
220
        cp_data[PKT_BYTEEN_H   :PKT_BYTEEN_L     ]         = av_byteenable;
221
        cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]         = burstsize_sig;
222
                cp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L] = burstsize_sig;
223
        cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L]                 = bursttype_value;
224
        cp_data[PKT_SRC_ID_H   :PKT_SRC_ID_L     ]         = id_int[PKT_SRC_ID_W-1:0];
225
        cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L  ]         = '0;
226
        cp_data[PKT_CACHE_H    :PKT_CACHE_L      ]         = CACHE_VALUE[3:0];
227
        cp_data[PKT_QOS_H      : PKT_QOS_L]                = '0;
228
        cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L]   = '0;
229
        cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L]  = '0;
230
 
231
        av_readdata                                        = rp_data[PKT_DATA_H : PKT_DATA_L];
232
        if (USE_WRITERESPONSE || USE_READRESPONSE)
233
            av_response  = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
234
        else
235
            av_response  = '0;
236
 
237
    end
238
 
239
    // --------------------------------------
240
    // Command Control
241
    // --------------------------------------
242
    always @* begin
243
        cp_valid = 0;
244
 
245
        if (av_write || av_read)
246
            cp_valid = 1;
247
    end
248
 
249
    generate if (BURSTING) begin
250
        reg sop_enable;
251
 
252
        always @(posedge clk, posedge reset) begin
253
            if (reset) begin
254
                sop_enable <= 1'b1;
255
            end
256
            else begin
257
                if (cp_valid && cp_ready) begin
258
                    sop_enable <= 1'b0;
259
                    if (cp_endofpacket)
260
                        sop_enable <= 1'b1;
261
                end
262
            end
263
        end
264
 
265
        assign cp_startofpacket = sop_enable;
266
        assign cp_endofpacket   = (av_read) | (av_burstcount == NUMSYMBOLS);
267
 
268
    end
269
    else begin
270
 
271
        assign cp_startofpacket = 1'b1;
272
        assign cp_endofpacket   = 1'b1;
273
 
274
    end
275
    endgenerate
276
 
277
    // --------------------------------------
278
    // Backpressure & Readdatavalid
279
    // --------------------------------------
280
    reg hold_waitrequest;
281
 
282
    always @ (posedge clk, posedge reset) begin
283
        if (reset)
284
            hold_waitrequest <= 1'b1;
285
        else
286
            hold_waitrequest <= 1'b0;
287
    end
288
 
289
    always @* begin
290
        rp_ready               = 1;
291
        av_readdatavalid       = 0;
292
        av_writeresponsevalid  = 0;
293
        av_waitrequest  = hold_waitrequest | !cp_ready;
294
 
295
        // --------------------------------------
296
        // Currently, responses are _always_ read responses because
297
        // this Avalon agent only issues posted writes, which do
298
        // not have responses. -> not true for now
299
        // Now Avalon supports response, so based on type of transaction
300
        // return, assert correct thing
301
        // --------------------------------------
302
        if (rp_data[PKT_TRANS_WRITE] == 1)
303
            av_writeresponsevalid  = rp_valid;
304
        else
305
            av_readdatavalid       = rp_valid;
306
 
307
        if (SUPPRESS_0_BYTEEN_RSP) begin
308
            if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0)
309
                av_readdatavalid = 0;
310
        end
311
    end
312
 
313
endmodule

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